SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/blackfin/kernel/cplb-mpu/cplbmgr.c

   1 /*
   2  * Blackfin CPLB exception handling for when MPU in on
   3  *
   4  * Copyright 2008-2009 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/mm.h>
  11
  12 #include <asm/blackfin.h>
  13 #include <asm/cacheflush.h>
  14 #include <asm/cplb.h>
  15 #include <asm/cplbinit.h>
  16 #include <asm/mmu_context.h>
  17
  18 /*
  19  * WARNING
  20  *
  21  * This file is compiled with certain -ffixed-reg options.  We have to
  22  * make sure not to call any functions here that could clobber these
  23  * registers.
  24  */
  25
  26 int page_mask_nelts;
  27 int page_mask_order;
  28 unsigned long *current_rwx_mask[NR_CPUS];
  29
  30 int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
  31 int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
  32 int nr_cplb_flush[NR_CPUS];
  33
  34 /*
  35  * Given the contents of the status register, return the index of the
  36  * CPLB that caused the fault.
  37  */
  38 static inline int faulting_cplb_index(int status)
  39 {
  40         int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
  41         return 30 - signbits;
  42 }
  43
  44 /*
  45  * Given the contents of the status register and the DCPLB_DATA contents,
  46  * return true if a write access should be permitted.
  47  */
  48 static inline int write_permitted(int status, unsigned long data)
  49 {
  50         if (status & FAULT_USERSUPV)
  51                 return !!(data & CPLB_SUPV_WR);
  52         else
  53                 return !!(data & CPLB_USER_WR);
  54 }
  55
  56 /* Counters to implement round-robin replacement.  */
  57 static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
  58
  59 /*
  60  * Find an ICPLB entry to be evicted and return its index.
  61  */
  62 static int evict_one_icplb(unsigned int cpu)
  63 {
  64         int i;
  65         for (i = first_switched_icplb; i < MAX_CPLBS; i++)
  66                 if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
  67                         return i;
  68         i = first_switched_icplb + icplb_rr_index[cpu];
  69         if (i >= MAX_CPLBS) {
  70                 i -= MAX_CPLBS - first_switched_icplb;
  71                 icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
  72         }
  73         icplb_rr_index[cpu]++;
  74         return i;
  75 }
  76
  77 static int evict_one_dcplb(unsigned int cpu)
  78 {
  79         int i;
  80         for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
  81                 if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
  82                         return i;
  83         i = first_switched_dcplb + dcplb_rr_index[cpu];
  84         if (i >= MAX_CPLBS) {
  85                 i -= MAX_CPLBS - first_switched_dcplb;
  86                 dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
  87         }
  88         dcplb_rr_index[cpu]++;
  89         return i;
  90 }
  91
  92 static noinline int dcplb_miss(unsigned int cpu)
  93 {
  94         unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
  95         int status = bfin_read_DCPLB_STATUS();
  96         unsigned long *mask;
  97         int idx;
  98         unsigned long d_data;
  99
 100         nr_dcplb_miss[cpu]++;
 101
 102         d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 103 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
 104         if (bfin_addr_dcacheable(addr)) {
 105                 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 106 # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
 107                 d_data |= CPLB_L1_AOW | CPLB_WT;
 108 # endif
 109         }
 110 #endif
 111
 112         if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
 113                 addr = L2_START;
 114                 d_data = L2_DMEMORY;
 115         } else if (addr >= physical_mem_end) {
 116                 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
 117                         mask = current_rwx_mask[cpu];
 118                         if (mask) {
 119                                 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
 120                                 int idx = page >> 5;
 121                                 int bit = 1 << (page & 31);
 122
 123                                 if (mask[idx] & bit)
 124                                         d_data |= CPLB_USER_RD;
 125                         }
 126                 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
 127                     && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
 128                         addr &= ~(1 * 1024 * 1024 - 1);
 129                         d_data &= ~PAGE_SIZE_4KB;
 130                         d_data |= PAGE_SIZE_1MB;
 131                 } else
 132                         return CPLB_PROT_VIOL;
 133         } else if (addr >= _ramend) {
 134             d_data |= CPLB_USER_RD | CPLB_USER_WR;
 135         } else {
 136                 mask = current_rwx_mask[cpu];
 137                 if (mask) {
 138                         int page = addr >> PAGE_SHIFT;
 139                         int idx = page >> 5;
 140                         int bit = 1 << (page & 31);
 141
 142                         if (mask[idx] & bit)
 143                                 d_data |= CPLB_USER_RD;
 144
 145                         mask += page_mask_nelts;
 146                         if (mask[idx] & bit)
 147                                 d_data |= CPLB_USER_WR;
 148                 }
 149         }
 150         idx = evict_one_dcplb(cpu);
 151
 152         addr &= PAGE_MASK;
 153         dcplb_tbl[cpu][idx].addr = addr;
 154         dcplb_tbl[cpu][idx].data = d_data;
 155
 156         _disable_dcplb();
 157         bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
 158         bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
 159         _enable_dcplb();
 160
 161         return 0;
 162 }
 163
 164 static noinline int icplb_miss(unsigned int cpu)
 165 {
 166         unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
 167         int status = bfin_read_ICPLB_STATUS();
 168         int idx;
 169         unsigned long i_data;
 170
 171         nr_icplb_miss[cpu]++;
 172
 173         /* If inside the uncached DMA region, fault.  */
 174         if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
 175                 return CPLB_PROT_VIOL;
 176
 177         if (status & FAULT_USERSUPV)
 178                 nr_icplb_supv_miss[cpu]++;
 179
 180         /*
 181          * First, try to find a CPLB that matches this address.  If we
 182          * find one, then the fact that we're in the miss handler means
 183          * that the instruction crosses a page boundary.
 184          */
 185         for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
 186                 if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
 187                         unsigned long this_addr = icplb_tbl[cpu][idx].addr;
 188                         if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
 189                                 addr += PAGE_SIZE;
 190                                 break;
 191                         }
 192                 }
 193         }
 194
 195         i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
 196
 197 #ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
 198         /*
 199          * Normal RAM, and possibly the reserved memory area, are
 200          * cacheable.
 201          */
 202         if (addr < _ramend ||
 203             (addr < physical_mem_end && reserved_mem_icache_on))
 204                 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 205 #endif
 206
 207         if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
 208                 addr = L2_START;
 209                 i_data = L2_IMEMORY;
 210         } else if (addr >= physical_mem_end) {
 211                 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
 212                         if (!(status & FAULT_USERSUPV)) {
 213                                 unsigned long *mask = current_rwx_mask[cpu];
 214
 215                                 if (mask) {
 216                                         int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
 217                                         int idx = page >> 5;
 218                                         int bit = 1 << (page & 31);
 219
 220                                         mask += 2 * page_mask_nelts;
 221                                         if (mask[idx] & bit)
 222                                                 i_data |= CPLB_USER_RD;
 223                                 }
 224                         }
 225                 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
 226                     && (status & FAULT_USERSUPV)) {
 227                         addr &= ~(1 * 1024 * 1024 - 1);
 228                         i_data &= ~PAGE_SIZE_4KB;
 229                         i_data |= PAGE_SIZE_1MB;
 230                 } else
 231                     return CPLB_PROT_VIOL;
 232         } else if (addr >= _ramend) {
 233                 i_data |= CPLB_USER_RD;
 234         } else {
 235                 /*
 236                  * Two cases to distinguish - a supervisor access must
 237                  * necessarily be for a module page; we grant it
 238                  * unconditionally (could do better here in the future).
 239                  * Otherwise, check the x bitmap of the current process.
 240                  */
 241                 if (!(status & FAULT_USERSUPV)) {
 242                         unsigned long *mask = current_rwx_mask[cpu];
 243
 244                         if (mask) {
 245                                 int page = addr >> PAGE_SHIFT;
 246                                 int idx = page >> 5;
 247                                 int bit = 1 << (page & 31);
 248
 249                                 mask += 2 * page_mask_nelts;
 250                                 if (mask[idx] & bit)
 251                                         i_data |= CPLB_USER_RD;
 252                         }
 253                 }
 254         }
 255         idx = evict_one_icplb(cpu);
 256         addr &= PAGE_MASK;
 257         icplb_tbl[cpu][idx].addr = addr;
 258         icplb_tbl[cpu][idx].data = i_data;
 259
 260         _disable_icplb();
 261         bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
 262         bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
 263         _enable_icplb();
 264
 265         return 0;
 266 }
 267
 268 static noinline int dcplb_protection_fault(unsigned int cpu)
 269 {
 270         int status = bfin_read_DCPLB_STATUS();
 271
 272         nr_dcplb_prot[cpu]++;
 273
 274         if (status & FAULT_RW) {
 275                 int idx = faulting_cplb_index(status);
 276                 unsigned long data = dcplb_tbl[cpu][idx].data;
 277                 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
 278                     write_permitted(status, data)) {
 279                         data |= CPLB_DIRTY;
 280                         dcplb_tbl[cpu][idx].data = data;
 281                         bfin_write32(DCPLB_DATA0 + idx * 4, data);
 282                         return 0;
 283                 }
 284         }
 285         return CPLB_PROT_VIOL;
 286 }
 287
 288 int cplb_hdr(int seqstat, struct pt_regs *regs)
 289 {
 290         int cause = seqstat & 0x3f;
 291         unsigned int cpu = raw_smp_processor_id();
 292         switch (cause) {
 293         case 0x23:
 294                 return dcplb_protection_fault(cpu);
 295         case 0x2C:
 296                 return icplb_miss(cpu);
 297         case 0x26:
 298                 return dcplb_miss(cpu);
 299         default:
 300                 return 1;
 301         }
 302 }
 303
 304 void flush_switched_cplbs(unsigned int cpu)
 305 {
 306         int i;
 307         unsigned long flags;
 308
 309         nr_cplb_flush[cpu]++;
 310
 311         local_irq_save_hw(flags);
 312         _disable_icplb();
 313         for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
 314                 icplb_tbl[cpu][i].data = 0;
 315                 bfin_write32(ICPLB_DATA0 + i * 4, 0);
 316         }
 317         _enable_icplb();
 318
 319         _disable_dcplb();
 320         for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
 321                 dcplb_tbl[cpu][i].data = 0;
 322                 bfin_write32(DCPLB_DATA0 + i * 4, 0);
 323         }
 324         _enable_dcplb();
 325         local_irq_restore_hw(flags);
 326
 327 }
 328
 329 void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
 330 {
 331         int i;
 332         unsigned long addr = (unsigned long)masks;
 333         unsigned long d_data;
 334         unsigned long flags;
 335
 336         if (!masks) {
 337                 current_rwx_mask[cpu] = masks;
 338                 return;
 339         }
 340
 341         local_irq_save_hw(flags);
 342         current_rwx_mask[cpu] = masks;
 343
 344         if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
 345                 addr = L2_START;
 346                 d_data = L2_DMEMORY;
 347         } else {
 348                 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 349 #ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
 350                 d_data |= CPLB_L1_CHBL;
 351 # ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
 352                 d_data |= CPLB_L1_AOW | CPLB_WT;
 353 # endif
 354 #endif
 355         }
 356
 357         _disable_dcplb();
 358         for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
 359                 dcplb_tbl[cpu][i].addr = addr;
 360                 dcplb_tbl[cpu][i].data = d_data;
 361                 bfin_write32(DCPLB_DATA0 + i * 4, d_data);
 362                 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
 363                 addr += PAGE_SIZE;
 364         }
 365         _enable_dcplb();
 366         local_irq_restore_hw(flags);
 367 }