2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <linux/module.h>
25 #include <asm/blackfin.h>
27 #include <asm/cplbinit.h>
30 # error the MPU will not function safely while Anomaly 05000263 applies
33 struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
34 struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
36 int first_switched_icplb, first_switched_dcplb;
39 void __init generate_cplb_tables_cpu(unsigned int cpu)
43 unsigned long d_data, i_data;
44 unsigned long d_cache = 0, i_cache = 0;
46 printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
48 #ifdef CONFIG_BFIN_ICACHE
49 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
52 #ifdef CONFIG_BFIN_DCACHE
53 d_cache = CPLB_L1_CHBL;
55 d_cache |= CPLB_L1_AOW | CPLB_WT;
61 /* Set up the zero page. */
62 dcplb_tbl[cpu][i_d].addr = 0;
63 dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
66 icplb_tbl[cpu][i_i].addr = 0;
67 icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
70 /* Cover kernel memory with 4M pages. */
72 d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
73 i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
75 for (; addr < memory_start; addr += 4 * 1024 * 1024) {
76 dcplb_tbl[cpu][i_d].addr = addr;
77 dcplb_tbl[cpu][i_d++].data = d_data;
78 icplb_tbl[cpu][i_i].addr = addr;
79 icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
82 /* Cover L1 memory. One 4M area for code and data each is enough. */
83 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
84 dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
85 dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
87 #if L1_CODE_LENGTH > 0
88 icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
89 icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
94 dcplb_tbl[cpu][i_d].addr = L2_START;
95 dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
96 icplb_tbl[cpu][i_i].addr = L2_START;
97 icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
100 first_mask_dcplb = i_d;
101 first_switched_dcplb = i_d + (1 << page_mask_order);
102 first_switched_icplb = i_i;
104 while (i_d < MAX_CPLBS)
105 dcplb_tbl[cpu][i_d++].data = 0;
106 while (i_i < MAX_CPLBS)
107 icplb_tbl[cpu][i_i++].data = 0;