2 * File: include/asm-blackfin/cplbinit.h
10 * Copyright 2004-2006 Analog Devices Inc.
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #ifndef __ASM_CPLBINIT_H__
31 #define __ASM_CPLBINIT_H__
33 #include <asm/blackfin.h>
38 #include <asm/cplb-mpu.h>
39 extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
40 extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
51 #define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
52 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
54 #define CPLB_MEM CONFIG_MAX_MEM_SIZE
57 * Number of required data CPLB switchtable entries
58 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
59 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
60 * 1 for L1 Data Memory
61 * possibly 1 for L2 Data Memory
62 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
65 #define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \
66 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
69 * Number of required instruction CPLB switchtable entries
70 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
71 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
72 * 1 for L1 Instruction Memory
73 * possibly 1 for L2 Instruction Memory
74 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
76 #define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)
78 /* Number of CPLB table entries, used for cplb-nompu. */
79 #define CPLB_TBL_ENTRIES (16 * 4)
82 ZERO_P, L1I_MEM, L1D_MEM, L2_MEM, SDRAM_KERN, SDRAM_RAM_MTD, SDRAM_DMAZ,
83 RES_MEM, ASYNC_MEM, OCB_ROM
87 u32 start; /* start address */
88 u32 end; /* end address */
89 u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
90 u16 attr;/* attributes */
91 u16 i_conf;/* I-CPLB DATA */
92 u16 d_conf;/* D-CPLB DATA */
94 const s8 name[30];/* name */
103 extern u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
104 extern u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
106 /* Till here we are discussing about the static memory management model.
107 * However, the operating envoronments commonly define more CPLB
108 * descriptors to cover the entire addressable memory than will fit into
109 * the available on-chip 16 CPLB MMRs. When this happens, the below table
110 * will be used which will hold all the potentially required CPLB descriptors
112 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
115 extern u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1];
116 extern u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1];
117 #ifdef CONFIG_CPLB_INFO
118 extern u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS];
119 extern u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS];
121 extern void bfin_icache_init(u_long icplbs[]);
122 extern void bfin_dcache_init(u_long dcplbs[]);
124 #endif /* CONFIG_MPU */
126 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
127 extern void generate_cplb_tables_cpu(unsigned int cpu);