2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
14 config RWSEM_GENERIC_SPINLOCK
17 config RWSEM_XCHGADD_ALGORITHM
22 select HAVE_FUNCTION_GRAPH_TRACER
23 select HAVE_FUNCTION_TRACER
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_BZIP2
27 select HAVE_KERNEL_LZMA
29 select ARCH_WANT_OPTIONAL_GPIOLIB
41 config GENERIC_FIND_NEXT_BIT
44 config GENERIC_HWEIGHT
47 config GENERIC_HARDIRQS
50 config GENERIC_IRQ_PROBE
53 config GENERIC_HARDIRQS_NO__DO_IRQ
59 config FORCE_MAX_ZONEORDER
63 config GENERIC_CALIBRATE_DELAY
66 config LOCKDEP_SUPPORT
69 config STACKTRACE_SUPPORT
72 config TRACE_IRQFLAGS_SUPPORT
77 source "kernel/Kconfig.preempt"
79 source "kernel/Kconfig.freezer"
81 menu "Blackfin Processor Options"
83 comment "Processor and Board Settings"
92 BF512 Processor Support.
97 BF514 Processor Support.
102 BF516 Processor Support.
107 BF518 Processor Support.
112 BF522 Processor Support.
117 BF523 Processor Support.
122 BF524 Processor Support.
127 BF525 Processor Support.
132 BF526 Processor Support.
137 BF527 Processor Support.
142 BF531 Processor Support.
147 BF532 Processor Support.
152 BF533 Processor Support.
157 BF534 Processor Support.
162 BF536 Processor Support.
167 BF537 Processor Support.
172 BF538 Processor Support.
177 BF539 Processor Support.
182 BF542 Processor Support.
187 BF542 Processor Support.
192 BF544 Processor Support.
197 BF544 Processor Support.
202 BF547 Processor Support.
207 BF547 Processor Support.
212 BF548 Processor Support.
217 BF548 Processor Support.
222 BF549 Processor Support.
227 BF549 Processor Support.
232 BF561 Processor Support.
238 select GENERIC_CLOCKEVENTS
239 bool "Symmetric multi-processing support"
241 This enables support for systems with more than one CPU,
242 like the dual core BF561. If you have a system with only one
243 CPU, say N. If you have a system with more than one CPU, say Y.
245 If you don't know what to do here, say N.
259 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
260 default 2 if (BF537 || BF536 || BF534)
261 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
262 default 4 if (BF538 || BF539)
266 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
267 default 3 if (BF537 || BF536 || BF534 || BF54xM)
268 default 5 if (BF561 || BF538 || BF539)
269 default 6 if (BF533 || BF532 || BF531)
273 default BF_REV_0_0 if (BF51x || BF52x)
274 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
275 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
279 depends on (BF51x || BF52x || (BF54x && !BF54xM))
283 depends on (BF51x || BF52x || (BF54x && !BF54xM))
287 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
291 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
295 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
299 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
303 depends on (BF533 || BF532 || BF531)
315 depends on (BF512 || BF514 || BF516 || BF518)
320 depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
325 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
330 depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
335 depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
338 config MEM_GENERIC_BOARD
340 depends on GENERIC_BOARD
343 config MEM_MT48LC64M4A2FB_7E
345 depends on (BFIN533_STAMP)
348 config MEM_MT48LC16M16A2TG_75
350 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
351 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
352 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
353 || BFIN527_BLUETECHNIX_CM)
356 config MEM_MT48LC32M8A2_75
358 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
361 config MEM_MT48LC8M32B2B5_7
363 depends on (BFIN561_BLUETECHNIX_CM)
366 config MEM_MT48LC32M16A2TG_75
368 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
371 config MEM_MT48LC32M8A2_75
373 depends on (BFIN518F_EZBRD)
376 config MEM_MT48H32M16LFCJ_75
378 depends on (BFIN526_EZBRD)
381 source "arch/blackfin/mach-bf518/Kconfig"
382 source "arch/blackfin/mach-bf527/Kconfig"
383 source "arch/blackfin/mach-bf533/Kconfig"
384 source "arch/blackfin/mach-bf561/Kconfig"
385 source "arch/blackfin/mach-bf537/Kconfig"
386 source "arch/blackfin/mach-bf538/Kconfig"
387 source "arch/blackfin/mach-bf548/Kconfig"
389 menu "Board customizations"
392 bool "Default bootloader kernel arguments"
395 string "Initial kernel command string"
396 depends on CMDLINE_BOOL
397 default "console=ttyBF0,57600"
399 If you don't have a boot loader capable of passing a command line string
400 to the kernel, you may specify one here. As a minimum, you should specify
401 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
404 hex "Kernel load address for booting"
406 range 0x1000 0x20000000
408 This option allows you to set the load address of the kernel.
409 This can be useful if you are on a board which has a small amount
410 of memory or you wish to reserve some memory at the beginning of
413 Note that you need to keep this value above 4k (0x1000) as this
414 memory region is used to capture NULL pointer references as well
415 as some core kernel functions.
418 hex "Kernel ROM Base"
421 range 0x20000000 0x20400000 if !(BF54x || BF561)
422 range 0x20000000 0x30000000 if (BF54x || BF561)
425 comment "Clock/PLL Setup"
428 int "Frequency of the crystal on the board in Hz"
429 default "10000000" if BFIN532_IP0X
430 default "11059200" if BFIN533_STAMP
431 default "24576000" if PNAV10
432 default "25000000" # most people use this
433 default "27000000" if BFIN533_EZKIT
434 default "30000000" if BFIN561_EZKIT
436 The frequency of CLKIN crystal oscillator on the board in Hz.
437 Warning: This value should match the crystal on the board. Otherwise,
438 peripherals won't work properly.
440 config BFIN_KERNEL_CLOCK
441 bool "Re-program Clocks while Kernel boots?"
444 This option decides if kernel clocks are re-programed from the
445 bootloader settings. If the clocks are not set, the SDRAM settings
446 are also not changed, and the Bootloader does 100% of the hardware
451 depends on BFIN_KERNEL_CLOCK
456 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
459 If this is set the clock will be divided by 2, before it goes to the PLL.
463 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
465 default "22" if BFIN533_EZKIT
466 default "45" if BFIN533_STAMP
467 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
468 default "22" if BFIN533_BLUETECHNIX_CM
469 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
470 default "20" if BFIN561_EZKIT
471 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
473 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
474 PLL Frequency = (Crystal Frequency) * (this setting)
477 prompt "Core Clock Divider"
478 depends on BFIN_KERNEL_CLOCK
481 This sets the frequency of the core. It can be 1, 2, 4 or 8
482 Core Frequency = (PLL frequency) / (this setting)
498 int "System Clock Divider"
499 depends on BFIN_KERNEL_CLOCK
503 This sets the frequency of the system clock (including SDRAM or DDR).
504 This can be between 1 and 15
505 System Clock = (PLL frequency) / (this setting)
508 prompt "DDR SDRAM Chip Type"
509 depends on BFIN_KERNEL_CLOCK
511 default MEM_MT46V32M16_5B
513 config MEM_MT46V32M16_6T
516 config MEM_MT46V32M16_5B
521 prompt "DDR/SDRAM Timing"
522 depends on BFIN_KERNEL_CLOCK
523 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
525 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
526 The calculated SDRAM timing parameters may not be 100%
527 accurate - This option is therefore marked experimental.
529 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
530 bool "Calculate Timings (EXPERIMENTAL)"
531 depends on EXPERIMENTAL
533 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
534 bool "Provide accurate Timings based on target SCLK"
536 Please consult the Blackfin Hardware Reference Manuals as well
537 as the memory device datasheet.
538 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
541 menu "Memory Init Control"
542 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
559 config MEM_EBIU_DDRQUE
576 # Max & Min Speeds for various Chips
580 default 400000000 if BF512
581 default 400000000 if BF514
582 default 400000000 if BF516
583 default 400000000 if BF518
584 default 400000000 if BF522
585 default 600000000 if BF523
586 default 400000000 if BF524
587 default 600000000 if BF525
588 default 400000000 if BF526
589 default 600000000 if BF527
590 default 400000000 if BF531
591 default 400000000 if BF532
592 default 750000000 if BF533
593 default 500000000 if BF534
594 default 400000000 if BF536
595 default 600000000 if BF537
596 default 533333333 if BF538
597 default 533333333 if BF539
598 default 600000000 if BF542
599 default 533333333 if BF544
600 default 600000000 if BF547
601 default 600000000 if BF548
602 default 533333333 if BF549
603 default 600000000 if BF561
617 comment "Kernel Timer/Scheduler"
619 source kernel/Kconfig.hz
624 config GENERIC_CLOCKEVENTS
625 bool "Generic clock events"
629 prompt "Kernel Tick Source"
630 depends on GENERIC_CLOCKEVENTS
631 default TICKSOURCE_CORETMR
633 config TICKSOURCE_GPTMR0
634 bool "Gptimer0 (SCLK domain)"
637 config TICKSOURCE_CORETMR
638 bool "Core timer (CCLK domain)"
642 config CYCLES_CLOCKSOURCE
643 bool "Use 'CYCLES' as a clocksource"
644 depends on GENERIC_CLOCKEVENTS
645 depends on !BFIN_SCRATCH_REG_CYCLES
648 If you say Y here, you will enable support for using the 'cycles'
649 registers as a clock source. Doing so means you will be unable to
650 safely write to the 'cycles' register during runtime. You will
651 still be able to read it (such as for performance monitoring), but
652 writing the registers will most likely crash the kernel.
654 config GPTMR0_CLOCKSOURCE
655 bool "Use GPTimer0 as a clocksource"
657 depends on GENERIC_CLOCKEVENTS
658 depends on !TICKSOURCE_GPTMR0
660 config ARCH_USES_GETTIMEOFFSET
661 depends on !GENERIC_CLOCKEVENTS
664 source kernel/time/Kconfig
669 prompt "Blackfin Exception Scratch Register"
670 default BFIN_SCRATCH_REG_RETN
672 Select the resource to reserve for the Exception handler:
673 - RETN: Non-Maskable Interrupt (NMI)
674 - RETE: Exception Return (JTAG/ICE)
675 - CYCLES: Performance counter
677 If you are unsure, please select "RETN".
679 config BFIN_SCRATCH_REG_RETN
682 Use the RETN register in the Blackfin exception handler
683 as a stack scratch register. This means you cannot
684 safely use NMI on the Blackfin while running Linux, but
685 you can debug the system with a JTAG ICE and use the
686 CYCLES performance registers.
688 If you are unsure, please select "RETN".
690 config BFIN_SCRATCH_REG_RETE
693 Use the RETE register in the Blackfin exception handler
694 as a stack scratch register. This means you cannot
695 safely use a JTAG ICE while debugging a Blackfin board,
696 but you can safely use the CYCLES performance registers
699 If you are unsure, please select "RETN".
701 config BFIN_SCRATCH_REG_CYCLES
704 Use the CYCLES register in the Blackfin exception handler
705 as a stack scratch register. This means you cannot
706 safely use the CYCLES performance registers on a Blackfin
707 board at anytime, but you can debug the system with a JTAG
710 If you are unsure, please select "RETN".
717 menu "Blackfin Kernel Optimizations"
720 comment "Memory Optimizations"
723 bool "Locate interrupt entry code in L1 Memory"
726 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
727 into L1 instruction memory. (less latency)
729 config EXCPT_IRQ_SYSC_L1
730 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
733 If enabled, the entire ASM lowlevel exception and interrupt entry code
734 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
738 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
741 If enabled, the frequently called do_irq dispatcher function is linked
742 into L1 instruction memory. (less latency)
744 config CORE_TIMER_IRQ_L1
745 bool "Locate frequently called timer_interrupt() function in L1 Memory"
748 If enabled, the frequently called timer_interrupt() function is linked
749 into L1 instruction memory. (less latency)
752 bool "Locate frequently idle function in L1 Memory"
755 If enabled, the frequently called idle function is linked
756 into L1 instruction memory. (less latency)
759 bool "Locate kernel schedule function in L1 Memory"
762 If enabled, the frequently called kernel schedule is linked
763 into L1 instruction memory. (less latency)
765 config ARITHMETIC_OPS_L1
766 bool "Locate kernel owned arithmetic functions in L1 Memory"
769 If enabled, arithmetic functions are linked
770 into L1 instruction memory. (less latency)
773 bool "Locate access_ok function in L1 Memory"
776 If enabled, the access_ok function is linked
777 into L1 instruction memory. (less latency)
780 bool "Locate memset function in L1 Memory"
783 If enabled, the memset function is linked
784 into L1 instruction memory. (less latency)
787 bool "Locate memcpy function in L1 Memory"
790 If enabled, the memcpy function is linked
791 into L1 instruction memory. (less latency)
793 config SYS_BFIN_SPINLOCK_L1
794 bool "Locate sys_bfin_spinlock function in L1 Memory"
797 If enabled, sys_bfin_spinlock function is linked
798 into L1 instruction memory. (less latency)
800 config IP_CHECKSUM_L1
801 bool "Locate IP Checksum function in L1 Memory"
804 If enabled, the IP Checksum function is linked
805 into L1 instruction memory. (less latency)
807 config CACHELINE_ALIGNED_L1
808 bool "Locate cacheline_aligned data to L1 Data Memory"
813 If enabled, cacheline_aligned data is linked
814 into L1 data memory. (less latency)
816 config SYSCALL_TAB_L1
817 bool "Locate Syscall Table L1 Data Memory"
821 If enabled, the Syscall LUT is linked
822 into L1 data memory. (less latency)
824 config CPLB_SWITCH_TAB_L1
825 bool "Locate CPLB Switch Tables L1 Data Memory"
829 If enabled, the CPLB Switch Tables are linked
830 into L1 data memory. (less latency)
833 bool "Support locating application stack in L1 Scratch Memory"
836 If enabled the application stack can be located in L1
837 scratch memory (less latency).
839 Currently only works with FLAT binaries.
841 config EXCEPTION_L1_SCRATCH
842 bool "Locate exception stack in L1 Scratch Memory"
844 depends on !APP_STACK_L1
846 Whenever an exception occurs, use the L1 Scratch memory for
847 stack storage. You cannot place the stacks of FLAT binaries
848 in L1 when using this option.
850 If you don't use L1 Scratch, then you should say Y here.
852 comment "Speed Optimizations"
853 config BFIN_INS_LOWOVERHEAD
854 bool "ins[bwl] low overhead, higher interrupt latency"
857 Reads on the Blackfin are speculative. In Blackfin terms, this means
858 they can be interrupted at any time (even after they have been issued
859 on to the external bus), and re-issued after the interrupt occurs.
860 For memory - this is not a big deal, since memory does not change if
863 If a FIFO is sitting on the end of the read, it will see two reads,
864 when the core only sees one since the FIFO receives both the read
865 which is cancelled (and not delivered to the core) and the one which
866 is re-issued (which is delivered to the core).
868 To solve this, interrupts are turned off before reads occur to
869 I/O space. This option controls which the overhead/latency of
870 controlling interrupts during this time
871 "n" turns interrupts off every read
872 (higher overhead, but lower interrupt latency)
873 "y" turns interrupts off every loop
874 (low overhead, but longer interrupt latency)
876 default behavior is to leave this set to on (type "Y"). If you are experiencing
877 interrupt latency issues, it is safe and OK to turn this off.
882 prompt "Kernel executes from"
884 Choose the memory type that the kernel will be running in.
889 The kernel will be resident in RAM when running.
894 The kernel will be resident in FLASH/ROM when running.
901 tristate "Enable Blackfin General Purpose Timers API"
904 Enable support for the General Purpose Timers API. If you
907 To compile this driver as a module, choose M here: the module
908 will be called gptimers.
911 prompt "Uncached DMA region"
912 default DMA_UNCACHED_1M
913 config DMA_UNCACHED_4M
914 bool "Enable 4M DMA region"
915 config DMA_UNCACHED_2M
916 bool "Enable 2M DMA region"
917 config DMA_UNCACHED_1M
918 bool "Enable 1M DMA region"
919 config DMA_UNCACHED_NONE
920 bool "Disable DMA region"
924 comment "Cache Support"
929 config BFIN_EXTMEM_ICACHEABLE
930 bool "Enable ICACHE for external memory"
931 depends on BFIN_ICACHE
933 config BFIN_L2_ICACHEABLE
934 bool "Enable ICACHE for L2 SRAM"
935 depends on BFIN_ICACHE
936 depends on BF54x || BF561
942 config BFIN_DCACHE_BANKA
943 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
944 depends on BFIN_DCACHE && !BF531
946 config BFIN_EXTMEM_DCACHEABLE
947 bool "Enable DCACHE for external memory"
948 depends on BFIN_DCACHE
951 prompt "External memory DCACHE policy"
952 depends on BFIN_EXTMEM_DCACHEABLE
953 default BFIN_EXTMEM_WRITEBACK if !SMP
954 default BFIN_EXTMEM_WRITETHROUGH if SMP
955 config BFIN_EXTMEM_WRITEBACK
960 Cached data will be written back to SDRAM only when needed.
961 This can give a nice increase in performance, but beware of
962 broken drivers that do not properly invalidate/flush their
965 Write Through Policy:
966 Cached data will always be written back to SDRAM when the
967 cache is updated. This is a completely safe setting, but
968 performance is worse than Write Back.
970 If you are unsure of the options and you want to be safe,
971 then go with Write Through.
973 config BFIN_EXTMEM_WRITETHROUGH
977 Cached data will be written back to SDRAM only when needed.
978 This can give a nice increase in performance, but beware of
979 broken drivers that do not properly invalidate/flush their
982 Write Through Policy:
983 Cached data will always be written back to SDRAM when the
984 cache is updated. This is a completely safe setting, but
985 performance is worse than Write Back.
987 If you are unsure of the options and you want to be safe,
988 then go with Write Through.
992 config BFIN_L2_DCACHEABLE
993 bool "Enable DCACHE for L2 SRAM"
994 depends on BFIN_DCACHE
995 depends on (BF54x || BF561) && !SMP
998 prompt "L2 SRAM DCACHE policy"
999 depends on BFIN_L2_DCACHEABLE
1000 default BFIN_L2_WRITEBACK
1001 config BFIN_L2_WRITEBACK
1004 config BFIN_L2_WRITETHROUGH
1005 bool "Write through"
1009 comment "Memory Protection Unit"
1011 bool "Enable the memory protection unit (EXPERIMENTAL)"
1014 Use the processor's MPU to protect applications from accessing
1015 memory they do not own. This comes at a performance penalty
1016 and is recommended only for debugging.
1018 comment "Asynchronous Memory Configuration"
1020 menu "EBIU_AMGCTL Global Control"
1022 bool "Enable CLKOUT"
1026 bool "DMA has priority over core for ext. accesses"
1031 bool "Bank 0 16 bit packing enable"
1036 bool "Bank 1 16 bit packing enable"
1041 bool "Bank 2 16 bit packing enable"
1046 bool "Bank 3 16 bit packing enable"
1050 prompt "Enable Asynchronous Memory Banks"
1054 bool "Disable All Banks"
1057 bool "Enable Bank 0"
1059 config C_AMBEN_B0_B1
1060 bool "Enable Bank 0 & 1"
1062 config C_AMBEN_B0_B1_B2
1063 bool "Enable Bank 0 & 1 & 2"
1066 bool "Enable All Banks"
1070 menu "EBIU_AMBCTL Control"
1072 hex "Bank 0 (AMBCTL0.L)"
1075 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1076 used to control the Asynchronous Memory Bank 0 settings.
1079 hex "Bank 1 (AMBCTL0.H)"
1081 default 0x5558 if BF54x
1083 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1084 used to control the Asynchronous Memory Bank 1 settings.
1087 hex "Bank 2 (AMBCTL1.L)"
1090 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1091 used to control the Asynchronous Memory Bank 2 settings.
1094 hex "Bank 3 (AMBCTL1.H)"
1097 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1098 used to control the Asynchronous Memory Bank 3 settings.
1102 config EBIU_MBSCTLVAL
1103 hex "EBIU Bank Select Control Register"
1108 hex "Flash Memory Mode Control Register"
1113 hex "Flash Memory Bank Control Register"
1118 #############################################################################
1119 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1125 Support for PCI bus.
1127 source "drivers/pci/Kconfig"
1130 bool "Support for hot-pluggable device"
1132 Say Y here if you want to plug devices into your computer while
1133 the system is running, and be able to use them quickly. In many
1134 cases, the devices can likewise be unplugged at any time too.
1136 One well known example of this is PCMCIA- or PC-cards, credit-card
1137 size devices such as network cards, modems or hard drives which are
1138 plugged into slots found on all modern laptop computers. Another
1139 example, used on modern desktops as well as laptops, is USB.
1141 Enable HOTPLUG and build a modular kernel. Get agent software
1142 (from <http://linux-hotplug.sourceforge.net/>) and install it.
1143 Then your kernel will automatically call out to a user mode "policy
1144 agent" (/sbin/hotplug) to load modules and set up software needed
1145 to use devices as you hotplug them.
1147 source "drivers/pcmcia/Kconfig"
1149 source "drivers/pci/hotplug/Kconfig"
1153 menu "Executable file formats"
1155 source "fs/Kconfig.binfmt"
1159 menu "Power management options"
1162 source "kernel/power/Kconfig"
1164 config ARCH_SUSPEND_POSSIBLE
1168 prompt "Standby Power Saving Mode"
1170 default PM_BFIN_SLEEP_DEEPER
1171 config PM_BFIN_SLEEP_DEEPER
1174 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1175 power dissipation by disabling the clock to the processor core (CCLK).
1176 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1177 to 0.85 V to provide the greatest power savings, while preserving the
1179 The PLL and system clock (SCLK) continue to operate at a very low
1180 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1181 the SDRAM is put into Self Refresh Mode. Typically an external event
1182 such as GPIO interrupt or RTC activity wakes up the processor.
1183 Various Peripherals such as UART, SPORT, PPI may not function as
1184 normal during Sleep Deeper, due to the reduced SCLK frequency.
1185 When in the sleep mode, system DMA access to L1 memory is not supported.
1187 If unsure, select "Sleep Deeper".
1189 config PM_BFIN_SLEEP
1192 Sleep Mode (High Power Savings) - The sleep mode reduces power
1193 dissipation by disabling the clock to the processor core (CCLK).
1194 The PLL and system clock (SCLK), however, continue to operate in
1195 this mode. Typically an external event or RTC activity will wake
1196 up the processor. When in the sleep mode, system DMA access to L1
1197 memory is not supported.
1199 If unsure, select "Sleep Deeper".
1202 config PM_WAKEUP_BY_GPIO
1203 bool "Allow Wakeup from Standby by GPIO"
1204 depends on PM && !BF54x
1206 config PM_WAKEUP_GPIO_NUMBER
1209 depends on PM_WAKEUP_BY_GPIO
1213 prompt "GPIO Polarity"
1214 depends on PM_WAKEUP_BY_GPIO
1215 default PM_WAKEUP_GPIO_POLAR_H
1216 config PM_WAKEUP_GPIO_POLAR_H
1218 config PM_WAKEUP_GPIO_POLAR_L
1220 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1222 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1224 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1228 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1231 config PM_BFIN_WAKE_PH6
1232 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1233 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1236 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1238 config PM_BFIN_WAKE_GP
1239 bool "Allow Wake-Up from GPIOs"
1240 depends on PM && BF54x
1243 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1244 (all processors, except ADSP-BF549). This option sets
1245 the general-purpose wake-up enable (GPWE) control bit to enable
1246 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1247 On ADSP-BF549 this option enables the the same functionality on the
1248 /MRXON pin also PH7.
1252 menu "CPU Frequency scaling"
1255 source "drivers/cpufreq/Kconfig"
1257 config BFIN_CPU_FREQ
1260 select CPU_FREQ_TABLE
1264 bool "CPU Voltage scaling"
1265 depends on EXPERIMENTAL
1269 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1270 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1271 manuals. There is a theoretical risk that during VDDINT transitions
1276 source "net/Kconfig"
1278 source "drivers/Kconfig"
1280 source "drivers/firmware/Kconfig"
1284 source "arch/blackfin/Kconfig.debug"
1286 source "security/Kconfig"
1288 source "crypto/Kconfig"
1290 source "lib/Kconfig"
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob