2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Blackfin Kernel Configuration"
18 config RWSEM_GENERIC_SPINLOCK
21 config RWSEM_XCHGADD_ALGORITHM
26 select HAVE_FUNCTION_GRAPH_TRACER
27 select HAVE_FUNCTION_TRACER
28 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
30 select HAVE_KERNEL_GZIP if RAMKERNEL
31 select HAVE_KERNEL_BZIP2 if RAMKERNEL
32 select HAVE_KERNEL_LZMA if RAMKERNEL
34 select ARCH_WANT_OPTIONAL_GPIOLIB
46 config GENERIC_FIND_NEXT_BIT
49 config GENERIC_HARDIRQS
52 config GENERIC_IRQ_PROBE
55 config GENERIC_HARDIRQS_NO__DO_IRQ
61 config FORCE_MAX_ZONEORDER
65 config GENERIC_CALIBRATE_DELAY
68 config LOCKDEP_SUPPORT
71 config STACKTRACE_SUPPORT
74 config TRACE_IRQFLAGS_SUPPORT
79 source "kernel/Kconfig.preempt"
81 source "kernel/Kconfig.freezer"
83 menu "Blackfin Processor Options"
85 comment "Processor and Board Settings"
94 BF512 Processor Support.
99 BF514 Processor Support.
104 BF516 Processor Support.
109 BF518 Processor Support.
114 BF522 Processor Support.
119 BF523 Processor Support.
124 BF524 Processor Support.
129 BF525 Processor Support.
134 BF526 Processor Support.
139 BF527 Processor Support.
144 BF531 Processor Support.
149 BF532 Processor Support.
154 BF533 Processor Support.
159 BF534 Processor Support.
164 BF536 Processor Support.
169 BF537 Processor Support.
174 BF538 Processor Support.
179 BF539 Processor Support.
184 BF542 Processor Support.
189 BF542 Processor Support.
194 BF544 Processor Support.
199 BF544 Processor Support.
204 BF547 Processor Support.
209 BF547 Processor Support.
214 BF548 Processor Support.
219 BF548 Processor Support.
224 BF549 Processor Support.
229 BF549 Processor Support.
234 BF561 Processor Support.
240 select TICKSOURCE_CORETMR
241 bool "Symmetric multi-processing support"
243 This enables support for systems with more than one CPU,
244 like the dual core BF561. If you have a system with only one
245 CPU, say N. If you have a system with more than one CPU, say Y.
247 If you don't know what to do here, say N.
255 bool "Support for hot-pluggable CPUs"
256 depends on SMP && HOTPLUG
264 config HAVE_LEGACY_PER_CPU_AREA
270 default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
271 default 2 if (BF537 || BF536 || BF534)
272 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
273 default 4 if (BF538 || BF539)
277 default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
278 default 3 if (BF537 || BF536 || BF534 || BF54xM)
279 default 5 if (BF561 || BF538 || BF539)
280 default 6 if (BF533 || BF532 || BF531)
284 default BF_REV_0_0 if (BF51x || BF52x)
285 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
286 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
290 depends on (BF51x || BF52x || (BF54x && !BF54xM))
294 depends on (BF51x || BF52x || (BF54x && !BF54xM))
298 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
302 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
306 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
310 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
314 depends on (BF533 || BF532 || BF531)
326 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
329 config MEM_GENERIC_BOARD
331 depends on GENERIC_BOARD
334 config MEM_MT48LC64M4A2FB_7E
336 depends on (BFIN533_STAMP)
339 config MEM_MT48LC16M16A2TG_75
341 depends on (BFIN533_EZKIT || BFIN561_EZKIT \
342 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
343 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
344 || BFIN527_BLUETECHNIX_CM)
347 config MEM_MT48LC32M8A2_75
349 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
352 config MEM_MT48LC8M32B2B5_7
354 depends on (BFIN561_BLUETECHNIX_CM)
357 config MEM_MT48LC32M16A2TG_75
359 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
362 config MEM_MT48LC32M8A2_75
364 depends on (BFIN518F_EZBRD)
367 config MEM_MT48H32M16LFCJ_75
369 depends on (BFIN526_EZBRD)
372 source "arch/blackfin/mach-bf518/Kconfig"
373 source "arch/blackfin/mach-bf527/Kconfig"
374 source "arch/blackfin/mach-bf533/Kconfig"
375 source "arch/blackfin/mach-bf561/Kconfig"
376 source "arch/blackfin/mach-bf537/Kconfig"
377 source "arch/blackfin/mach-bf538/Kconfig"
378 source "arch/blackfin/mach-bf548/Kconfig"
380 menu "Board customizations"
383 bool "Default bootloader kernel arguments"
386 string "Initial kernel command string"
387 depends on CMDLINE_BOOL
388 default "console=ttyBF0,57600"
390 If you don't have a boot loader capable of passing a command line string
391 to the kernel, you may specify one here. As a minimum, you should specify
392 the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
395 hex "Kernel load address for booting"
397 range 0x1000 0x20000000
399 This option allows you to set the load address of the kernel.
400 This can be useful if you are on a board which has a small amount
401 of memory or you wish to reserve some memory at the beginning of
404 Note that you need to keep this value above 4k (0x1000) as this
405 memory region is used to capture NULL pointer references as well
406 as some core kernel functions.
409 hex "Kernel ROM Base"
412 range 0x20000000 0x20400000 if !(BF54x || BF561)
413 range 0x20000000 0x30000000 if (BF54x || BF561)
415 Make sure your ROM base does not include any file-header
416 information that is prepended to the kernel.
418 For example, the bootable U-Boot format (created with
419 mkimage) has a 64 byte header (0x40). So while the image
420 you write to flash might start at say 0x20080000, you have
421 to add 0x40 to get the kernel's ROM base as it will come
424 comment "Clock/PLL Setup"
427 int "Frequency of the crystal on the board in Hz"
428 default "10000000" if BFIN532_IP0X
429 default "11059200" if BFIN533_STAMP
430 default "24576000" if PNAV10
431 default "25000000" # most people use this
432 default "27000000" if BFIN533_EZKIT
433 default "30000000" if BFIN561_EZKIT
435 The frequency of CLKIN crystal oscillator on the board in Hz.
436 Warning: This value should match the crystal on the board. Otherwise,
437 peripherals won't work properly.
439 config BFIN_KERNEL_CLOCK
440 bool "Re-program Clocks while Kernel boots?"
443 This option decides if kernel clocks are re-programed from the
444 bootloader settings. If the clocks are not set, the SDRAM settings
445 are also not changed, and the Bootloader does 100% of the hardware
450 depends on BFIN_KERNEL_CLOCK
455 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
458 If this is set the clock will be divided by 2, before it goes to the PLL.
462 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
464 default "22" if BFIN533_EZKIT
465 default "45" if BFIN533_STAMP
466 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
467 default "22" if BFIN533_BLUETECHNIX_CM
468 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
469 default "20" if BFIN561_EZKIT
470 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
472 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
473 PLL Frequency = (Crystal Frequency) * (this setting)
476 prompt "Core Clock Divider"
477 depends on BFIN_KERNEL_CLOCK
480 This sets the frequency of the core. It can be 1, 2, 4 or 8
481 Core Frequency = (PLL frequency) / (this setting)
497 int "System Clock Divider"
498 depends on BFIN_KERNEL_CLOCK
502 This sets the frequency of the system clock (including SDRAM or DDR).
503 This can be between 1 and 15
504 System Clock = (PLL frequency) / (this setting)
507 prompt "DDR SDRAM Chip Type"
508 depends on BFIN_KERNEL_CLOCK
510 default MEM_MT46V32M16_5B
512 config MEM_MT46V32M16_6T
515 config MEM_MT46V32M16_5B
520 prompt "DDR/SDRAM Timing"
521 depends on BFIN_KERNEL_CLOCK
522 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
524 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
525 The calculated SDRAM timing parameters may not be 100%
526 accurate - This option is therefore marked experimental.
528 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
529 bool "Calculate Timings (EXPERIMENTAL)"
530 depends on EXPERIMENTAL
532 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
533 bool "Provide accurate Timings based on target SCLK"
535 Please consult the Blackfin Hardware Reference Manuals as well
536 as the memory device datasheet.
537 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
540 menu "Memory Init Control"
541 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
558 config MEM_EBIU_DDRQUE
575 # Max & Min Speeds for various Chips
579 default 400000000 if BF512
580 default 400000000 if BF514
581 default 400000000 if BF516
582 default 400000000 if BF518
583 default 400000000 if BF522
584 default 600000000 if BF523
585 default 400000000 if BF524
586 default 600000000 if BF525
587 default 400000000 if BF526
588 default 600000000 if BF527
589 default 400000000 if BF531
590 default 400000000 if BF532
591 default 750000000 if BF533
592 default 500000000 if BF534
593 default 400000000 if BF536
594 default 600000000 if BF537
595 default 533333333 if BF538
596 default 533333333 if BF539
597 default 600000000 if BF542
598 default 533333333 if BF544
599 default 600000000 if BF547
600 default 600000000 if BF548
601 default 533333333 if BF549
602 default 600000000 if BF561
616 comment "Kernel Timer/Scheduler"
618 source kernel/Kconfig.hz
623 config GENERIC_CLOCKEVENTS
624 bool "Generic clock events"
627 menu "Clock event device"
628 depends on GENERIC_CLOCKEVENTS
629 config TICKSOURCE_GPTMR0
634 config TICKSOURCE_CORETMR
640 depends on GENERIC_CLOCKEVENTS
641 config CYCLES_CLOCKSOURCE
644 depends on !BFIN_SCRATCH_REG_CYCLES
647 If you say Y here, you will enable support for using the 'cycles'
648 registers as a clock source. Doing so means you will be unable to
649 safely write to the 'cycles' register during runtime. You will
650 still be able to read it (such as for performance monitoring), but
651 writing the registers will most likely crash the kernel.
653 config GPTMR0_CLOCKSOURCE
656 depends on !TICKSOURCE_GPTMR0
659 config ARCH_USES_GETTIMEOFFSET
660 depends on !GENERIC_CLOCKEVENTS
663 source kernel/time/Kconfig
668 prompt "Blackfin Exception Scratch Register"
669 default BFIN_SCRATCH_REG_RETN
671 Select the resource to reserve for the Exception handler:
672 - RETN: Non-Maskable Interrupt (NMI)
673 - RETE: Exception Return (JTAG/ICE)
674 - CYCLES: Performance counter
676 If you are unsure, please select "RETN".
678 config BFIN_SCRATCH_REG_RETN
681 Use the RETN register in the Blackfin exception handler
682 as a stack scratch register. This means you cannot
683 safely use NMI on the Blackfin while running Linux, but
684 you can debug the system with a JTAG ICE and use the
685 CYCLES performance registers.
687 If you are unsure, please select "RETN".
689 config BFIN_SCRATCH_REG_RETE
692 Use the RETE register in the Blackfin exception handler
693 as a stack scratch register. This means you cannot
694 safely use a JTAG ICE while debugging a Blackfin board,
695 but you can safely use the CYCLES performance registers
698 If you are unsure, please select "RETN".
700 config BFIN_SCRATCH_REG_CYCLES
703 Use the CYCLES register in the Blackfin exception handler
704 as a stack scratch register. This means you cannot
705 safely use the CYCLES performance registers on a Blackfin
706 board at anytime, but you can debug the system with a JTAG
709 If you are unsure, please select "RETN".
716 menu "Blackfin Kernel Optimizations"
719 comment "Memory Optimizations"
722 bool "Locate interrupt entry code in L1 Memory"
725 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
726 into L1 instruction memory. (less latency)
728 config EXCPT_IRQ_SYSC_L1
729 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
732 If enabled, the entire ASM lowlevel exception and interrupt entry code
733 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
737 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
740 If enabled, the frequently called do_irq dispatcher function is linked
741 into L1 instruction memory. (less latency)
743 config CORE_TIMER_IRQ_L1
744 bool "Locate frequently called timer_interrupt() function in L1 Memory"
747 If enabled, the frequently called timer_interrupt() function is linked
748 into L1 instruction memory. (less latency)
751 bool "Locate frequently idle function in L1 Memory"
754 If enabled, the frequently called idle function is linked
755 into L1 instruction memory. (less latency)
758 bool "Locate kernel schedule function in L1 Memory"
761 If enabled, the frequently called kernel schedule is linked
762 into L1 instruction memory. (less latency)
764 config ARITHMETIC_OPS_L1
765 bool "Locate kernel owned arithmetic functions in L1 Memory"
768 If enabled, arithmetic functions are linked
769 into L1 instruction memory. (less latency)
772 bool "Locate access_ok function in L1 Memory"
775 If enabled, the access_ok function is linked
776 into L1 instruction memory. (less latency)
779 bool "Locate memset function in L1 Memory"
782 If enabled, the memset function is linked
783 into L1 instruction memory. (less latency)
786 bool "Locate memcpy function in L1 Memory"
789 If enabled, the memcpy function is linked
790 into L1 instruction memory. (less latency)
792 config SYS_BFIN_SPINLOCK_L1
793 bool "Locate sys_bfin_spinlock function in L1 Memory"
796 If enabled, sys_bfin_spinlock function is linked
797 into L1 instruction memory. (less latency)
799 config IP_CHECKSUM_L1
800 bool "Locate IP Checksum function in L1 Memory"
803 If enabled, the IP Checksum function is linked
804 into L1 instruction memory. (less latency)
806 config CACHELINE_ALIGNED_L1
807 bool "Locate cacheline_aligned data to L1 Data Memory"
812 If enabled, cacheline_aligned data is linked
813 into L1 data memory. (less latency)
815 config SYSCALL_TAB_L1
816 bool "Locate Syscall Table L1 Data Memory"
820 If enabled, the Syscall LUT is linked
821 into L1 data memory. (less latency)
823 config CPLB_SWITCH_TAB_L1
824 bool "Locate CPLB Switch Tables L1 Data Memory"
828 If enabled, the CPLB Switch Tables are linked
829 into L1 data memory. (less latency)
832 bool "Support locating application stack in L1 Scratch Memory"
835 If enabled the application stack can be located in L1
836 scratch memory (less latency).
838 Currently only works with FLAT binaries.
840 config EXCEPTION_L1_SCRATCH
841 bool "Locate exception stack in L1 Scratch Memory"
843 depends on !APP_STACK_L1
845 Whenever an exception occurs, use the L1 Scratch memory for
846 stack storage. You cannot place the stacks of FLAT binaries
847 in L1 when using this option.
849 If you don't use L1 Scratch, then you should say Y here.
851 comment "Speed Optimizations"
852 config BFIN_INS_LOWOVERHEAD
853 bool "ins[bwl] low overhead, higher interrupt latency"
856 Reads on the Blackfin are speculative. In Blackfin terms, this means
857 they can be interrupted at any time (even after they have been issued
858 on to the external bus), and re-issued after the interrupt occurs.
859 For memory - this is not a big deal, since memory does not change if
862 If a FIFO is sitting on the end of the read, it will see two reads,
863 when the core only sees one since the FIFO receives both the read
864 which is cancelled (and not delivered to the core) and the one which
865 is re-issued (which is delivered to the core).
867 To solve this, interrupts are turned off before reads occur to
868 I/O space. This option controls which the overhead/latency of
869 controlling interrupts during this time
870 "n" turns interrupts off every read
871 (higher overhead, but lower interrupt latency)
872 "y" turns interrupts off every loop
873 (low overhead, but longer interrupt latency)
875 default behavior is to leave this set to on (type "Y"). If you are experiencing
876 interrupt latency issues, it is safe and OK to turn this off.
881 prompt "Kernel executes from"
883 Choose the memory type that the kernel will be running in.
888 The kernel will be resident in RAM when running.
893 The kernel will be resident in FLASH/ROM when running.
900 tristate "Enable Blackfin General Purpose Timers API"
903 Enable support for the General Purpose Timers API. If you
906 To compile this driver as a module, choose M here: the module
907 will be called gptimers.
910 prompt "Uncached DMA region"
911 default DMA_UNCACHED_1M
912 config DMA_UNCACHED_4M
913 bool "Enable 4M DMA region"
914 config DMA_UNCACHED_2M
915 bool "Enable 2M DMA region"
916 config DMA_UNCACHED_1M
917 bool "Enable 1M DMA region"
918 config DMA_UNCACHED_512K
919 bool "Enable 512K DMA region"
920 config DMA_UNCACHED_256K
921 bool "Enable 256K DMA region"
922 config DMA_UNCACHED_128K
923 bool "Enable 128K DMA region"
924 config DMA_UNCACHED_NONE
925 bool "Disable DMA region"
929 comment "Cache Support"
934 config BFIN_EXTMEM_ICACHEABLE
935 bool "Enable ICACHE for external memory"
936 depends on BFIN_ICACHE
938 config BFIN_L2_ICACHEABLE
939 bool "Enable ICACHE for L2 SRAM"
940 depends on BFIN_ICACHE
941 depends on BF54x || BF561
947 config BFIN_DCACHE_BANKA
948 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
949 depends on BFIN_DCACHE && !BF531
951 config BFIN_EXTMEM_DCACHEABLE
952 bool "Enable DCACHE for external memory"
953 depends on BFIN_DCACHE
956 prompt "External memory DCACHE policy"
957 depends on BFIN_EXTMEM_DCACHEABLE
958 default BFIN_EXTMEM_WRITEBACK if !SMP
959 default BFIN_EXTMEM_WRITETHROUGH if SMP
960 config BFIN_EXTMEM_WRITEBACK
965 Cached data will be written back to SDRAM only when needed.
966 This can give a nice increase in performance, but beware of
967 broken drivers that do not properly invalidate/flush their
970 Write Through Policy:
971 Cached data will always be written back to SDRAM when the
972 cache is updated. This is a completely safe setting, but
973 performance is worse than Write Back.
975 If you are unsure of the options and you want to be safe,
976 then go with Write Through.
978 config BFIN_EXTMEM_WRITETHROUGH
982 Cached data will be written back to SDRAM only when needed.
983 This can give a nice increase in performance, but beware of
984 broken drivers that do not properly invalidate/flush their
987 Write Through Policy:
988 Cached data will always be written back to SDRAM when the
989 cache is updated. This is a completely safe setting, but
990 performance is worse than Write Back.
992 If you are unsure of the options and you want to be safe,
993 then go with Write Through.
997 config BFIN_L2_DCACHEABLE
998 bool "Enable DCACHE for L2 SRAM"
999 depends on BFIN_DCACHE
1000 depends on (BF54x || BF561) && !SMP
1003 prompt "L2 SRAM DCACHE policy"
1004 depends on BFIN_L2_DCACHEABLE
1005 default BFIN_L2_WRITEBACK
1006 config BFIN_L2_WRITEBACK
1009 config BFIN_L2_WRITETHROUGH
1010 bool "Write through"
1014 comment "Memory Protection Unit"
1016 bool "Enable the memory protection unit (EXPERIMENTAL)"
1019 Use the processor's MPU to protect applications from accessing
1020 memory they do not own. This comes at a performance penalty
1021 and is recommended only for debugging.
1023 comment "Asynchronous Memory Configuration"
1025 menu "EBIU_AMGCTL Global Control"
1027 bool "Enable CLKOUT"
1031 bool "DMA has priority over core for ext. accesses"
1036 bool "Bank 0 16 bit packing enable"
1041 bool "Bank 1 16 bit packing enable"
1046 bool "Bank 2 16 bit packing enable"
1051 bool "Bank 3 16 bit packing enable"
1055 prompt "Enable Asynchronous Memory Banks"
1059 bool "Disable All Banks"
1062 bool "Enable Bank 0"
1064 config C_AMBEN_B0_B1
1065 bool "Enable Bank 0 & 1"
1067 config C_AMBEN_B0_B1_B2
1068 bool "Enable Bank 0 & 1 & 2"
1071 bool "Enable All Banks"
1075 menu "EBIU_AMBCTL Control"
1077 hex "Bank 0 (AMBCTL0.L)"
1080 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1081 used to control the Asynchronous Memory Bank 0 settings.
1084 hex "Bank 1 (AMBCTL0.H)"
1086 default 0x5558 if BF54x
1088 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1089 used to control the Asynchronous Memory Bank 1 settings.
1092 hex "Bank 2 (AMBCTL1.L)"
1095 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1096 used to control the Asynchronous Memory Bank 2 settings.
1099 hex "Bank 3 (AMBCTL1.H)"
1102 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1103 used to control the Asynchronous Memory Bank 3 settings.
1107 config EBIU_MBSCTLVAL
1108 hex "EBIU Bank Select Control Register"
1113 hex "Flash Memory Mode Control Register"
1118 hex "Flash Memory Bank Control Register"
1123 #############################################################################
1124 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1130 Support for PCI bus.
1132 source "drivers/pci/Kconfig"
1134 source "drivers/pcmcia/Kconfig"
1136 source "drivers/pci/hotplug/Kconfig"
1140 menu "Executable file formats"
1142 source "fs/Kconfig.binfmt"
1146 menu "Power management options"
1148 source "kernel/power/Kconfig"
1150 config ARCH_SUSPEND_POSSIBLE
1154 prompt "Standby Power Saving Mode"
1156 default PM_BFIN_SLEEP_DEEPER
1157 config PM_BFIN_SLEEP_DEEPER
1160 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1161 power dissipation by disabling the clock to the processor core (CCLK).
1162 Furthermore, Standby sets the internal power supply voltage (VDDINT)
1163 to 0.85 V to provide the greatest power savings, while preserving the
1165 The PLL and system clock (SCLK) continue to operate at a very low
1166 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1167 the SDRAM is put into Self Refresh Mode. Typically an external event
1168 such as GPIO interrupt or RTC activity wakes up the processor.
1169 Various Peripherals such as UART, SPORT, PPI may not function as
1170 normal during Sleep Deeper, due to the reduced SCLK frequency.
1171 When in the sleep mode, system DMA access to L1 memory is not supported.
1173 If unsure, select "Sleep Deeper".
1175 config PM_BFIN_SLEEP
1178 Sleep Mode (High Power Savings) - The sleep mode reduces power
1179 dissipation by disabling the clock to the processor core (CCLK).
1180 The PLL and system clock (SCLK), however, continue to operate in
1181 this mode. Typically an external event or RTC activity will wake
1182 up the processor. When in the sleep mode, system DMA access to L1
1183 memory is not supported.
1185 If unsure, select "Sleep Deeper".
1188 config PM_WAKEUP_BY_GPIO
1189 bool "Allow Wakeup from Standby by GPIO"
1190 depends on PM && !BF54x
1192 config PM_WAKEUP_GPIO_NUMBER
1195 depends on PM_WAKEUP_BY_GPIO
1199 prompt "GPIO Polarity"
1200 depends on PM_WAKEUP_BY_GPIO
1201 default PM_WAKEUP_GPIO_POLAR_H
1202 config PM_WAKEUP_GPIO_POLAR_H
1204 config PM_WAKEUP_GPIO_POLAR_L
1206 config PM_WAKEUP_GPIO_POLAR_EDGE_F
1208 config PM_WAKEUP_GPIO_POLAR_EDGE_R
1210 config PM_WAKEUP_GPIO_POLAR_EDGE_B
1214 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1217 config PM_BFIN_WAKE_PH6
1218 bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1219 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1222 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1224 config PM_BFIN_WAKE_GP
1225 bool "Allow Wake-Up from GPIOs"
1226 depends on PM && BF54x
1229 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1230 (all processors, except ADSP-BF549). This option sets
1231 the general-purpose wake-up enable (GPWE) control bit to enable
1232 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1233 On ADSP-BF549 this option enables the the same functionality on the
1234 /MRXON pin also PH7.
1238 menu "CPU Frequency scaling"
1241 source "drivers/cpufreq/Kconfig"
1243 config BFIN_CPU_FREQ
1246 select CPU_FREQ_TABLE
1250 bool "CPU Voltage scaling"
1251 depends on EXPERIMENTAL
1255 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1256 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1257 manuals. There is a theoretical risk that during VDDINT transitions
1262 source "net/Kconfig"
1264 source "drivers/Kconfig"
1266 source "drivers/firmware/Kconfig"
1270 source "arch/blackfin/Kconfig.debug"
1272 source "security/Kconfig"
1274 source "crypto/Kconfig"
1276 source "lib/Kconfig"
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob