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   1 /*
   2  *  linux/arch/arm/plat-versatile/timer-sp.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/clocksource.h>
  22 #include <linux/clockchips.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26
  27 #include <asm/hardware/arm_timer.h>
  28
  29 #include <mach/platform.h>
  30
  31 #include <plat/timer-sp.h>
  32
  33 /*
  34  * How long is the timer interval?
  35  */
  36 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
  37 #if TIMER_INTERVAL >= 0x100000
  38 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
  39 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
  40 #elif TIMER_INTERVAL >= 0x10000
  41 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
  42 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
  43 #else
  44 #define TIMER_RELOAD    (TIMER_INTERVAL)
  45 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
  46 #endif
  47
  48
  49 static void __iomem *clksrc_base;
  50
  51 static cycle_t sp804_read(struct clocksource *cs)
  52 {
  53         return ~readl(clksrc_base + TIMER_VALUE);
  54 }
  55
  56 static struct clocksource clocksource_sp804 = {
  57         .name           = "timer3",
  58         .rating         = 200,
  59         .read           = sp804_read,
  60         .mask           = CLOCKSOURCE_MASK(32),
  61         .shift          = 20,
  62         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  63 };
  64
  65 void __init sp804_clocksource_init(void __iomem *base)
  66 {
  67         struct clocksource *cs = &clocksource_sp804;
  68
  69         clksrc_base = base;
  70
  71         /* setup timer 0 as free-running clocksource */
  72         writel(0, clksrc_base + TIMER_CTRL);
  73         writel(0xffffffff, clksrc_base + TIMER_LOAD);
  74         writel(0xffffffff, clksrc_base + TIMER_VALUE);
  75         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
  76                 clksrc_base + TIMER_CTRL);
  77
  78         cs->mult = clocksource_khz2mult(1000, cs->shift);
  79         clocksource_register(cs);
  80 }
  81
  82
  83 static void __iomem *clkevt_base;
  84
  85 /*
  86  * IRQ handler for the timer
  87  */
  88 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
  89 {
  90         struct clock_event_device *evt = dev_id;
  91
  92         /* clear the interrupt */
  93         writel(1, clkevt_base + TIMER_INTCLR);
  94
  95         evt->event_handler(evt);
  96
  97         return IRQ_HANDLED;
  98 }
  99
 100 static void sp804_set_mode(enum clock_event_mode mode,
 101         struct clock_event_device *evt)
 102 {
 103         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 104
 105         writel(ctrl, clkevt_base + TIMER_CTRL);
 106
 107         switch (mode) {
 108         case CLOCK_EVT_MODE_PERIODIC:
 109                 writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
 110                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 111                 break;
 112
 113         case CLOCK_EVT_MODE_ONESHOT:
 114                 /* period set, and timer enabled in 'next_event' hook */
 115                 ctrl |= TIMER_CTRL_ONESHOT;
 116                 break;
 117
 118         case CLOCK_EVT_MODE_UNUSED:
 119         case CLOCK_EVT_MODE_SHUTDOWN:
 120         default:
 121                 break;
 122         }
 123
 124         writel(ctrl, clkevt_base + TIMER_CTRL);
 125 }
 126
 127 static int sp804_set_next_event(unsigned long next,
 128         struct clock_event_device *evt)
 129 {
 130         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 131
 132         writel(next, clkevt_base + TIMER_LOAD);
 133         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 134
 135         return 0;
 136 }
 137
 138 static struct clock_event_device sp804_clockevent = {
 139         .name           = "timer0",
 140         .shift          = 32,
 141         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 142         .set_mode       = sp804_set_mode,
 143         .set_next_event = sp804_set_next_event,
 144         .rating         = 300,
 145         .cpumask        = cpu_all_mask,
 146 };
 147
 148 static struct irqaction sp804_timer_irq = {
 149         .name           = "timer",
 150         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 151         .handler        = sp804_timer_interrupt,
 152         .dev_id         = &sp804_clockevent,
 153 };
 154
 155 void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
 156 {
 157         struct clock_event_device *evt = &sp804_clockevent;
 158
 159         clkevt_base = base;
 160
 161         evt->irq = timer_irq;
 162         evt->mult = div_sc(1000000, NSEC_PER_SEC, evt->shift);
 163         evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
 164         evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 165
 166         setup_irq(timer_irq, &sp804_timer_irq);
 167         clockevents_register_device(evt);
 168 }