1 /* linux/arch/arm/plat-s3c64xx/dma.c
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/dmapool.h>
19 #include <linux/sysdev.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
28 #include <mach/irqs.h>
30 #include <plat/dma-plat.h>
31 #include <plat/regs-sys.h>
33 #include <asm/hardware/pl080.h>
35 /* dma channel state information */
38 struct sys_device sysdev;
41 struct s3c2410_dma_chan *channels;
45 /* pool to provide LLI buffers */
46 static struct dma_pool *dma_pool;
48 /* Debug configuration and code */
50 static unsigned char debug_show_buffs = 0;
52 static void dbg_showchan(struct s3c2410_dma_chan *chan)
54 pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
56 readl(chan->regs + PL080_CH_SRC_ADDR),
57 readl(chan->regs + PL080_CH_DST_ADDR),
58 readl(chan->regs + PL080_CH_LLI),
59 readl(chan->regs + PL080_CH_CONTROL),
60 readl(chan->regs + PL080S_CH_CONTROL2),
61 readl(chan->regs + PL080S_CH_CONFIG));
64 static void show_lli(struct pl080s_lli *lli)
66 pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
67 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
68 lli->control0, lli->control1);
71 static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
73 struct s3c64xx_dma_buff *ptr;
74 struct s3c64xx_dma_buff *end;
76 pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
77 chan->number, chan->next, chan->curr, chan->end);
82 if (debug_show_buffs) {
83 for (; ptr != NULL; ptr = ptr->next) {
84 pr_debug("DMA%d: %08x ",
85 chan->number, ptr->lli_dma);
93 static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
95 struct s3c2410_dma_chan *chan;
96 unsigned int start, offs;
100 if (channel >= DMACH_PCM1_TX)
103 for (offs = 0; offs < 8; offs++) {
104 chan = &s3c2410_chans[start + offs];
112 s3c_dma_chan_map[channel] = chan;
116 int s3c2410_dma_config(unsigned int channel, int xferunit)
118 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
134 printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
140 EXPORT_SYMBOL(s3c2410_dma_config);
142 static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
143 struct pl080s_lli *lli,
144 dma_addr_t data, int size)
147 u32 control0, control1;
149 switch (chan->source) {
150 case S3C2410_DMASRC_HW:
151 src = chan->dev_addr;
153 control0 = PL080_CONTROL_SRC_AHB2;
154 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
155 control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
156 control0 |= PL080_CONTROL_DST_INCR;
159 case S3C2410_DMASRC_MEM:
161 dst = chan->dev_addr;
162 control0 = PL080_CONTROL_DST_AHB2;
163 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
164 control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
165 control0 |= PL080_CONTROL_SRC_INCR;
171 /* note, we do not currently setup any of the burst controls */
173 control1 = size >> chan->hw_width; /* size in no of xfers */
174 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
175 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
180 lli->control0 = control0;
181 lli->control1 = control1;
184 static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
185 struct pl080s_lli *lli)
187 void __iomem *regs = chan->regs;
189 pr_debug("%s: LLI %p => regs\n", __func__, lli);
192 writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
193 writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
194 writel(lli->next_lli, regs + PL080_CH_LLI);
195 writel(lli->control0, regs + PL080_CH_CONTROL);
196 writel(lli->control1, regs + PL080S_CH_CONTROL2);
199 static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
201 struct s3c64xx_dmac *dmac = chan->dmac;
207 pr_debug("%s: clearing interrupts\n", __func__);
209 /* clear interrupts */
210 writel(bit, dmac->regs + PL080_TC_CLEAR);
211 writel(bit, dmac->regs + PL080_ERR_CLEAR);
213 pr_debug("%s: starting channel\n", __func__);
215 config = readl(chan->regs + PL080S_CH_CONFIG);
216 config |= PL080_CONFIG_ENABLE;
218 pr_debug("%s: writing config %08x\n", __func__, config);
219 writel(config, chan->regs + PL080S_CH_CONFIG);
224 static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
229 pr_debug("%s: stopping channel\n", __func__);
233 config = readl(chan->regs + PL080S_CH_CONFIG);
234 config |= PL080_CONFIG_HALT;
235 writel(config, chan->regs + PL080S_CH_CONFIG);
239 config = readl(chan->regs + PL080S_CH_CONFIG);
240 pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
241 if (config & PL080_CONFIG_ACTIVE)
245 } while (--timeout > 0);
247 if (config & PL080_CONFIG_ACTIVE) {
248 printk(KERN_ERR "%s: channel still active\n", __func__);
252 config = readl(chan->regs + PL080S_CH_CONFIG);
253 config &= ~PL080_CONFIG_ENABLE;
254 writel(config, chan->regs + PL080S_CH_CONFIG);
259 static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
260 struct s3c64xx_dma_buff *buf,
261 enum s3c2410_dma_buffresult result)
263 if (chan->callback_fn != NULL)
264 (chan->callback_fn)(chan, buf->pw, 0, result);
267 static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
269 dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
273 static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
275 struct s3c64xx_dma_buff *buff, *next;
280 pr_debug("%s: flushing channel\n", __func__);
282 config = readl(chan->regs + PL080S_CH_CONFIG);
283 config &= ~PL080_CONFIG_ENABLE;
284 writel(config, chan->regs + PL080S_CH_CONFIG);
286 /* dump all the buffers associated with this channel */
288 for (buff = chan->curr; buff != NULL; buff = next) {
290 pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
292 s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
293 s3c64xx_dma_freebuff(buff);
296 chan->curr = chan->next = chan->end = NULL;
301 int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
303 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
310 case S3C2410_DMAOP_START:
311 return s3c64xx_dma_start(chan);
313 case S3C2410_DMAOP_STOP:
314 return s3c64xx_dma_stop(chan);
316 case S3C2410_DMAOP_FLUSH:
317 return s3c64xx_dma_flush(chan);
319 /* belive PAUSE/RESUME are no-ops */
320 case S3C2410_DMAOP_PAUSE:
321 case S3C2410_DMAOP_RESUME:
322 case S3C2410_DMAOP_STARTED:
323 case S3C2410_DMAOP_TIMEOUT:
329 EXPORT_SYMBOL(s3c2410_dma_ctrl);
335 int s3c2410_dma_enqueue(unsigned int channel, void *id,
336 dma_addr_t data, int size)
338 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
339 struct s3c64xx_dma_buff *next;
340 struct s3c64xx_dma_buff *buff;
341 struct pl080s_lli *lli;
349 buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC);
351 printk(KERN_ERR "%s: no memory for buffer\n", __func__);
355 lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma);
357 printk(KERN_ERR "%s: no memory for lli\n", __func__);
362 pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
363 __func__, buff, data, lli, (u32)buff->lli_dma, size);
368 s3c64xx_dma_fill_lli(chan, lli, data, size);
370 local_irq_save(flags);
372 if ((next = chan->next) != NULL) {
373 struct s3c64xx_dma_buff *end = chan->end;
374 struct pl080s_lli *endlli = end->lli;
376 pr_debug("enquing onto channel\n");
379 endlli->next_lli = buff->lli_dma;
381 if (chan->flags & S3C2410_DMAF_CIRCULAR) {
382 struct s3c64xx_dma_buff *curr = chan->curr;
383 lli->next_lli = curr->lli_dma;
386 if (next == chan->curr) {
387 writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
394 pr_debug("enquing onto empty channel\n");
400 s3c64xx_lli_to_regs(chan, lli);
403 local_irq_restore(flags);
416 EXPORT_SYMBOL(s3c2410_dma_enqueue);
419 int s3c2410_dma_devconfig(int channel,
420 enum s3c2410_dmasrc source,
421 unsigned long devaddr)
423 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
427 pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
428 __func__, channel, source, devaddr, chan);
434 peripheral = (chan->peripheral & 0xf);
435 chan->source = source;
436 chan->dev_addr = devaddr;
438 pr_debug("%s: peripheral %d\n", __func__, peripheral);
441 case S3C2410_DMASRC_HW:
442 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
443 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
445 case S3C2410_DMASRC_MEM:
446 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
447 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
450 printk(KERN_ERR "%s: bad source\n", __func__);
454 /* allow TC and ERR interrupts */
455 config |= PL080_CONFIG_TC_IRQ_MASK;
456 config |= PL080_CONFIG_ERR_IRQ_MASK;
458 pr_debug("%s: config %08x\n", __func__, config);
460 writel(config, chan->regs + PL080S_CH_CONFIG);
464 EXPORT_SYMBOL(s3c2410_dma_devconfig);
467 int s3c2410_dma_getposition(unsigned int channel,
468 dma_addr_t *src, dma_addr_t *dst)
470 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
477 *src = readl(chan->regs + PL080_CH_SRC_ADDR);
480 *dst = readl(chan->regs + PL080_CH_DST_ADDR);
484 EXPORT_SYMBOL(s3c2410_dma_getposition);
486 /* s3c2410_request_dma
488 * get control of an dma channel
491 int s3c2410_dma_request(unsigned int channel,
492 struct s3c2410_dma_client *client,
495 struct s3c2410_dma_chan *chan;
498 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
499 channel, client->name, dev);
501 local_irq_save(flags);
503 chan = s3c64xx_dma_map_channel(channel);
505 local_irq_restore(flags);
511 chan->client = client;
513 chan->peripheral = channel;
515 local_irq_restore(flags);
519 pr_debug("%s: channel initialised, %p\n", __func__, chan);
521 return chan->number | DMACH_LOW_LEVEL;
524 EXPORT_SYMBOL(s3c2410_dma_request);
528 * release the given channel back to the system, will stop and flush
529 * any outstanding transfers, and ensure the channel is ready for the
532 * Note, although a warning is currently printed if the freeing client
533 * info is not the same as the registrant's client info, the free is still
534 * allowed to go through.
537 int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
539 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
545 local_irq_save(flags);
547 if (chan->client != client) {
548 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
549 channel, chan->client, client);
552 /* sort out stopping and freeing the channel */
558 if (!(channel & DMACH_LOW_LEVEL))
559 s3c_dma_chan_map[channel] = NULL;
561 local_irq_restore(flags);
566 EXPORT_SYMBOL(s3c2410_dma_free);
568 static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
570 struct s3c64xx_dmac *dmac = pw;
571 struct s3c2410_dma_chan *chan;
572 enum s3c2410_dma_buffresult res;
577 tcstat = readl(dmac->regs + PL080_TC_STATUS);
578 errstat = readl(dmac->regs + PL080_ERR_STATUS);
580 for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
582 if (!(errstat & bit) && !(tcstat & bit))
585 chan = dmac->channels + offs;
586 res = S3C2410_RES_ERR;
589 writel(bit, dmac->regs + PL080_TC_CLEAR);
590 res = S3C2410_RES_OK;
594 writel(bit, dmac->regs + PL080_ERR_CLEAR);
596 s3c64xx_dma_bufffdone(chan, chan->curr, res);
602 static struct sysdev_class dma_sysclass = {
603 .name = "s3c64xx-dma",
606 static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
607 int irq, unsigned int base)
609 struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
610 struct s3c64xx_dmac *dmac;
613 void __iomem *regptr;
616 dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
618 printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
622 dmac->sysdev.id = chno / 8;
623 dmac->sysdev.cls = &dma_sysclass;
625 err = sysdev_register(&dmac->sysdev);
627 printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
631 regs = ioremap(base, 0x200);
633 printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
638 snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
640 dmac->clk = clk_get(NULL, clkname);
641 if (IS_ERR(dmac->clk)) {
642 printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
643 err = PTR_ERR(dmac->clk);
647 clk_enable(dmac->clk);
650 dmac->chanbase = chbase;
651 dmac->channels = chptr;
653 err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
655 printk(KERN_ERR "%s: failed to get irq\n", __func__);
659 regptr = regs + PL080_Cx_BASE(0);
661 for (ch = 0; ch < 8; ch++, chno++, chptr++) {
662 printk(KERN_INFO "%s: registering DMA %d (%p)\n",
663 __func__, chno, regptr);
665 chptr->bit = 1 << ch;
666 chptr->number = chno;
668 chptr->regs = regptr;
669 regptr += PL008_Cx_STRIDE;
672 /* for the moment, permanently enable the controller */
673 writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
675 printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
680 clk_disable(dmac->clk);
685 sysdev_unregister(&dmac->sysdev);
691 static int __init s3c64xx_dma_init(void)
695 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
697 dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
699 printk(KERN_ERR "%s: failed to create pool\n", __func__);
703 ret = sysdev_class_register(&dma_sysclass);
705 printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
709 /* Set all DMA configuration to be DMA, not SDMA */
710 writel(0xffffff, S3C_SYSREG(0x110));
712 /* Register standard DMA controlers */
713 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
714 s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
719 arch_initcall(s3c64xx_dma_init);