SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/plat-omap/include/plat/mux.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mux.h
   3  *
   4  * Table of the Omap register configurations for the FUNC_MUX and
   5  * PULL_DWN combinations.
   6  *
   7  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
   8  * Copyright (C) 2003 - 2008 Nokia Corporation
   9  *
  10  * Written by Tony Lindgren
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25  *
  26  * NOTE: Please use the following naming style for new pin entries.
  27  *       For example, W8_1610_MMC2_DAT0, where:
  28  *       - W8        = ball
  29  *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
  30  *       - MMC2_DAT0 = function
  31  */
  32
  33 #ifndef __ASM_ARCH_MUX_H
  34 #define __ASM_ARCH_MUX_H
  35
  36 #define PU_PD_SEL_NA            0       /* No pu_pd reg available */
  37 #define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
  38
  39 #ifdef  CONFIG_OMAP_MUX_DEBUG
  40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
  41                                         .mux_reg = FUNC_MUX_CTRL_##reg, \
  42                                         .mask_offset = mode_offset, \
  43                                         .mask = mode,
  44
  45 #define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
  46                                         .pull_reg = PULL_DWN_CTRL_##reg, \
  47                                         .pull_bit = bit, \
  48                                         .pull_val = status,
  49
  50 #define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
  51                                         .pu_pd_reg = PU_PD_SEL_##reg, \
  52                                         .pu_pd_val = status,
  53
  54 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
  55                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  56                                         .mask_offset = mode_offset, \
  57                                         .mask = mode,
  58
  59 #define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
  60                                         .pull_reg = OMAP7XX_IO_CONF_##reg, \
  61                                         .pull_bit = bit, \
  62                                         .pull_val = status,
  63
  64 #else
  65
  66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
  67                                         .mask_offset = mode_offset, \
  68                                         .mask = mode,
  69
  70 #define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
  71                                         .pull_bit = bit, \
  72                                         .pull_val = status,
  73
  74 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
  75                                         .pu_pd_val = status,
  76
  77 #define MUX_REG_7XX(reg, mode_offset, mode) \
  78                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  79                                         .mask_offset = mode_offset, \
  80                                         .mask = mode,
  81
  82 #define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
  83                                         .pull_bit = bit, \
  84                                         .pull_val = status,
  85
  86 #endif /* CONFIG_OMAP_MUX_DEBUG */
  87
  88 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
  89                 pull_reg, pull_bit, pull_status,        \
  90                 pu_pd_reg, pu_pd_status, debug_status)  \
  91 {                                                       \
  92         .name =  desc,                                  \
  93         .debug = debug_status,                          \
  94         MUX_REG(mux_reg, mode_offset, mode)             \
  95         PULL_REG(pull_reg, pull_bit, pull_status)       \
  96         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
  97 },
  98
  99
 100 /*
 101  * OMAP730/850 has a slightly different config for the pin mux.
 102  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
 103  *   not the FUNC_MUX_CTRL_x regs from hardware.h
 104  * - for pull-up/down, only has one enable bit which is is in the same register
 105  *   as mux config
 106  */
 107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
 108                    pull_bit, pull_status, debug_status)\
 109 {                                                       \
 110         .name =  desc,                                  \
 111         .debug = debug_status,                          \
 112         MUX_REG_7XX(mux_reg, mode_offset, mode)         \
 113         PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
 114         PU_PD_REG(NA, 0)                \
 115 },
 116
 117 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
 118                                 pull_en, pull_mode, dbg)        \
 119 {                                                               \
 120         .name           = desc,                                 \
 121         .debug          = dbg,                                  \
 122         .mux_reg        = reg_offset,                           \
 123         .mask           = mode,                                 \
 124         .pull_val       = pull_en,                              \
 125         .pu_pd_val      = pull_mode,                            \
 126 },
 127
 128 /* 24xx/34xx mux bit defines */
 129 #define OMAP2_PULL_ENA          (1 << 3)
 130 #define OMAP2_PULL_UP           (1 << 4)
 131 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
 132
 133 struct pin_config {
 134         char                    *name;
 135         const unsigned int      mux_reg;
 136         unsigned char           debug;
 137
 138 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
 139         const unsigned char mask_offset;
 140         const unsigned char mask;
 141
 142         const char *pull_name;
 143         const unsigned int pull_reg;
 144         const unsigned char pull_val;
 145         const unsigned char pull_bit;
 146
 147         const char *pu_pd_name;
 148         const unsigned int pu_pd_reg;
 149         const unsigned char pu_pd_val;
 150 #endif
 151
 152 #if     defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 153         const char *mux_reg_name;
 154 #endif
 155
 156 };
 157
 158 enum omap7xx_index {
 159         /* OMAP 730 keyboard */
 160         E2_7XX_KBR0,
 161         J7_7XX_KBR1,
 162         E1_7XX_KBR2,
 163         F3_7XX_KBR3,
 164         D2_7XX_KBR4,
 165         C2_7XX_KBC0,
 166         D3_7XX_KBC1,
 167         E4_7XX_KBC2,
 168         F4_7XX_KBC3,
 169         E3_7XX_KBC4,
 170
 171         /* USB */
 172         AA17_7XX_USB_DM,
 173         W16_7XX_USB_PU_EN,
 174         W17_7XX_USB_VBUSI,
 175         W18_7XX_USB_DMCK_OUT,
 176         W19_7XX_USB_DCRST,
 177
 178         /* MMC */
 179         MMC_7XX_CMD,
 180         MMC_7XX_CLK,
 181         MMC_7XX_DAT0,
 182 };
 183
 184 enum omap1xxx_index {
 185         /* UART1 (BT_UART_GATING)*/
 186         UART1_TX = 0,
 187         UART1_RTS,
 188
 189         /* UART2 (COM_UART_GATING)*/
 190         UART2_TX,
 191         UART2_RX,
 192         UART2_CTS,
 193         UART2_RTS,
 194
 195         /* UART3 (GIGA_UART_GATING) */
 196         UART3_TX,
 197         UART3_RX,
 198         UART3_CTS,
 199         UART3_RTS,
 200         UART3_CLKREQ,
 201         UART3_BCLK,     /* 12MHz clock out */
 202         Y15_1610_UART3_RTS,
 203
 204         /* PWT & PWL */
 205         PWT,
 206         PWL,
 207
 208         /* USB master generic */
 209         R18_USB_VBUS,
 210         R18_1510_USB_GPIO0,
 211         W4_USB_PUEN,
 212         W4_USB_CLKO,
 213         W4_USB_HIGHZ,
 214         W4_GPIO58,
 215
 216         /* USB1 master */
 217         USB1_SUSP,
 218         USB1_SEO,
 219         W13_1610_USB1_SE0,
 220         USB1_TXEN,
 221         USB1_TXD,
 222         USB1_VP,
 223         USB1_VM,
 224         USB1_RCV,
 225         USB1_SPEED,
 226         R13_1610_USB1_SPEED,
 227         R13_1710_USB1_SE0,
 228
 229         /* USB2 master */
 230         USB2_SUSP,
 231         USB2_VP,
 232         USB2_TXEN,
 233         USB2_VM,
 234         USB2_RCV,
 235         USB2_SEO,
 236         USB2_TXD,
 237
 238         /* OMAP-1510 GPIO */
 239         R18_1510_GPIO0,
 240         R19_1510_GPIO1,
 241         M14_1510_GPIO2,
 242
 243         /* OMAP1610 GPIO */
 244         P18_1610_GPIO3,
 245         Y15_1610_GPIO17,
 246
 247         /* OMAP-1710 GPIO */
 248         R18_1710_GPIO0,
 249         V2_1710_GPIO10,
 250         N21_1710_GPIO14,
 251         W15_1710_GPIO40,
 252
 253         /* MPUIO */
 254         MPUIO2,
 255         N15_1610_MPUIO2,
 256         MPUIO4,
 257         MPUIO5,
 258         T20_1610_MPUIO5,
 259         W11_1610_MPUIO6,
 260         V10_1610_MPUIO7,
 261         W11_1610_MPUIO9,
 262         V10_1610_MPUIO10,
 263         W10_1610_MPUIO11,
 264         E20_1610_MPUIO13,
 265         U20_1610_MPUIO14,
 266         E19_1610_MPUIO15,
 267
 268         /* MCBSP2 */
 269         MCBSP2_CLKR,
 270         MCBSP2_CLKX,
 271         MCBSP2_DR,
 272         MCBSP2_DX,
 273         MCBSP2_FSR,
 274         MCBSP2_FSX,
 275
 276         /* MCBSP3 */
 277         MCBSP3_CLKX,
 278
 279         /* Misc ballouts */
 280         BALLOUT_V8_ARMIO3,
 281         N20_HDQ,
 282
 283         /* OMAP-1610 MMC2 */
 284         W8_1610_MMC2_DAT0,
 285         V8_1610_MMC2_DAT1,
 286         W15_1610_MMC2_DAT2,
 287         R10_1610_MMC2_DAT3,
 288         Y10_1610_MMC2_CLK,
 289         Y8_1610_MMC2_CMD,
 290         V9_1610_MMC2_CMDDIR,
 291         V5_1610_MMC2_DATDIR0,
 292         W19_1610_MMC2_DATDIR1,
 293         R18_1610_MMC2_CLKIN,
 294
 295         /* OMAP-1610 External Trace Interface */
 296         M19_1610_ETM_PSTAT0,
 297         L15_1610_ETM_PSTAT1,
 298         L18_1610_ETM_PSTAT2,
 299         L19_1610_ETM_D0,
 300         J19_1610_ETM_D6,
 301         J18_1610_ETM_D7,
 302
 303         /* OMAP16XX GPIO */
 304         P20_1610_GPIO4,
 305         V9_1610_GPIO7,
 306         W8_1610_GPIO9,
 307         N20_1610_GPIO11,
 308         N19_1610_GPIO13,
 309         P10_1610_GPIO22,
 310         V5_1610_GPIO24,
 311         AA20_1610_GPIO_41,
 312         W19_1610_GPIO48,
 313         M7_1610_GPIO62,
 314         V14_16XX_GPIO37,
 315         R9_16XX_GPIO18,
 316         L14_16XX_GPIO49,
 317
 318         /* OMAP-1610 uWire */
 319         V19_1610_UWIRE_SCLK,
 320         U18_1610_UWIRE_SDI,
 321         W21_1610_UWIRE_SDO,
 322         N14_1610_UWIRE_CS0,
 323         P15_1610_UWIRE_CS3,
 324         N15_1610_UWIRE_CS1,
 325
 326         /* OMAP-1610 SPI */
 327         U19_1610_SPIF_SCK,
 328         U18_1610_SPIF_DIN,
 329         P20_1610_SPIF_DIN,
 330         W21_1610_SPIF_DOUT,
 331         R18_1610_SPIF_DOUT,
 332         N14_1610_SPIF_CS0,
 333         N15_1610_SPIF_CS1,
 334         T19_1610_SPIF_CS2,
 335         P15_1610_SPIF_CS3,
 336
 337         /* OMAP-1610 Flash */
 338         L3_1610_FLASH_CS2B_OE,
 339         M8_1610_FLASH_CS2B_WE,
 340
 341         /* First MMC */
 342         MMC_CMD,
 343         MMC_DAT1,
 344         MMC_DAT2,
 345         MMC_DAT0,
 346         MMC_CLK,
 347         MMC_DAT3,
 348
 349         /* OMAP-1710 MMC CMDDIR and DATDIR0 */
 350         M15_1710_MMC_CLKI,
 351         P19_1710_MMC_CMDDIR,
 352         P20_1710_MMC_DATDIR0,
 353
 354         /* OMAP-1610 USB0 alternate pin configuration */
 355         W9_USB0_TXEN,
 356         AA9_USB0_VP,
 357         Y5_USB0_RCV,
 358         R9_USB0_VM,
 359         V6_USB0_TXD,
 360         W5_USB0_SE0,
 361         V9_USB0_SPEED,
 362         V9_USB0_SUSP,
 363
 364         /* USB2 */
 365         W9_USB2_TXEN,
 366         AA9_USB2_VP,
 367         Y5_USB2_RCV,
 368         R9_USB2_VM,
 369         V6_USB2_TXD,
 370         W5_USB2_SE0,
 371
 372         /* 16XX UART */
 373         R13_1610_UART1_TX,
 374         V14_16XX_UART1_RX,
 375         R14_1610_UART1_CTS,
 376         AA15_1610_UART1_RTS,
 377         R9_16XX_UART2_RX,
 378         L14_16XX_UART3_RX,
 379
 380         /* I2C OMAP-1610 */
 381         I2C_SCL,
 382         I2C_SDA,
 383
 384         /* Keypad */
 385         F18_1610_KBC0,
 386         D20_1610_KBC1,
 387         D19_1610_KBC2,
 388         E18_1610_KBC3,
 389         C21_1610_KBC4,
 390         G18_1610_KBR0,
 391         F19_1610_KBR1,
 392         H14_1610_KBR2,
 393         E20_1610_KBR3,
 394         E19_1610_KBR4,
 395         N19_1610_KBR5,
 396
 397         /* Power management */
 398         T20_1610_LOW_PWR,
 399
 400         /* MCLK Settings */
 401         V5_1710_MCLK_ON,
 402         V5_1710_MCLK_OFF,
 403         R10_1610_MCLK_ON,
 404         R10_1610_MCLK_OFF,
 405
 406         /* CompactFlash controller */
 407         P11_1610_CF_CD2,
 408         R11_1610_CF_IOIS16,
 409         V10_1610_CF_IREQ,
 410         W10_1610_CF_RESET,
 411         W11_1610_CF_CD1,
 412
 413         /* parallel camera */
 414         J15_1610_CAM_LCLK,
 415         J18_1610_CAM_D7,
 416         J19_1610_CAM_D6,
 417         J14_1610_CAM_D5,
 418         K18_1610_CAM_D4,
 419         K19_1610_CAM_D3,
 420         K15_1610_CAM_D2,
 421         K14_1610_CAM_D1,
 422         L19_1610_CAM_D0,
 423         L18_1610_CAM_VS,
 424         L15_1610_CAM_HS,
 425         M19_1610_CAM_RSTZ,
 426         Y15_1610_CAM_OUTCLK,
 427
 428         /* serial camera */
 429         H19_1610_CAM_EXCLK,
 430         Y12_1610_CCP_CLKP,
 431         W13_1610_CCP_CLKM,
 432         W14_1610_CCP_DATAP,
 433         Y14_1610_CCP_DATAM,
 434
 435 };
 436
 437 enum omap24xx_index {
 438         /* 24xx I2C */
 439         M19_24XX_I2C1_SCL,
 440         L15_24XX_I2C1_SDA,
 441         J15_24XX_I2C2_SCL,
 442         H19_24XX_I2C2_SDA,
 443
 444         /* 24xx Menelaus interrupt */
 445         W19_24XX_SYS_NIRQ,
 446
 447         /* 24xx clock */
 448         W14_24XX_SYS_CLKOUT,
 449
 450         /* 24xx GPMC chipselects, wait pin monitoring */
 451         E2_GPMC_NCS2,
 452         L2_GPMC_NCS7,
 453         L3_GPMC_WAIT0,
 454         N7_GPMC_WAIT1,
 455         M1_GPMC_WAIT2,
 456         P1_GPMC_WAIT3,
 457
 458         /* 242X McBSP */
 459         Y15_24XX_MCBSP2_CLKX,
 460         R14_24XX_MCBSP2_FSX,
 461         W15_24XX_MCBSP2_DR,
 462         V15_24XX_MCBSP2_DX,
 463
 464         /* 24xx GPIO */
 465         M21_242X_GPIO11,
 466         P21_242X_GPIO12,
 467         AA10_242X_GPIO13,
 468         AA6_242X_GPIO14,
 469         AA4_242X_GPIO15,
 470         Y11_242X_GPIO16,
 471         AA12_242X_GPIO17,
 472         AA8_242X_GPIO58,
 473         Y20_24XX_GPIO60,
 474         W4__24XX_GPIO74,
 475         N15_24XX_GPIO85,
 476         M15_24XX_GPIO92,
 477         P20_24XX_GPIO93,
 478         P18_24XX_GPIO95,
 479         M18_24XX_GPIO96,
 480         L14_24XX_GPIO97,
 481         J15_24XX_GPIO99,
 482         V14_24XX_GPIO117,
 483         P14_24XX_GPIO125,
 484
 485         /* 242x DBG GPIO */
 486         V4_242X_GPIO49,
 487         W2_242X_GPIO50,
 488         U4_242X_GPIO51,
 489         V3_242X_GPIO52,
 490         V2_242X_GPIO53,
 491         V6_242X_GPIO53,
 492         T4_242X_GPIO54,
 493         Y4_242X_GPIO54,
 494         T3_242X_GPIO55,
 495         U2_242X_GPIO56,
 496
 497         /* 24xx external DMA requests */
 498         AA10_242X_DMAREQ0,
 499         AA6_242X_DMAREQ1,
 500         E4_242X_DMAREQ2,
 501         G4_242X_DMAREQ3,
 502         D3_242X_DMAREQ4,
 503         E3_242X_DMAREQ5,
 504
 505         /* UART3 */
 506         K15_24XX_UART3_TX,
 507         K14_24XX_UART3_RX,
 508
 509         /* MMC/SDIO */
 510         G19_24XX_MMC_CLKO,
 511         H18_24XX_MMC_CMD,
 512         F20_24XX_MMC_DAT0,
 513         H14_24XX_MMC_DAT1,
 514         E19_24XX_MMC_DAT2,
 515         D19_24XX_MMC_DAT3,
 516         F19_24XX_MMC_DAT_DIR0,
 517         E20_24XX_MMC_DAT_DIR1,
 518         F18_24XX_MMC_DAT_DIR2,
 519         E18_24XX_MMC_DAT_DIR3,
 520         G18_24XX_MMC_CMD_DIR,
 521         H15_24XX_MMC_CLKI,
 522
 523         /* Full speed USB */
 524         J20_24XX_USB0_PUEN,
 525         J19_24XX_USB0_VP,
 526         K20_24XX_USB0_VM,
 527         J18_24XX_USB0_RCV,
 528         K19_24XX_USB0_TXEN,
 529         J14_24XX_USB0_SE0,
 530         K18_24XX_USB0_DAT,
 531
 532         N14_24XX_USB1_SE0,
 533         W12_24XX_USB1_SE0,
 534         P15_24XX_USB1_DAT,
 535         R13_24XX_USB1_DAT,
 536         W20_24XX_USB1_TXEN,
 537         P13_24XX_USB1_TXEN,
 538         V19_24XX_USB1_RCV,
 539         V12_24XX_USB1_RCV,
 540
 541         AA10_24XX_USB2_SE0,
 542         Y11_24XX_USB2_DAT,
 543         AA12_24XX_USB2_TXEN,
 544         AA6_24XX_USB2_RCV,
 545         AA4_24XX_USB2_TLLSE0,
 546
 547         /* Keypad GPIO*/
 548         T19_24XX_KBR0,
 549         R19_24XX_KBR1,
 550         V18_24XX_KBR2,
 551         M21_24XX_KBR3,
 552         E5__24XX_KBR4,
 553         M18_24XX_KBR5,
 554         R20_24XX_KBC0,
 555         M14_24XX_KBC1,
 556         H19_24XX_KBC2,
 557         V17_24XX_KBC3,
 558         P21_24XX_KBC4,
 559         L14_24XX_KBC5,
 560         N19_24XX_KBC6,
 561
 562         /* 24xx Menelaus Keypad GPIO */
 563         B3__24XX_KBR5,
 564         AA4_24XX_KBC2,
 565         B13_24XX_KBC6,
 566
 567         /* 2430 USB */
 568         AD9_2430_USB0_PUEN,
 569         Y11_2430_USB0_VP,
 570         AD7_2430_USB0_VM,
 571         AE7_2430_USB0_RCV,
 572         AD4_2430_USB0_TXEN,
 573         AF9_2430_USB0_SE0,
 574         AE6_2430_USB0_DAT,
 575         AD24_2430_USB1_SE0,
 576         AB24_2430_USB1_RCV,
 577         Y25_2430_USB1_TXEN,
 578         AA26_2430_USB1_DAT,
 579
 580         /* 2430 HS-USB */
 581         AD9_2430_USB0HS_DATA3,
 582         Y11_2430_USB0HS_DATA4,
 583         AD7_2430_USB0HS_DATA5,
 584         AE7_2430_USB0HS_DATA6,
 585         AD4_2430_USB0HS_DATA2,
 586         AF9_2430_USB0HS_DATA0,
 587         AE6_2430_USB0HS_DATA1,
 588         AE8_2430_USB0HS_CLK,
 589         AD8_2430_USB0HS_DIR,
 590         AE5_2430_USB0HS_STP,
 591         AE9_2430_USB0HS_NXT,
 592         AC7_2430_USB0HS_DATA7,
 593
 594         /* 2430 McBSP */
 595         AD6_2430_MCBSP_CLKS,
 596
 597         AB2_2430_MCBSP1_CLKR,
 598         AD5_2430_MCBSP1_FSR,
 599         AA1_2430_MCBSP1_DX,
 600         AF3_2430_MCBSP1_DR,
 601         AB3_2430_MCBSP1_FSX,
 602         Y9_2430_MCBSP1_CLKX,
 603
 604         AC10_2430_MCBSP2_FSX,
 605         AD16_2430_MCBSP2_CLX,
 606         AE13_2430_MCBSP2_DX,
 607         AD13_2430_MCBSP2_DR,
 608         AC10_2430_MCBSP2_FSX_OFF,
 609         AD16_2430_MCBSP2_CLX_OFF,
 610         AE13_2430_MCBSP2_DX_OFF,
 611         AD13_2430_MCBSP2_DR_OFF,
 612
 613         AC9_2430_MCBSP3_CLKX,
 614         AE4_2430_MCBSP3_FSX,
 615         AE2_2430_MCBSP3_DR,
 616         AF4_2430_MCBSP3_DX,
 617
 618         N3_2430_MCBSP4_CLKX,
 619         AD23_2430_MCBSP4_DR,
 620         AB25_2430_MCBSP4_DX,
 621         AC25_2430_MCBSP4_FSX,
 622
 623         AE16_2430_MCBSP5_CLKX,
 624         AF12_2430_MCBSP5_FSX,
 625         K7_2430_MCBSP5_DX,
 626         M1_2430_MCBSP5_DR,
 627
 628         /* 2430 McSPI*/
 629         Y18_2430_MCSPI1_CLK,
 630         AD15_2430_MCSPI1_SIMO,
 631         AE17_2430_MCSPI1_SOMI,
 632         U1_2430_MCSPI1_CS0,
 633
 634         /* Touchscreen GPIO */
 635         AF19_2430_GPIO_85,
 636
 637 };
 638
 639 struct omap_mux_cfg {
 640         struct pin_config       *pins;
 641         unsigned long           size;
 642         int                     (*cfg_reg)(const struct pin_config *cfg);
 643 };
 644
 645 #ifdef  CONFIG_OMAP_MUX
 646 /* setup pin muxing in Linux */
 647 extern int omap1_mux_init(void);
 648 extern int omap_mux_register(struct omap_mux_cfg *);
 649 extern int omap_cfg_reg(unsigned long reg_cfg);
 650 #else
 651 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 652 static inline int omap1_mux_init(void) { return 0; }
 653 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 654 #endif
 655
 656 extern int omap2_mux_init(void);
 657
 658 #endif