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   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/irq.h>
  30 #include <asm/hardware.h>
  31 #include <asm/dma.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/arch/tc.h>
  35
  36 #define DEBUG_PRINTS
  37 #undef DEBUG_PRINTS
  38 #ifdef DEBUG_PRINTS
  39 #define debug_printk(x) printk x
  40 #else
  41 #define debug_printk(x)
  42 #endif
  43
  44 #define OMAP_DMA_ACTIVE         0x01
  45 #define OMAP_DMA_CCR_EN         (1 << 7)
  46
  47 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  48
  49 static int enable_1510_mode = 0;
  50
  51 struct omap_dma_lch {
  52         int next_lch;
  53         int dev_id;
  54         u16 saved_csr;
  55         u16 enabled_irqs;
  56         const char *dev_name;
  57         void (* callback)(int lch, u16 ch_status, void *data);
  58         void *data;
  59         long flags;
  60 };
  61
  62 static int dma_chan_count;
  63
  64 static spinlock_t dma_chan_lock;
  65 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
  66
  67 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
  68         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
  69         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
  70         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
  71         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
  72         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
  73 };
  74
  75 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
  76                                                 __FUNCTION__);
  77
  78 #ifdef CONFIG_ARCH_OMAP15XX
  79 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
  80 int omap_dma_in_1510_mode(void)
  81 {
  82         return enable_1510_mode;
  83 }
  84 #else
  85 #define omap_dma_in_1510_mode()         0
  86 #endif
  87
  88 #ifdef CONFIG_ARCH_OMAP1
  89 static inline int get_gdma_dev(int req)
  90 {
  91         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
  92         int shift = ((req - 1) % 5) * 6;
  93
  94         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
  95 }
  96
  97 static inline void set_gdma_dev(int req, int dev)
  98 {
  99         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 100         int shift = ((req - 1) % 5) * 6;
 101         u32 l;
 102
 103         l = omap_readl(reg);
 104         l &= ~(0x3f << shift);
 105         l |= (dev - 1) << shift;
 106         omap_writel(l, reg);
 107 }
 108 #else
 109 #define set_gdma_dev(req, dev)  do {} while (0)
 110 #endif
 111
 112 static void clear_lch_regs(int lch)
 113 {
 114         int i;
 115         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
 116
 117         for (i = 0; i < 0x2c; i += 2)
 118                 omap_writew(0, lch_base + i);
 119 }
 120
 121 void omap_set_dma_priority(int dst_port, int priority)
 122 {
 123         unsigned long reg;
 124         u32 l;
 125
 126         switch (dst_port) {
 127         case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 128                 reg = OMAP_TC_OCPT1_PRIOR;
 129                 break;
 130         case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 131                 reg = OMAP_TC_OCPT2_PRIOR;
 132                 break;
 133         case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 134                 reg = OMAP_TC_EMIFF_PRIOR;
 135                 break;
 136         case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 137                 reg = OMAP_TC_EMIFS_PRIOR;
 138                 break;
 139         default:
 140                 BUG();
 141                 return;
 142         }
 143         l = omap_readl(reg);
 144         l &= ~(0xf << 8);
 145         l |= (priority & 0xf) << 8;
 146         omap_writel(l, reg);
 147 }
 148
 149 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 150                                   int frame_count, int sync_mode,
 151                                   int dma_trigger, int src_or_dst_synch)
 152 {
 153         OMAP_DMA_CSDP_REG(lch) &= ~0x03;
 154         OMAP_DMA_CSDP_REG(lch) |= data_type;
 155
 156         if (cpu_class_is_omap1()) {
 157                 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
 158                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 159                         OMAP_DMA_CCR_REG(lch) |= 1 << 5;
 160
 161                 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
 162                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 163                         OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
 164         }
 165
 166         if (cpu_is_omap24xx() && dma_trigger) {
 167                 u32 val = OMAP_DMA_CCR_REG(lch);
 168
 169                 val &= ~(3 << 19);
 170                 if (dma_trigger > 63)
 171                         val |= 1 << 20;
 172                 if (dma_trigger > 31)
 173                         val |= 1 << 19;
 174
 175                 val &= ~(0x1f);
 176                 val |= (dma_trigger & 0x1f);
 177
 178                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 179                         val |= 1 << 5;
 180                 else
 181                         val &= ~(1 << 5);
 182
 183                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 184                         val |= 1 << 18;
 185                 else
 186                         val &= ~(1 << 18);
 187
 188                 if (src_or_dst_synch)
 189                         val |= 1 << 24;         /* source synch */
 190                 else
 191                         val &= ~(1 << 24);      /* dest synch */
 192
 193                 OMAP_DMA_CCR_REG(lch) = val;
 194         }
 195
 196         OMAP_DMA_CEN_REG(lch) = elem_count;
 197         OMAP_DMA_CFN_REG(lch) = frame_count;
 198 }
 199
 200 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 201 {
 202         u16 w;
 203
 204         BUG_ON(omap_dma_in_1510_mode());
 205
 206         if (cpu_is_omap24xx()) {
 207                 REVISIT_24XX();
 208                 return;
 209         }
 210
 211         w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
 212         switch (mode) {
 213         case OMAP_DMA_CONSTANT_FILL:
 214                 w |= 0x01;
 215                 break;
 216         case OMAP_DMA_TRANSPARENT_COPY:
 217                 w |= 0x02;
 218                 break;
 219         case OMAP_DMA_COLOR_DIS:
 220                 break;
 221         default:
 222                 BUG();
 223         }
 224         OMAP1_DMA_CCR2_REG(lch) = w;
 225
 226         w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
 227         /* Default is channel type 2D */
 228         if (mode) {
 229                 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
 230                 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
 231                 w |= 1;         /* Channel type G */
 232         }
 233         OMAP1_DMA_LCH_CTRL_REG(lch) = w;
 234 }
 235
 236 /* Note that src_port is only for omap1 */
 237 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 238                              unsigned long src_start,
 239                              int src_ei, int src_fi)
 240 {
 241         if (cpu_class_is_omap1()) {
 242                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
 243                 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
 244         }
 245
 246         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
 247         OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
 248
 249         if (cpu_class_is_omap1()) {
 250                 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
 251                 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
 252         }
 253
 254         if (cpu_is_omap24xx())
 255                 OMAP2_DMA_CSSA_REG(lch) = src_start;
 256
 257         OMAP_DMA_CSEI_REG(lch) = src_ei;
 258         OMAP_DMA_CSFI_REG(lch) = src_fi;
 259 }
 260
 261 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
 262 {
 263         omap_set_dma_transfer_params(lch, params->data_type,
 264                                      params->elem_count, params->frame_count,
 265                                      params->sync_mode, params->trigger,
 266                                      params->src_or_dst_synch);
 267         omap_set_dma_src_params(lch, params->src_port,
 268                                 params->src_amode, params->src_start,
 269                                 params->src_ei, params->src_fi);
 270
 271         omap_set_dma_dest_params(lch, params->dst_port,
 272                                  params->dst_amode, params->dst_start,
 273                                  params->dst_ei, params->dst_fi);
 274 }
 275
 276 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 277 {
 278         if (cpu_is_omap24xx()) {
 279                 REVISIT_24XX();
 280                 return;
 281         }
 282         OMAP_DMA_CSEI_REG(lch) = eidx;
 283         OMAP_DMA_CSFI_REG(lch) = fidx;
 284 }
 285
 286 void omap_set_dma_src_data_pack(int lch, int enable)
 287 {
 288         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
 289         if (enable)
 290                 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
 291 }
 292
 293 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 294 {
 295         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
 296
 297         switch (burst_mode) {
 298         case OMAP_DMA_DATA_BURST_DIS:
 299                 break;
 300         case OMAP_DMA_DATA_BURST_4:
 301                 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 7);
 302                 break;
 303         case OMAP_DMA_DATA_BURST_8:
 304                 /* not supported by current hardware
 305                  * w |= (0x03 << 7);
 306                  * fall through
 307                  */
 308         default:
 309                 BUG();
 310         }
 311 }
 312
 313 /* Note that dest_port is only for OMAP1 */
 314 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 315                               unsigned long dest_start,
 316                               int dst_ei, int dst_fi)
 317 {
 318         if (cpu_class_is_omap1()) {
 319                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
 320                 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
 321         }
 322
 323         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
 324         OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
 325
 326         if (cpu_class_is_omap1()) {
 327                 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
 328                 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
 329         }
 330
 331         if (cpu_is_omap24xx())
 332                 OMAP2_DMA_CDSA_REG(lch) = dest_start;
 333
 334         OMAP_DMA_CDEI_REG(lch) = dst_ei;
 335         OMAP_DMA_CDFI_REG(lch) = dst_fi;
 336 }
 337
 338 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 339 {
 340         if (cpu_is_omap24xx()) {
 341                 REVISIT_24XX();
 342                 return;
 343         }
 344         OMAP_DMA_CDEI_REG(lch) = eidx;
 345         OMAP_DMA_CDFI_REG(lch) = fidx;
 346 }
 347
 348 void omap_set_dma_dest_data_pack(int lch, int enable)
 349 {
 350         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
 351         if (enable)
 352                 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
 353 }
 354
 355 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 356 {
 357         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
 358
 359         switch (burst_mode) {
 360         case OMAP_DMA_DATA_BURST_DIS:
 361                 break;
 362         case OMAP_DMA_DATA_BURST_4:
 363                 OMAP_DMA_CSDP_REG(lch) |= (0x02 << 14);
 364                 break;
 365         case OMAP_DMA_DATA_BURST_8:
 366                 OMAP_DMA_CSDP_REG(lch) |= (0x03 << 14);
 367                 break;
 368         default:
 369                 printk(KERN_ERR "Invalid DMA burst mode\n");
 370                 BUG();
 371                 return;
 372         }
 373 }
 374
 375 static inline void omap_enable_channel_irq(int lch)
 376 {
 377         u32 status;
 378
 379         /* Read CSR to make sure it's cleared. */
 380         status = OMAP_DMA_CSR_REG(lch);
 381
 382         /* Enable some nice interrupts. */
 383         OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
 384
 385         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 386 }
 387
 388 static void omap_disable_channel_irq(int lch)
 389 {
 390         if (cpu_is_omap24xx())
 391                 OMAP_DMA_CICR_REG(lch) = 0;
 392 }
 393
 394 void omap_enable_dma_irq(int lch, u16 bits)
 395 {
 396         dma_chan[lch].enabled_irqs |= bits;
 397 }
 398
 399 void omap_disable_dma_irq(int lch, u16 bits)
 400 {
 401         dma_chan[lch].enabled_irqs &= ~bits;
 402 }
 403
 404 static inline void enable_lnk(int lch)
 405 {
 406         if (cpu_class_is_omap1())
 407                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
 408
 409         /* Set the ENABLE_LNK bits */
 410         if (dma_chan[lch].next_lch != -1)
 411                 OMAP_DMA_CLNK_CTRL_REG(lch) =
 412                         dma_chan[lch].next_lch | (1 << 15);
 413 }
 414
 415 static inline void disable_lnk(int lch)
 416 {
 417         /* Disable interrupts */
 418         if (cpu_class_is_omap1()) {
 419                 OMAP_DMA_CICR_REG(lch) = 0;
 420                 /* Set the STOP_LNK bit */
 421                 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
 422         }
 423
 424         if (cpu_is_omap24xx()) {
 425                 omap_disable_channel_irq(lch);
 426                 /* Clear the ENABLE_LNK bit */
 427                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
 428         }
 429
 430         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 431 }
 432
 433 static inline void omap2_enable_irq_lch(int lch)
 434 {
 435         u32 val;
 436
 437         if (!cpu_is_omap24xx())
 438                 return;
 439
 440         val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 441         val |= 1 << lch;
 442         omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 443 }
 444
 445 int omap_request_dma(int dev_id, const char *dev_name,
 446                      void (* callback)(int lch, u16 ch_status, void *data),
 447                      void *data, int *dma_ch_out)
 448 {
 449         int ch, free_ch = -1;
 450         unsigned long flags;
 451         struct omap_dma_lch *chan;
 452
 453         spin_lock_irqsave(&dma_chan_lock, flags);
 454         for (ch = 0; ch < dma_chan_count; ch++) {
 455                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 456                         free_ch = ch;
 457                         if (dev_id == 0)
 458                                 break;
 459                 }
 460         }
 461         if (free_ch == -1) {
 462                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 463                 return -EBUSY;
 464         }
 465         chan = dma_chan + free_ch;
 466         chan->dev_id = dev_id;
 467
 468         if (cpu_class_is_omap1())
 469                 clear_lch_regs(free_ch);
 470
 471         if (cpu_is_omap24xx())
 472                 omap_clear_dma(free_ch);
 473
 474         spin_unlock_irqrestore(&dma_chan_lock, flags);
 475
 476         chan->dev_name = dev_name;
 477         chan->callback = callback;
 478         chan->data = data;
 479         chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ |
 480                                 OMAP_DMA_BLOCK_IRQ;
 481
 482         if (cpu_is_omap24xx())
 483                 chan->enabled_irqs |= OMAP2_DMA_TRANS_ERR_IRQ;
 484
 485         if (cpu_is_omap16xx()) {
 486                 /* If the sync device is set, configure it dynamically. */
 487                 if (dev_id != 0) {
 488                         set_gdma_dev(free_ch + 1, dev_id);
 489                         dev_id = free_ch + 1;
 490                 }
 491                 /* Disable the 1510 compatibility mode and set the sync device
 492                  * id. */
 493                 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
 494         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 495                 OMAP_DMA_CCR_REG(free_ch) = dev_id;
 496         }
 497
 498         if (cpu_is_omap24xx()) {
 499                 omap2_enable_irq_lch(free_ch);
 500
 501                 omap_enable_channel_irq(free_ch);
 502                 /* Clear the CSR register and IRQ status register */
 503                 OMAP_DMA_CSR_REG(free_ch) = 0x0;
 504                 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
 505         }
 506
 507         *dma_ch_out = free_ch;
 508
 509         return 0;
 510 }
 511
 512 void omap_free_dma(int lch)
 513 {
 514         unsigned long flags;
 515
 516         spin_lock_irqsave(&dma_chan_lock, flags);
 517         if (dma_chan[lch].dev_id == -1) {
 518                 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
 519                        lch);
 520                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 521                 return;
 522         }
 523         dma_chan[lch].dev_id = -1;
 524         dma_chan[lch].next_lch = -1;
 525         dma_chan[lch].callback = NULL;
 526         spin_unlock_irqrestore(&dma_chan_lock, flags);
 527
 528         if (cpu_class_is_omap1()) {
 529                 /* Disable all DMA interrupts for the channel. */
 530                 OMAP_DMA_CICR_REG(lch) = 0;
 531                 /* Make sure the DMA transfer is stopped. */
 532                 OMAP_DMA_CCR_REG(lch) = 0;
 533         }
 534
 535         if (cpu_is_omap24xx()) {
 536                 u32 val;
 537                 /* Disable interrupts */
 538                 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 539                 val &= ~(1 << lch);
 540                 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 541
 542                 /* Clear the CSR register and IRQ status register */
 543                 OMAP_DMA_CSR_REG(lch) = 0x0;
 544
 545                 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 546                 val |= 1 << lch;
 547                 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
 548
 549                 /* Disable all DMA interrupts for the channel. */
 550                 OMAP_DMA_CICR_REG(lch) = 0;
 551
 552                 /* Make sure the DMA transfer is stopped. */
 553                 OMAP_DMA_CCR_REG(lch) = 0;
 554                 omap_clear_dma(lch);
 555         }
 556 }
 557
 558 /*
 559  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 560  * through omap_start_dma(). Any buffers in flight are discarded.
 561  */
 562 void omap_clear_dma(int lch)
 563 {
 564         unsigned long flags;
 565
 566         local_irq_save(flags);
 567
 568         if (cpu_class_is_omap1()) {
 569                 int status;
 570                 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 571
 572                 /* Clear pending interrupts */
 573                 status = OMAP_DMA_CSR_REG(lch);
 574         }
 575
 576         if (cpu_is_omap24xx()) {
 577                 int i;
 578                 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
 579                 for (i = 0; i < 0x44; i += 4)
 580                         omap_writel(0, lch_base + i);
 581         }
 582
 583         local_irq_restore(flags);
 584 }
 585
 586 void omap_start_dma(int lch)
 587 {
 588         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 589                 int next_lch, cur_lch;
 590                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 591
 592                 dma_chan_link_map[lch] = 1;
 593                 /* Set the link register of the first channel */
 594                 enable_lnk(lch);
 595
 596                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 597                 cur_lch = dma_chan[lch].next_lch;
 598                 do {
 599                         next_lch = dma_chan[cur_lch].next_lch;
 600
 601                         /* The loop case: we've been here already */
 602                         if (dma_chan_link_map[cur_lch])
 603                                 break;
 604                         /* Mark the current channel */
 605                         dma_chan_link_map[cur_lch] = 1;
 606
 607                         enable_lnk(cur_lch);
 608                         omap_enable_channel_irq(cur_lch);
 609
 610                         cur_lch = next_lch;
 611                 } while (next_lch != -1);
 612         } else if (cpu_is_omap24xx()) {
 613                 /* Errata: Need to write lch even if not using chaining */
 614                 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
 615         }
 616
 617         omap_enable_channel_irq(lch);
 618
 619         /* Errata: On ES2.0 BUFFERING disable must be set.
 620          * This will always fail on ES1.0 */
 621         if (cpu_is_omap24xx()) {
 622                 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 623         }
 624
 625         OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 626
 627         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 628 }
 629
 630 void omap_stop_dma(int lch)
 631 {
 632         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 633                 int next_lch, cur_lch = lch;
 634                 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
 635
 636                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 637                 do {
 638                         /* The loop case: we've been here already */
 639                         if (dma_chan_link_map[cur_lch])
 640                                 break;
 641                         /* Mark the current channel */
 642                         dma_chan_link_map[cur_lch] = 1;
 643
 644                         disable_lnk(cur_lch);
 645
 646                         next_lch = dma_chan[cur_lch].next_lch;
 647                         cur_lch = next_lch;
 648                 } while (next_lch != -1);
 649
 650                 return;
 651         }
 652
 653         /* Disable all interrupts on the channel */
 654         if (cpu_class_is_omap1())
 655                 OMAP_DMA_CICR_REG(lch) = 0;
 656
 657         OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 658         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 659 }
 660
 661 /*
 662  * Returns current physical source address for the given DMA channel.
 663  * If the channel is running the caller must disable interrupts prior calling
 664  * this function and process the returned value before re-enabling interrupt to
 665  * prevent races with the interrupt handler. Note that in continuous mode there
 666  * is a chance for CSSA_L register overflow inbetween the two reads resulting
 667  * in incorrect return value.
 668  */
 669 dma_addr_t omap_get_dma_src_pos(int lch)
 670 {
 671         dma_addr_t offset;
 672
 673         if (cpu_class_is_omap1())
 674                 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
 675                                        (OMAP1_DMA_CSSA_U_REG(lch) << 16));
 676
 677         if (cpu_is_omap24xx())
 678                 offset = OMAP_DMA_CSAC_REG(lch);
 679
 680         return offset;
 681 }
 682
 683 /*
 684  * Returns current physical destination address for the given DMA channel.
 685  * If the channel is running the caller must disable interrupts prior calling
 686  * this function and process the returned value before re-enabling interrupt to
 687  * prevent races with the interrupt handler. Note that in continuous mode there
 688  * is a chance for CDSA_L register overflow inbetween the two reads resulting
 689  * in incorrect return value.
 690  */
 691 dma_addr_t omap_get_dma_dst_pos(int lch)
 692 {
 693         dma_addr_t offset;
 694
 695         if (cpu_class_is_omap1())
 696                 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
 697                                        (OMAP1_DMA_CDSA_U_REG(lch) << 16));
 698
 699         if (cpu_is_omap24xx())
 700                 offset = OMAP2_DMA_CDSA_REG(lch);
 701
 702         return offset;
 703 }
 704
 705 /*
 706  * Returns current source transfer counting for the given DMA channel.
 707  * Can be used to monitor the progress of a transfer inside a block.
 708  * It must be called with disabled interrupts.
 709  */
 710 int omap_get_dma_src_addr_counter(int lch)
 711 {
 712         return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
 713 }
 714
 715 int omap_dma_running(void)
 716 {
 717         int lch;
 718
 719         /* Check if LCD DMA is running */
 720         if (cpu_is_omap16xx())
 721                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
 722                         return 1;
 723
 724         for (lch = 0; lch < dma_chan_count; lch++)
 725                 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
 726                         return 1;
 727
 728         return 0;
 729 }
 730
 731 /*
 732  * lch_queue DMA will start right after lch_head one is finished.
 733  * For this DMA link to start, you still need to start (see omap_start_dma)
 734  * the first one. That will fire up the entire queue.
 735  */
 736 void omap_dma_link_lch (int lch_head, int lch_queue)
 737 {
 738         if (omap_dma_in_1510_mode()) {
 739                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 740                 BUG();
 741                 return;
 742         }
 743
 744         if ((dma_chan[lch_head].dev_id == -1) ||
 745             (dma_chan[lch_queue].dev_id == -1)) {
 746                 printk(KERN_ERR "omap_dma: trying to link "
 747                        "non requested channels\n");
 748                 dump_stack();
 749         }
 750
 751         dma_chan[lch_head].next_lch = lch_queue;
 752 }
 753
 754 /*
 755  * Once the DMA queue is stopped, we can destroy it.
 756  */
 757 void omap_dma_unlink_lch (int lch_head, int lch_queue)
 758 {
 759         if (omap_dma_in_1510_mode()) {
 760                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 761                 BUG();
 762                 return;
 763         }
 764
 765         if (dma_chan[lch_head].next_lch != lch_queue ||
 766             dma_chan[lch_head].next_lch == -1) {
 767                 printk(KERN_ERR "omap_dma: trying to unlink "
 768                        "non linked channels\n");
 769                 dump_stack();
 770         }
 771
 772
 773         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 774             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
 775                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
 776                        "before unlinking\n");
 777                 dump_stack();
 778         }
 779
 780         dma_chan[lch_head].next_lch = -1;
 781 }
 782
 783 /*----------------------------------------------------------------------------*/
 784
 785 #ifdef CONFIG_ARCH_OMAP1
 786
 787 static int omap1_dma_handle_ch(int ch)
 788 {
 789         u16 csr;
 790
 791         if (enable_1510_mode && ch >= 6) {
 792                 csr = dma_chan[ch].saved_csr;
 793                 dma_chan[ch].saved_csr = 0;
 794         } else
 795                 csr = OMAP_DMA_CSR_REG(ch);
 796         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
 797                 dma_chan[ch + 6].saved_csr = csr >> 7;
 798                 csr &= 0x7f;
 799         }
 800         if ((csr & 0x3f) == 0)
 801                 return 0;
 802         if (unlikely(dma_chan[ch].dev_id == -1)) {
 803                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
 804                        "%d (CSR %04x)\n", ch, csr);
 805                 return 0;
 806         }
 807         if (unlikely(csr & OMAP_DMA_TOUT_IRQ))
 808                 printk(KERN_WARNING "DMA timeout with device %d\n",
 809                        dma_chan[ch].dev_id);
 810         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
 811                 printk(KERN_WARNING "DMA synchronization event drop occurred "
 812                        "with device %d\n", dma_chan[ch].dev_id);
 813         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
 814                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
 815         if (likely(dma_chan[ch].callback != NULL))
 816                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
 817         return 1;
 818 }
 819
 820 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id,
 821                                          struct pt_regs *regs)
 822 {
 823         int ch = ((int) dev_id) - 1;
 824         int handled = 0;
 825
 826         for (;;) {
 827                 int handled_now = 0;
 828
 829                 handled_now += omap1_dma_handle_ch(ch);
 830                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
 831                         handled_now += omap1_dma_handle_ch(ch + 6);
 832                 if (!handled_now)
 833                         break;
 834                 handled += handled_now;
 835         }
 836
 837         return handled ? IRQ_HANDLED : IRQ_NONE;
 838 }
 839
 840 #else
 841 #define omap1_dma_irq_handler   NULL
 842 #endif
 843
 844 #ifdef CONFIG_ARCH_OMAP2
 845
 846 static int omap2_dma_handle_ch(int ch)
 847 {
 848         u32 status = OMAP_DMA_CSR_REG(ch);
 849         u32 val;
 850
 851         if (!status)
 852                 return 0;
 853         if (unlikely(dma_chan[ch].dev_id == -1))
 854                 return 0;
 855         /* REVISIT: According to 24xx TRM, there's no TOUT_IE */
 856         if (unlikely(status & OMAP_DMA_TOUT_IRQ))
 857                 printk(KERN_INFO "DMA timeout with device %d\n",
 858                        dma_chan[ch].dev_id);
 859         if (unlikely(status & OMAP_DMA_DROP_IRQ))
 860                 printk(KERN_INFO
 861                        "DMA synchronization event drop occurred with device "
 862                        "%d\n", dma_chan[ch].dev_id);
 863
 864         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
 865                 printk(KERN_INFO "DMA transaction error with device %d\n",
 866                        dma_chan[ch].dev_id);
 867
 868         OMAP_DMA_CSR_REG(ch) = 0x20;
 869
 870         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 871         /* ch in this function is from 0-31 while in register it is 1-32 */
 872         val = 1 << (ch);
 873         omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
 874
 875         if (likely(dma_chan[ch].callback != NULL))
 876                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 877
 878         return 0;
 879 }
 880
 881 /* STATUS register count is from 1-32 while our is 0-31 */
 882 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id,
 883                                          struct pt_regs *regs)
 884 {
 885         u32 val;
 886         int i;
 887
 888         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
 889
 890         for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
 891                 int active = val & (1 << (i - 1));
 892                 if (active)
 893                         omap2_dma_handle_ch(i - 1);
 894         }
 895
 896         return IRQ_HANDLED;
 897 }
 898
 899 static struct irqaction omap24xx_dma_irq = {
 900         .name = "DMA",
 901         .handler = omap2_dma_irq_handler,
 902         .flags = SA_INTERRUPT
 903 };
 904
 905 #else
 906 static struct irqaction omap24xx_dma_irq;
 907 #endif
 908
 909 /*----------------------------------------------------------------------------*/
 910
 911 static struct lcd_dma_info {
 912         spinlock_t lock;
 913         int reserved;
 914         void (* callback)(u16 status, void *data);
 915         void *cb_data;
 916
 917         int active;
 918         unsigned long addr, size;
 919         int rotate, data_type, xres, yres;
 920         int vxres;
 921         int mirror;
 922         int xscale, yscale;
 923         int ext_ctrl;
 924         int src_port;
 925         int single_transfer;
 926 } lcd_dma;
 927
 928 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 929                          int data_type)
 930 {
 931         lcd_dma.addr = addr;
 932         lcd_dma.data_type = data_type;
 933         lcd_dma.xres = fb_xres;
 934         lcd_dma.yres = fb_yres;
 935 }
 936
 937 void omap_set_lcd_dma_src_port(int port)
 938 {
 939         lcd_dma.src_port = port;
 940 }
 941
 942 void omap_set_lcd_dma_ext_controller(int external)
 943 {
 944         lcd_dma.ext_ctrl = external;
 945 }
 946
 947 void omap_set_lcd_dma_single_transfer(int single)
 948 {
 949         lcd_dma.single_transfer = single;
 950 }
 951
 952
 953 void omap_set_lcd_dma_b1_rotation(int rotate)
 954 {
 955         if (omap_dma_in_1510_mode()) {
 956                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
 957                 BUG();
 958                 return;
 959         }
 960         lcd_dma.rotate = rotate;
 961 }
 962
 963 void omap_set_lcd_dma_b1_mirror(int mirror)
 964 {
 965         if (omap_dma_in_1510_mode()) {
 966                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
 967                 BUG();
 968         }
 969         lcd_dma.mirror = mirror;
 970 }
 971
 972 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
 973 {
 974         if (omap_dma_in_1510_mode()) {
 975                 printk(KERN_ERR "DMA virtual resulotion is not supported "
 976                                 "in 1510 mode\n");
 977                 BUG();
 978         }
 979         lcd_dma.vxres = vxres;
 980 }
 981
 982 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
 983 {
 984         if (omap_dma_in_1510_mode()) {
 985                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
 986                 BUG();
 987         }
 988         lcd_dma.xscale = xscale;
 989         lcd_dma.yscale = yscale;
 990 }
 991
 992 static void set_b1_regs(void)
 993 {
 994         unsigned long top, bottom;
 995         int es;
 996         u16 w;
 997         unsigned long en, fn;
 998         long ei, fi;
 999         unsigned long vxres;
1000         unsigned int xscale, yscale;
1001
1002         switch (lcd_dma.data_type) {
1003         case OMAP_DMA_DATA_TYPE_S8:
1004                 es = 1;
1005                 break;
1006         case OMAP_DMA_DATA_TYPE_S16:
1007                 es = 2;
1008                 break;
1009         case OMAP_DMA_DATA_TYPE_S32:
1010                 es = 4;
1011                 break;
1012         default:
1013                 BUG();
1014                 return;
1015         }
1016
1017         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1018         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1019         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1020         BUG_ON(vxres < lcd_dma.xres);
1021 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1022 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1023         switch (lcd_dma.rotate) {
1024         case 0:
1025                 if (!lcd_dma.mirror) {
1026                         top = PIXADDR(0, 0);
1027                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1028                         /* 1510 DMA requires the bottom address to be 2 more
1029                          * than the actual last memory access location. */
1030                         if (omap_dma_in_1510_mode() &&
1031                             lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1032                                 bottom += 2;
1033                         ei = PIXSTEP(0, 0, 1, 0);
1034                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1035                 } else {
1036                         top = PIXADDR(lcd_dma.xres - 1, 0);
1037                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1038                         ei = PIXSTEP(1, 0, 0, 0);
1039                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1040                 }
1041                 en = lcd_dma.xres;
1042                 fn = lcd_dma.yres;
1043                 break;
1044         case 90:
1045                 if (!lcd_dma.mirror) {
1046                         top = PIXADDR(0, lcd_dma.yres - 1);
1047                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1048                         ei = PIXSTEP(0, 1, 0, 0);
1049                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1050                 } else {
1051                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1052                         bottom = PIXADDR(0, 0);
1053                         ei = PIXSTEP(0, 1, 0, 0);
1054                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1055                 }
1056                 en = lcd_dma.yres;
1057                 fn = lcd_dma.xres;
1058                 break;
1059         case 180:
1060                 if (!lcd_dma.mirror) {
1061                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1062                         bottom = PIXADDR(0, 0);
1063                         ei = PIXSTEP(1, 0, 0, 0);
1064                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1065                 } else {
1066                         top = PIXADDR(0, lcd_dma.yres - 1);
1067                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1068                         ei = PIXSTEP(0, 0, 1, 0);
1069                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1070                 }
1071                 en = lcd_dma.xres;
1072                 fn = lcd_dma.yres;
1073                 break;
1074         case 270:
1075                 if (!lcd_dma.mirror) {
1076                         top = PIXADDR(lcd_dma.xres - 1, 0);
1077                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1078                         ei = PIXSTEP(0, 0, 0, 1);
1079                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1080                 } else {
1081                         top = PIXADDR(0, 0);
1082                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1083                         ei = PIXSTEP(0, 0, 0, 1);
1084                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1085                 }
1086                 en = lcd_dma.yres;
1087                 fn = lcd_dma.xres;
1088                 break;
1089         default:
1090                 BUG();
1091                 return; /* Supress warning about uninitialized vars */
1092         }
1093
1094         if (omap_dma_in_1510_mode()) {
1095                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1096                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1097                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1098                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1099
1100                 return;
1101         }
1102
1103         /* 1610 regs */
1104         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1105         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1106         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1107         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1108
1109         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1110         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1111
1112         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1113         w &= ~0x03;
1114         w |= lcd_dma.data_type;
1115         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1116
1117         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1118         /* Always set the source port as SDRAM for now*/
1119         w &= ~(0x03 << 6);
1120         if (lcd_dma.callback != NULL)
1121                 w |= 1 << 1;            /* Block interrupt enable */
1122         else
1123                 w &= ~(1 << 1);
1124         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1125
1126         if (!(lcd_dma.rotate || lcd_dma.mirror ||
1127               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1128                 return;
1129
1130         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1131         /* Set the double-indexed addressing mode */
1132         w |= (0x03 << 12);
1133         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1134
1135         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1136         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1137         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1138 }
1139
1140 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id,
1141                                        struct pt_regs *regs)
1142 {
1143         u16 w;
1144
1145         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1146         if (unlikely(!(w & (1 << 3)))) {
1147                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1148                 return IRQ_NONE;
1149         }
1150         /* Ack the IRQ */
1151         w |= (1 << 3);
1152         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1153         lcd_dma.active = 0;
1154         if (lcd_dma.callback != NULL)
1155                 lcd_dma.callback(w, lcd_dma.cb_data);
1156
1157         return IRQ_HANDLED;
1158 }
1159
1160 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
1161                          void *data)
1162 {
1163         spin_lock_irq(&lcd_dma.lock);
1164         if (lcd_dma.reserved) {
1165                 spin_unlock_irq(&lcd_dma.lock);
1166                 printk(KERN_ERR "LCD DMA channel already reserved\n");
1167                 BUG();
1168                 return -EBUSY;
1169         }
1170         lcd_dma.reserved = 1;
1171         spin_unlock_irq(&lcd_dma.lock);
1172         lcd_dma.callback = callback;
1173         lcd_dma.cb_data = data;
1174         lcd_dma.active = 0;
1175         lcd_dma.single_transfer = 0;
1176         lcd_dma.rotate = 0;
1177         lcd_dma.vxres = 0;
1178         lcd_dma.mirror = 0;
1179         lcd_dma.xscale = 0;
1180         lcd_dma.yscale = 0;
1181         lcd_dma.ext_ctrl = 0;
1182         lcd_dma.src_port = 0;
1183
1184         return 0;
1185 }
1186
1187 void omap_free_lcd_dma(void)
1188 {
1189         spin_lock(&lcd_dma.lock);
1190         if (!lcd_dma.reserved) {
1191                 spin_unlock(&lcd_dma.lock);
1192                 printk(KERN_ERR "LCD DMA is not reserved\n");
1193                 BUG();
1194                 return;
1195         }
1196         if (!enable_1510_mode)
1197                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1198                             OMAP1610_DMA_LCD_CCR);
1199         lcd_dma.reserved = 0;
1200         spin_unlock(&lcd_dma.lock);
1201 }
1202
1203 void omap_enable_lcd_dma(void)
1204 {
1205         u16 w;
1206
1207         /* Set the Enable bit only if an external controller is
1208          * connected. Otherwise the OMAP internal controller will
1209          * start the transfer when it gets enabled.
1210          */
1211         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1212                 return;
1213
1214         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1215         w |= 1 << 8;
1216         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1217
1218         lcd_dma.active = 1;
1219
1220         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1221         w |= 1 << 7;
1222         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1223 }
1224
1225 void omap_setup_lcd_dma(void)
1226 {
1227         BUG_ON(lcd_dma.active);
1228         if (!enable_1510_mode) {
1229                 /* Set some reasonable defaults */
1230                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
1231                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
1232                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
1233         }
1234         set_b1_regs();
1235         if (!enable_1510_mode) {
1236                 u16 w;
1237
1238                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1239                 /* If DMA was already active set the end_prog bit to have
1240                  * the programmed register set loaded into the active
1241                  * register set.
1242                  */
1243                 w |= 1 << 11;           /* End_prog */
1244                 if (!lcd_dma.single_transfer)
1245                         w |= (3 << 8);  /* Auto_init, repeat */
1246                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1247         }
1248 }
1249
1250 void omap_stop_lcd_dma(void)
1251 {
1252         u16 w;
1253
1254         lcd_dma.active = 0;
1255         if (enable_1510_mode || !lcd_dma.ext_ctrl)
1256                 return;
1257
1258         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1259         w &= ~(1 << 7);
1260         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1261
1262         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1263         w &= ~(1 << 8);
1264         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1265 }
1266
1267 int omap_lcd_dma_ext_running(void)
1268 {
1269         return lcd_dma.ext_ctrl && lcd_dma.active;
1270 }
1271
1272 /*----------------------------------------------------------------------------*/
1273
1274 static int __init omap_init_dma(void)
1275 {
1276         int ch, r;
1277
1278         if (cpu_is_omap15xx()) {
1279                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1280                 dma_chan_count = 9;
1281                 enable_1510_mode = 1;
1282         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1283                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1284                        omap_readw(OMAP_DMA_HW_ID));
1285                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1286                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1287                        omap_readw(OMAP_DMA_CAPS_0_L),
1288                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1289                        omap_readw(OMAP_DMA_CAPS_1_L),
1290                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1291                        omap_readw(OMAP_DMA_CAPS_4));
1292                 if (!enable_1510_mode) {
1293                         u16 w;
1294
1295                         /* Disable OMAP 3.0/3.1 compatibility mode. */
1296                         w = omap_readw(OMAP_DMA_GSCR);
1297                         w |= 1 << 3;
1298                         omap_writew(w, OMAP_DMA_GSCR);
1299                         dma_chan_count = 16;
1300                 } else
1301                         dma_chan_count = 9;
1302         } else if (cpu_is_omap24xx()) {
1303                 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1304                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1305                        revision >> 4, revision & 0xf);
1306                 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1307         } else {
1308                 dma_chan_count = 0;
1309                 return 0;
1310         }
1311
1312         memset(&lcd_dma, 0, sizeof(lcd_dma));
1313         spin_lock_init(&lcd_dma.lock);
1314         spin_lock_init(&dma_chan_lock);
1315         memset(&dma_chan, 0, sizeof(dma_chan));
1316
1317         for (ch = 0; ch < dma_chan_count; ch++) {
1318                 omap_clear_dma(ch);
1319                 dma_chan[ch].dev_id = -1;
1320                 dma_chan[ch].next_lch = -1;
1321
1322                 if (ch >= 6 && enable_1510_mode)
1323                         continue;
1324
1325                 if (cpu_class_is_omap1()) {
1326                         /* request_irq() doesn't like dev_id (ie. ch) being
1327                          * zero, so we have to kludge around this. */
1328                         r = request_irq(omap1_dma_irq[ch],
1329                                         omap1_dma_irq_handler, 0, "DMA",
1330                                         (void *) (ch + 1));
1331                         if (r != 0) {
1332                                 int i;
1333
1334                                 printk(KERN_ERR "unable to request IRQ %d "
1335                                        "for DMA (error %d)\n",
1336                                        omap1_dma_irq[ch], r);
1337                                 for (i = 0; i < ch; i++)
1338                                         free_irq(omap1_dma_irq[i],
1339                                                  (void *) (i + 1));
1340                                 return r;
1341                         }
1342                 }
1343         }
1344
1345         if (cpu_is_omap24xx())
1346                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1347
1348         /* FIXME: Update LCD DMA to work on 24xx */
1349         if (cpu_class_is_omap1()) {
1350                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1351                                 "LCD DMA", NULL);
1352                 if (r != 0) {
1353                         int i;
1354
1355                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
1356                                "(error %d)\n", r);
1357                         for (i = 0; i < dma_chan_count; i++)
1358                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1359                         return r;
1360                 }
1361         }
1362
1363         return 0;
1364 }
1365
1366 arch_initcall(omap_init_dma);
1367
1368 EXPORT_SYMBOL(omap_get_dma_src_pos);
1369 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1370 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1371 EXPORT_SYMBOL(omap_clear_dma);
1372 EXPORT_SYMBOL(omap_set_dma_priority);
1373 EXPORT_SYMBOL(omap_request_dma);
1374 EXPORT_SYMBOL(omap_free_dma);
1375 EXPORT_SYMBOL(omap_start_dma);
1376 EXPORT_SYMBOL(omap_stop_dma);
1377 EXPORT_SYMBOL(omap_enable_dma_irq);
1378 EXPORT_SYMBOL(omap_disable_dma_irq);
1379
1380 EXPORT_SYMBOL(omap_set_dma_transfer_params);
1381 EXPORT_SYMBOL(omap_set_dma_color_mode);
1382
1383 EXPORT_SYMBOL(omap_set_dma_src_params);
1384 EXPORT_SYMBOL(omap_set_dma_src_index);
1385 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
1386 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
1387
1388 EXPORT_SYMBOL(omap_set_dma_dest_params);
1389 EXPORT_SYMBOL(omap_set_dma_dest_index);
1390 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1391 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1392
1393 EXPORT_SYMBOL(omap_set_dma_params);
1394
1395 EXPORT_SYMBOL(omap_dma_link_lch);
1396 EXPORT_SYMBOL(omap_dma_unlink_lch);
1397
1398 EXPORT_SYMBOL(omap_request_lcd_dma);
1399 EXPORT_SYMBOL(omap_free_lcd_dma);
1400 EXPORT_SYMBOL(omap_enable_lcd_dma);
1401 EXPORT_SYMBOL(omap_setup_lcd_dma);
1402 EXPORT_SYMBOL(omap_stop_lcd_dma);
1403 EXPORT_SYMBOL(omap_lcd_dma_ext_running);
1404 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1405 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1406 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1407 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1408 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1409 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1410 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1411