SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/plat-omap/dma.c

   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Support functions for the OMAP internal DMA channels.
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License version 2 as
  20  * published by the Free Software Foundation.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/sched.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/errno.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/irq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/system.h>
  34 #include <mach/hardware.h>
  35 #include <plat/dma.h>
  36
  37 #include <plat/tc.h>
  38
  39 #undef DEBUG
  40
  41 #ifndef CONFIG_ARCH_OMAP1
  42 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  43         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  44 };
  45
  46 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  47 #endif
  48
  49 #define OMAP_DMA_ACTIVE                 0x01
  50 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  51
  52 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  53
  54 static int enable_1510_mode;
  55
  56 static struct omap_dma_global_context_registers {
  57         u32 dma_irqenable_l0;
  58         u32 dma_ocp_sysconfig;
  59         u32 dma_gcr;
  60 } omap_dma_global_context;
  61
  62 struct omap_dma_lch {
  63         int next_lch;
  64         int dev_id;
  65         u16 saved_csr;
  66         u16 enabled_irqs;
  67         const char *dev_name;
  68         void (*callback)(int lch, u16 ch_status, void *data);
  69         void *data;
  70
  71 #ifndef CONFIG_ARCH_OMAP1
  72         /* required for Dynamic chaining */
  73         int prev_linked_ch;
  74         int next_linked_ch;
  75         int state;
  76         int chain_id;
  77
  78         int status;
  79 #endif
  80         long flags;
  81 };
  82
  83 struct dma_link_info {
  84         int *linked_dmach_q;
  85         int no_of_lchs_linked;
  86
  87         int q_count;
  88         int q_tail;
  89         int q_head;
  90
  91         int chain_state;
  92         int chain_mode;
  93
  94 };
  95
  96 static struct dma_link_info *dma_linked_lch;
  97
  98 #ifndef CONFIG_ARCH_OMAP1
  99
 100 /* Chain handling macros */
 101 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
 102         do {                                                            \
 103                 dma_linked_lch[chain_id].q_head =                       \
 104                 dma_linked_lch[chain_id].q_tail =                       \
 105                 dma_linked_lch[chain_id].q_count = 0;                   \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 108                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 109                 dma_linked_lch[chain_id].q_count)
 110 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 111         do {                                                            \
 112                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 113                 dma_linked_lch[chain_id].q_count)                       \
 114         } while (0)
 115 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 116                 (0 == dma_linked_lch[chain_id].q_count)
 117 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 118         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 119 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 120         do {                                                            \
 121                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 122                 dma_linked_lch[chain_id].q_count--;                     \
 123         } while (0)
 124
 125 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 126         do {                                                            \
 127                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 128                 dma_linked_lch[chain_id].q_count++; \
 129         } while (0)
 130 #endif
 131
 132 static int dma_lch_count;
 133 static int dma_chan_count;
 134 static int omap_dma_reserve_channels;
 135
 136 static spinlock_t dma_chan_lock;
 137 static struct omap_dma_lch *dma_chan;
 138 static void __iomem *omap_dma_base;
 139
 140 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 141         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 142         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 143         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 144         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 145         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 146 };
 147
 148 static inline void disable_lnk(int lch);
 149 static void omap_disable_channel_irq(int lch);
 150 static inline void omap_enable_channel_irq(int lch);
 151
 152 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 153                                                 __func__);
 154
 155 #define dma_read(reg)                                                   \
 156 ({                                                                      \
 157         u32 __val;                                                      \
 158         if (cpu_class_is_omap1())                                       \
 159                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 160         else                                                            \
 161                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 162         __val;                                                          \
 163 })
 164
 165 #define dma_write(val, reg)                                             \
 166 ({                                                                      \
 167         if (cpu_class_is_omap1())                                       \
 168                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 169         else                                                            \
 170                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 171 })
 172
 173 #ifdef CONFIG_ARCH_OMAP15XX
 174 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 175 int omap_dma_in_1510_mode(void)
 176 {
 177         return enable_1510_mode;
 178 }
 179 #else
 180 #define omap_dma_in_1510_mode()         0
 181 #endif
 182
 183 #ifdef CONFIG_ARCH_OMAP1
 184 static inline int get_gdma_dev(int req)
 185 {
 186         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 187         int shift = ((req - 1) % 5) * 6;
 188
 189         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 190 }
 191
 192 static inline void set_gdma_dev(int req, int dev)
 193 {
 194         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 195         int shift = ((req - 1) % 5) * 6;
 196         u32 l;
 197
 198         l = omap_readl(reg);
 199         l &= ~(0x3f << shift);
 200         l |= (dev - 1) << shift;
 201         omap_writel(l, reg);
 202 }
 203 #else
 204 #define set_gdma_dev(req, dev)  do {} while (0)
 205 #endif
 206
 207 /* Omap1 only */
 208 static void clear_lch_regs(int lch)
 209 {
 210         int i;
 211         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 212
 213         for (i = 0; i < 0x2c; i += 2)
 214                 __raw_writew(0, lch_base + i);
 215 }
 216
 217 void omap_set_dma_priority(int lch, int dst_port, int priority)
 218 {
 219         unsigned long reg;
 220         u32 l;
 221
 222         if (cpu_class_is_omap1()) {
 223                 switch (dst_port) {
 224                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 225                         reg = OMAP_TC_OCPT1_PRIOR;
 226                         break;
 227                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 228                         reg = OMAP_TC_OCPT2_PRIOR;
 229                         break;
 230                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 231                         reg = OMAP_TC_EMIFF_PRIOR;
 232                         break;
 233                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 234                         reg = OMAP_TC_EMIFS_PRIOR;
 235                         break;
 236                 default:
 237                         BUG();
 238                         return;
 239                 }
 240                 l = omap_readl(reg);
 241                 l &= ~(0xf << 8);
 242                 l |= (priority & 0xf) << 8;
 243                 omap_writel(l, reg);
 244         }
 245
 246         if (cpu_class_is_omap2()) {
 247                 u32 ccr;
 248
 249                 ccr = dma_read(CCR(lch));
 250                 if (priority)
 251                         ccr |= (1 << 6);
 252                 else
 253                         ccr &= ~(1 << 6);
 254                 dma_write(ccr, CCR(lch));
 255         }
 256 }
 257 EXPORT_SYMBOL(omap_set_dma_priority);
 258
 259 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 260                                   int frame_count, int sync_mode,
 261                                   int dma_trigger, int src_or_dst_synch)
 262 {
 263         u32 l;
 264
 265         l = dma_read(CSDP(lch));
 266         l &= ~0x03;
 267         l |= data_type;
 268         dma_write(l, CSDP(lch));
 269
 270         if (cpu_class_is_omap1()) {
 271                 u16 ccr;
 272
 273                 ccr = dma_read(CCR(lch));
 274                 ccr &= ~(1 << 5);
 275                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 276                         ccr |= 1 << 5;
 277                 dma_write(ccr, CCR(lch));
 278
 279                 ccr = dma_read(CCR2(lch));
 280                 ccr &= ~(1 << 2);
 281                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 282                         ccr |= 1 << 2;
 283                 dma_write(ccr, CCR2(lch));
 284         }
 285
 286         if (cpu_class_is_omap2() && dma_trigger) {
 287                 u32 val;
 288
 289                 val = dma_read(CCR(lch));
 290
 291                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 292                 val &= ~((3 << 19) | 0x1f);
 293                 val |= (dma_trigger & ~0x1f) << 14;
 294                 val |= dma_trigger & 0x1f;
 295
 296                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 297                         val |= 1 << 5;
 298                 else
 299                         val &= ~(1 << 5);
 300
 301                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 302                         val |= 1 << 18;
 303                 else
 304                         val &= ~(1 << 18);
 305
 306                 if (src_or_dst_synch)
 307                         val |= 1 << 24;         /* source synch */
 308                 else
 309                         val &= ~(1 << 24);      /* dest synch */
 310
 311                 dma_write(val, CCR(lch));
 312         }
 313
 314         dma_write(elem_count, CEN(lch));
 315         dma_write(frame_count, CFN(lch));
 316 }
 317 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 318
 319 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 320 {
 321         BUG_ON(omap_dma_in_1510_mode());
 322
 323         if (cpu_class_is_omap1()) {
 324                 u16 w;
 325
 326                 w = dma_read(CCR2(lch));
 327                 w &= ~0x03;
 328
 329                 switch (mode) {
 330                 case OMAP_DMA_CONSTANT_FILL:
 331                         w |= 0x01;
 332                         break;
 333                 case OMAP_DMA_TRANSPARENT_COPY:
 334                         w |= 0x02;
 335                         break;
 336                 case OMAP_DMA_COLOR_DIS:
 337                         break;
 338                 default:
 339                         BUG();
 340                 }
 341                 dma_write(w, CCR2(lch));
 342
 343                 w = dma_read(LCH_CTRL(lch));
 344                 w &= ~0x0f;
 345                 /* Default is channel type 2D */
 346                 if (mode) {
 347                         dma_write((u16)color, COLOR_L(lch));
 348                         dma_write((u16)(color >> 16), COLOR_U(lch));
 349                         w |= 1;         /* Channel type G */
 350                 }
 351                 dma_write(w, LCH_CTRL(lch));
 352         }
 353
 354         if (cpu_class_is_omap2()) {
 355                 u32 val;
 356
 357                 val = dma_read(CCR(lch));
 358                 val &= ~((1 << 17) | (1 << 16));
 359
 360                 switch (mode) {
 361                 case OMAP_DMA_CONSTANT_FILL:
 362                         val |= 1 << 16;
 363                         break;
 364                 case OMAP_DMA_TRANSPARENT_COPY:
 365                         val |= 1 << 17;
 366                         break;
 367                 case OMAP_DMA_COLOR_DIS:
 368                         break;
 369                 default:
 370                         BUG();
 371                 }
 372                 dma_write(val, CCR(lch));
 373
 374                 color &= 0xffffff;
 375                 dma_write(color, COLOR(lch));
 376         }
 377 }
 378 EXPORT_SYMBOL(omap_set_dma_color_mode);
 379
 380 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 381 {
 382         if (cpu_class_is_omap2()) {
 383                 u32 csdp;
 384
 385                 csdp = dma_read(CSDP(lch));
 386                 csdp &= ~(0x3 << 16);
 387                 csdp |= (mode << 16);
 388                 dma_write(csdp, CSDP(lch));
 389         }
 390 }
 391 EXPORT_SYMBOL(omap_set_dma_write_mode);
 392
 393 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 394 {
 395         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 396                 u32 l;
 397
 398                 l = dma_read(LCH_CTRL(lch));
 399                 l &= ~0x7;
 400                 l |= mode;
 401                 dma_write(l, LCH_CTRL(lch));
 402         }
 403 }
 404 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 405
 406 /* Note that src_port is only for omap1 */
 407 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 408                              unsigned long src_start,
 409                              int src_ei, int src_fi)
 410 {
 411         u32 l;
 412
 413         if (cpu_class_is_omap1()) {
 414                 u16 w;
 415
 416                 w = dma_read(CSDP(lch));
 417                 w &= ~(0x1f << 2);
 418                 w |= src_port << 2;
 419                 dma_write(w, CSDP(lch));
 420         }
 421
 422         l = dma_read(CCR(lch));
 423         l &= ~(0x03 << 12);
 424         l |= src_amode << 12;
 425         dma_write(l, CCR(lch));
 426
 427         if (cpu_class_is_omap1()) {
 428                 dma_write(src_start >> 16, CSSA_U(lch));
 429                 dma_write((u16)src_start, CSSA_L(lch));
 430         }
 431
 432         if (cpu_class_is_omap2())
 433                 dma_write(src_start, CSSA(lch));
 434
 435         dma_write(src_ei, CSEI(lch));
 436         dma_write(src_fi, CSFI(lch));
 437 }
 438 EXPORT_SYMBOL(omap_set_dma_src_params);
 439
 440 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 441 {
 442         omap_set_dma_transfer_params(lch, params->data_type,
 443                                      params->elem_count, params->frame_count,
 444                                      params->sync_mode, params->trigger,
 445                                      params->src_or_dst_synch);
 446         omap_set_dma_src_params(lch, params->src_port,
 447                                 params->src_amode, params->src_start,
 448                                 params->src_ei, params->src_fi);
 449
 450         omap_set_dma_dest_params(lch, params->dst_port,
 451                                  params->dst_amode, params->dst_start,
 452                                  params->dst_ei, params->dst_fi);
 453         if (params->read_prio || params->write_prio)
 454                 omap_dma_set_prio_lch(lch, params->read_prio,
 455                                       params->write_prio);
 456 }
 457 EXPORT_SYMBOL(omap_set_dma_params);
 458
 459 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 460 {
 461         if (cpu_class_is_omap2())
 462                 return;
 463
 464         dma_write(eidx, CSEI(lch));
 465         dma_write(fidx, CSFI(lch));
 466 }
 467 EXPORT_SYMBOL(omap_set_dma_src_index);
 468
 469 void omap_set_dma_src_data_pack(int lch, int enable)
 470 {
 471         u32 l;
 472
 473         l = dma_read(CSDP(lch));
 474         l &= ~(1 << 6);
 475         if (enable)
 476                 l |= (1 << 6);
 477         dma_write(l, CSDP(lch));
 478 }
 479 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 480
 481 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 482 {
 483         unsigned int burst = 0;
 484         u32 l;
 485
 486         l = dma_read(CSDP(lch));
 487         l &= ~(0x03 << 7);
 488
 489         switch (burst_mode) {
 490         case OMAP_DMA_DATA_BURST_DIS:
 491                 break;
 492         case OMAP_DMA_DATA_BURST_4:
 493                 if (cpu_class_is_omap2())
 494                         burst = 0x1;
 495                 else
 496                         burst = 0x2;
 497                 break;
 498         case OMAP_DMA_DATA_BURST_8:
 499                 if (cpu_class_is_omap2()) {
 500                         burst = 0x2;
 501                         break;
 502                 }
 503                 /* not supported by current hardware on OMAP1
 504                  * w |= (0x03 << 7);
 505                  * fall through
 506                  */
 507         case OMAP_DMA_DATA_BURST_16:
 508                 if (cpu_class_is_omap2()) {
 509                         burst = 0x3;
 510                         break;
 511                 }
 512                 /* OMAP1 don't support burst 16
 513                  * fall through
 514                  */
 515         default:
 516                 BUG();
 517         }
 518
 519         l |= (burst << 7);
 520         dma_write(l, CSDP(lch));
 521 }
 522 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 523
 524 /* Note that dest_port is only for OMAP1 */
 525 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 526                               unsigned long dest_start,
 527                               int dst_ei, int dst_fi)
 528 {
 529         u32 l;
 530
 531         if (cpu_class_is_omap1()) {
 532                 l = dma_read(CSDP(lch));
 533                 l &= ~(0x1f << 9);
 534                 l |= dest_port << 9;
 535                 dma_write(l, CSDP(lch));
 536         }
 537
 538         l = dma_read(CCR(lch));
 539         l &= ~(0x03 << 14);
 540         l |= dest_amode << 14;
 541         dma_write(l, CCR(lch));
 542
 543         if (cpu_class_is_omap1()) {
 544                 dma_write(dest_start >> 16, CDSA_U(lch));
 545                 dma_write(dest_start, CDSA_L(lch));
 546         }
 547
 548         if (cpu_class_is_omap2())
 549                 dma_write(dest_start, CDSA(lch));
 550
 551         dma_write(dst_ei, CDEI(lch));
 552         dma_write(dst_fi, CDFI(lch));
 553 }
 554 EXPORT_SYMBOL(omap_set_dma_dest_params);
 555
 556 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 557 {
 558         if (cpu_class_is_omap2())
 559                 return;
 560
 561         dma_write(eidx, CDEI(lch));
 562         dma_write(fidx, CDFI(lch));
 563 }
 564 EXPORT_SYMBOL(omap_set_dma_dest_index);
 565
 566 void omap_set_dma_dest_data_pack(int lch, int enable)
 567 {
 568         u32 l;
 569
 570         l = dma_read(CSDP(lch));
 571         l &= ~(1 << 13);
 572         if (enable)
 573                 l |= 1 << 13;
 574         dma_write(l, CSDP(lch));
 575 }
 576 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 577
 578 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 579 {
 580         unsigned int burst = 0;
 581         u32 l;
 582
 583         l = dma_read(CSDP(lch));
 584         l &= ~(0x03 << 14);
 585
 586         switch (burst_mode) {
 587         case OMAP_DMA_DATA_BURST_DIS:
 588                 break;
 589         case OMAP_DMA_DATA_BURST_4:
 590                 if (cpu_class_is_omap2())
 591                         burst = 0x1;
 592                 else
 593                         burst = 0x2;
 594                 break;
 595         case OMAP_DMA_DATA_BURST_8:
 596                 if (cpu_class_is_omap2())
 597                         burst = 0x2;
 598                 else
 599                         burst = 0x3;
 600                 break;
 601         case OMAP_DMA_DATA_BURST_16:
 602                 if (cpu_class_is_omap2()) {
 603                         burst = 0x3;
 604                         break;
 605                 }
 606                 /* OMAP1 don't support burst 16
 607                  * fall through
 608                  */
 609         default:
 610                 printk(KERN_ERR "Invalid DMA burst mode\n");
 611                 BUG();
 612                 return;
 613         }
 614         l |= (burst << 14);
 615         dma_write(l, CSDP(lch));
 616 }
 617 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 618
 619 static inline void omap_enable_channel_irq(int lch)
 620 {
 621         u32 status;
 622
 623         /* Clear CSR */
 624         if (cpu_class_is_omap1())
 625                 status = dma_read(CSR(lch));
 626         else if (cpu_class_is_omap2())
 627                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 628
 629         /* Enable some nice interrupts. */
 630         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 631 }
 632
 633 static void omap_disable_channel_irq(int lch)
 634 {
 635         if (cpu_class_is_omap2())
 636                 dma_write(0, CICR(lch));
 637 }
 638
 639 void omap_enable_dma_irq(int lch, u16 bits)
 640 {
 641         dma_chan[lch].enabled_irqs |= bits;
 642 }
 643 EXPORT_SYMBOL(omap_enable_dma_irq);
 644
 645 void omap_disable_dma_irq(int lch, u16 bits)
 646 {
 647         dma_chan[lch].enabled_irqs &= ~bits;
 648 }
 649 EXPORT_SYMBOL(omap_disable_dma_irq);
 650
 651 static inline void enable_lnk(int lch)
 652 {
 653         u32 l;
 654
 655         l = dma_read(CLNK_CTRL(lch));
 656
 657         if (cpu_class_is_omap1())
 658                 l &= ~(1 << 14);
 659
 660         /* Set the ENABLE_LNK bits */
 661         if (dma_chan[lch].next_lch != -1)
 662                 l = dma_chan[lch].next_lch | (1 << 15);
 663
 664 #ifndef CONFIG_ARCH_OMAP1
 665         if (cpu_class_is_omap2())
 666                 if (dma_chan[lch].next_linked_ch != -1)
 667                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 668 #endif
 669
 670         dma_write(l, CLNK_CTRL(lch));
 671 }
 672
 673 static inline void disable_lnk(int lch)
 674 {
 675         u32 l;
 676
 677         l = dma_read(CLNK_CTRL(lch));
 678
 679         /* Disable interrupts */
 680         if (cpu_class_is_omap1()) {
 681                 dma_write(0, CICR(lch));
 682                 /* Set the STOP_LNK bit */
 683                 l |= 1 << 14;
 684         }
 685
 686         if (cpu_class_is_omap2()) {
 687                 omap_disable_channel_irq(lch);
 688                 /* Clear the ENABLE_LNK bit */
 689                 l &= ~(1 << 15);
 690         }
 691
 692         dma_write(l, CLNK_CTRL(lch));
 693         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 694 }
 695
 696 static inline void omap2_enable_irq_lch(int lch)
 697 {
 698         u32 val;
 699         unsigned long flags;
 700
 701         if (!cpu_class_is_omap2())
 702                 return;
 703
 704         spin_lock_irqsave(&dma_chan_lock, flags);
 705         val = dma_read(IRQENABLE_L0);
 706         val |= 1 << lch;
 707         dma_write(val, IRQENABLE_L0);
 708         spin_unlock_irqrestore(&dma_chan_lock, flags);
 709 }
 710
 711 int omap_request_dma(int dev_id, const char *dev_name,
 712                      void (*callback)(int lch, u16 ch_status, void *data),
 713                      void *data, int *dma_ch_out)
 714 {
 715         int ch, free_ch = -1;
 716         unsigned long flags;
 717         struct omap_dma_lch *chan;
 718
 719         spin_lock_irqsave(&dma_chan_lock, flags);
 720         for (ch = 0; ch < dma_chan_count; ch++) {
 721                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 722                         free_ch = ch;
 723                         if (dev_id == 0)
 724                                 break;
 725                 }
 726         }
 727         if (free_ch == -1) {
 728                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 729                 return -EBUSY;
 730         }
 731         chan = dma_chan + free_ch;
 732         chan->dev_id = dev_id;
 733
 734         if (cpu_class_is_omap1())
 735                 clear_lch_regs(free_ch);
 736
 737         if (cpu_class_is_omap2())
 738                 omap_clear_dma(free_ch);
 739
 740         spin_unlock_irqrestore(&dma_chan_lock, flags);
 741
 742         chan->dev_name = dev_name;
 743         chan->callback = callback;
 744         chan->data = data;
 745         chan->flags = 0;
 746
 747 #ifndef CONFIG_ARCH_OMAP1
 748         if (cpu_class_is_omap2()) {
 749                 chan->chain_id = -1;
 750                 chan->next_linked_ch = -1;
 751         }
 752 #endif
 753
 754         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 755
 756         if (cpu_class_is_omap1())
 757                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 758         else if (cpu_class_is_omap2())
 759                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 760                         OMAP2_DMA_TRANS_ERR_IRQ;
 761
 762         if (cpu_is_omap16xx()) {
 763                 /* If the sync device is set, configure it dynamically. */
 764                 if (dev_id != 0) {
 765                         set_gdma_dev(free_ch + 1, dev_id);
 766                         dev_id = free_ch + 1;
 767                 }
 768                 /*
 769                  * Disable the 1510 compatibility mode and set the sync device
 770                  * id.
 771                  */
 772                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 773         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 774                 dma_write(dev_id, CCR(free_ch));
 775         }
 776
 777         if (cpu_class_is_omap2()) {
 778                 omap2_enable_irq_lch(free_ch);
 779                 omap_enable_channel_irq(free_ch);
 780                 /* Clear the CSR register and IRQ status register */
 781                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 782                 dma_write(1 << free_ch, IRQSTATUS_L0);
 783         }
 784
 785         *dma_ch_out = free_ch;
 786
 787         return 0;
 788 }
 789 EXPORT_SYMBOL(omap_request_dma);
 790
 791 void omap_free_dma(int lch)
 792 {
 793         unsigned long flags;
 794
 795         if (dma_chan[lch].dev_id == -1) {
 796                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 797                        lch);
 798                 return;
 799         }
 800
 801         if (cpu_class_is_omap1()) {
 802                 /* Disable all DMA interrupts for the channel. */
 803                 dma_write(0, CICR(lch));
 804                 /* Make sure the DMA transfer is stopped. */
 805                 dma_write(0, CCR(lch));
 806         }
 807
 808         if (cpu_class_is_omap2()) {
 809                 u32 val;
 810
 811                 spin_lock_irqsave(&dma_chan_lock, flags);
 812                 /* Disable interrupts */
 813                 val = dma_read(IRQENABLE_L0);
 814                 val &= ~(1 << lch);
 815                 dma_write(val, IRQENABLE_L0);
 816                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 817
 818                 /* Clear the CSR register and IRQ status register */
 819                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 820                 dma_write(1 << lch, IRQSTATUS_L0);
 821
 822                 /* Disable all DMA interrupts for the channel. */
 823                 dma_write(0, CICR(lch));
 824
 825                 /* Make sure the DMA transfer is stopped. */
 826                 dma_write(0, CCR(lch));
 827                 omap_clear_dma(lch);
 828         }
 829
 830         spin_lock_irqsave(&dma_chan_lock, flags);
 831         dma_chan[lch].dev_id = -1;
 832         dma_chan[lch].next_lch = -1;
 833         dma_chan[lch].callback = NULL;
 834         spin_unlock_irqrestore(&dma_chan_lock, flags);
 835 }
 836 EXPORT_SYMBOL(omap_free_dma);
 837
 838 /**
 839  * @brief omap_dma_set_global_params : Set global priority settings for dma
 840  *
 841  * @param arb_rate
 842  * @param max_fifo_depth
 843  * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
 844  *                                                 DMA_THREAD_RESERVE_ONET
 845  *                                                 DMA_THREAD_RESERVE_TWOT
 846  *                                                 DMA_THREAD_RESERVE_THREET
 847  */
 848 void
 849 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 850 {
 851         u32 reg;
 852
 853         if (!cpu_class_is_omap2()) {
 854                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 855                 return;
 856         }
 857
 858         if (max_fifo_depth == 0)
 859                 max_fifo_depth = 1;
 860         if (arb_rate == 0)
 861                 arb_rate = 1;
 862
 863         reg = 0xff & max_fifo_depth;
 864         reg |= (0x3 & tparams) << 12;
 865         reg |= (arb_rate & 0xff) << 16;
 866
 867         dma_write(reg, GCR);
 868 }
 869 EXPORT_SYMBOL(omap_dma_set_global_params);
 870
 871 /**
 872  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 873  *
 874  * @param lch
 875  * @param read_prio - Read priority
 876  * @param write_prio - Write priority
 877  * Both of the above can be set with one of the following values :
 878  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 879  */
 880 int
 881 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 882                       unsigned char write_prio)
 883 {
 884         u32 l;
 885
 886         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 887                 printk(KERN_ERR "Invalid channel id\n");
 888                 return -EINVAL;
 889         }
 890         l = dma_read(CCR(lch));
 891         l &= ~((1 << 6) | (1 << 26));
 892         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
 893                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 894         else
 895                 l |= ((read_prio & 0x1) << 6);
 896
 897         dma_write(l, CCR(lch));
 898
 899         return 0;
 900 }
 901 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 902
 903 /*
 904  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 905  * through omap_start_dma(). Any buffers in flight are discarded.
 906  */
 907 void omap_clear_dma(int lch)
 908 {
 909         unsigned long flags;
 910
 911         local_irq_save(flags);
 912
 913         if (cpu_class_is_omap1()) {
 914                 u32 l;
 915
 916                 l = dma_read(CCR(lch));
 917                 l &= ~OMAP_DMA_CCR_EN;
 918                 dma_write(l, CCR(lch));
 919
 920                 /* Clear pending interrupts */
 921                 l = dma_read(CSR(lch));
 922         }
 923
 924         if (cpu_class_is_omap2()) {
 925                 int i;
 926                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 927                 for (i = 0; i < 0x44; i += 4)
 928                         __raw_writel(0, lch_base + i);
 929         }
 930
 931         local_irq_restore(flags);
 932 }
 933 EXPORT_SYMBOL(omap_clear_dma);
 934
 935 void omap_start_dma(int lch)
 936 {
 937         u32 l;
 938
 939         /*
 940          * The CPC/CDAC register needs to be initialized to zero
 941          * before starting dma transfer.
 942          */
 943         if (cpu_is_omap15xx())
 944                 dma_write(0, CPC(lch));
 945         else
 946                 dma_write(0, CDAC(lch));
 947
 948         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 949                 int next_lch, cur_lch;
 950                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 951
 952                 dma_chan_link_map[lch] = 1;
 953                 /* Set the link register of the first channel */
 954                 enable_lnk(lch);
 955
 956                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 957                 cur_lch = dma_chan[lch].next_lch;
 958                 do {
 959                         next_lch = dma_chan[cur_lch].next_lch;
 960
 961                         /* The loop case: we've been here already */
 962                         if (dma_chan_link_map[cur_lch])
 963                                 break;
 964                         /* Mark the current channel */
 965                         dma_chan_link_map[cur_lch] = 1;
 966
 967                         enable_lnk(cur_lch);
 968                         omap_enable_channel_irq(cur_lch);
 969
 970                         cur_lch = next_lch;
 971                 } while (next_lch != -1);
 972         } else if (cpu_is_omap242x() ||
 973                 (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
 974
 975                 /* Errata: Need to write lch even if not using chaining */
 976                 dma_write(lch, CLNK_CTRL(lch));
 977         }
 978
 979         omap_enable_channel_irq(lch);
 980
 981         l = dma_read(CCR(lch));
 982
 983         /*
 984          * Errata: On ES2.0 BUFFERING disable must be set.
 985          * This will always fail on ES1.0
 986          */
 987         if (cpu_is_omap24xx())
 988                 l |= OMAP_DMA_CCR_EN;
 989
 990         l |= OMAP_DMA_CCR_EN;
 991         dma_write(l, CCR(lch));
 992
 993         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 994 }
 995 EXPORT_SYMBOL(omap_start_dma);
 996
 997 void omap_stop_dma(int lch)
 998 {
 999         u32 l;
1000
1001         /* Disable all interrupts on the channel */
1002         if (cpu_class_is_omap1())
1003                 dma_write(0, CICR(lch));
1004
1005         l = dma_read(CCR(lch));
1006         l &= ~OMAP_DMA_CCR_EN;
1007         dma_write(l, CCR(lch));
1008
1009         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
1010                 int next_lch, cur_lch = lch;
1011                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
1012
1013                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
1014                 do {
1015                         /* The loop case: we've been here already */
1016                         if (dma_chan_link_map[cur_lch])
1017                                 break;
1018                         /* Mark the current channel */
1019                         dma_chan_link_map[cur_lch] = 1;
1020
1021                         disable_lnk(cur_lch);
1022
1023                         next_lch = dma_chan[cur_lch].next_lch;
1024                         cur_lch = next_lch;
1025                 } while (next_lch != -1);
1026         }
1027
1028         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1029 }
1030 EXPORT_SYMBOL(omap_stop_dma);
1031
1032 /*
1033  * Allows changing the DMA callback function or data. This may be needed if
1034  * the driver shares a single DMA channel for multiple dma triggers.
1035  */
1036 int omap_set_dma_callback(int lch,
1037                           void (*callback)(int lch, u16 ch_status, void *data),
1038                           void *data)
1039 {
1040         unsigned long flags;
1041
1042         if (lch < 0)
1043                 return -ENODEV;
1044
1045         spin_lock_irqsave(&dma_chan_lock, flags);
1046         if (dma_chan[lch].dev_id == -1) {
1047                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1048                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1049                 return -EINVAL;
1050         }
1051         dma_chan[lch].callback = callback;
1052         dma_chan[lch].data = data;
1053         spin_unlock_irqrestore(&dma_chan_lock, flags);
1054
1055         return 0;
1056 }
1057 EXPORT_SYMBOL(omap_set_dma_callback);
1058
1059 /*
1060  * Returns current physical source address for the given DMA channel.
1061  * If the channel is running the caller must disable interrupts prior calling
1062  * this function and process the returned value before re-enabling interrupt to
1063  * prevent races with the interrupt handler. Note that in continuous mode there
1064  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1065  * in incorrect return value.
1066  */
1067 dma_addr_t omap_get_dma_src_pos(int lch)
1068 {
1069         dma_addr_t offset = 0;
1070
1071         if (cpu_is_omap15xx())
1072                 offset = dma_read(CPC(lch));
1073         else
1074                 offset = dma_read(CSAC(lch));
1075
1076         /*
1077          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1078          * read before the DMA controller finished disabling the channel.
1079          */
1080         if (!cpu_is_omap15xx() && offset == 0)
1081                 offset = dma_read(CSAC(lch));
1082
1083         if (cpu_class_is_omap1())
1084                 offset |= (dma_read(CSSA_U(lch)) << 16);
1085
1086         return offset;
1087 }
1088 EXPORT_SYMBOL(omap_get_dma_src_pos);
1089
1090 /*
1091  * Returns current physical destination address for the given DMA channel.
1092  * If the channel is running the caller must disable interrupts prior calling
1093  * this function and process the returned value before re-enabling interrupt to
1094  * prevent races with the interrupt handler. Note that in continuous mode there
1095  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1096  * in incorrect return value.
1097  */
1098 dma_addr_t omap_get_dma_dst_pos(int lch)
1099 {
1100         dma_addr_t offset = 0;
1101
1102         if (cpu_is_omap15xx())
1103                 offset = dma_read(CPC(lch));
1104         else
1105                 offset = dma_read(CDAC(lch));
1106
1107         /*
1108          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1109          * read before the DMA controller finished disabling the channel.
1110          */
1111         if (!cpu_is_omap15xx() && offset == 0)
1112                 offset = dma_read(CDAC(lch));
1113
1114         if (cpu_class_is_omap1())
1115                 offset |= (dma_read(CDSA_U(lch)) << 16);
1116
1117         return offset;
1118 }
1119 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1120
1121 int omap_get_dma_active_status(int lch)
1122 {
1123         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1124 }
1125 EXPORT_SYMBOL(omap_get_dma_active_status);
1126
1127 int omap_dma_running(void)
1128 {
1129         int lch;
1130
1131         if (cpu_class_is_omap1())
1132                 if (omap_lcd_dma_running())
1133                         return 1;
1134
1135         for (lch = 0; lch < dma_chan_count; lch++)
1136                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1137                         return 1;
1138
1139         return 0;
1140 }
1141
1142 /*
1143  * lch_queue DMA will start right after lch_head one is finished.
1144  * For this DMA link to start, you still need to start (see omap_start_dma)
1145  * the first one. That will fire up the entire queue.
1146  */
1147 void omap_dma_link_lch(int lch_head, int lch_queue)
1148 {
1149         if (omap_dma_in_1510_mode()) {
1150                 if (lch_head == lch_queue) {
1151                         dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1152                                                                 CCR(lch_head));
1153                         return;
1154                 }
1155                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1156                 BUG();
1157                 return;
1158         }
1159
1160         if ((dma_chan[lch_head].dev_id == -1) ||
1161             (dma_chan[lch_queue].dev_id == -1)) {
1162                 printk(KERN_ERR "omap_dma: trying to link "
1163                        "non requested channels\n");
1164                 dump_stack();
1165         }
1166
1167         dma_chan[lch_head].next_lch = lch_queue;
1168 }
1169 EXPORT_SYMBOL(omap_dma_link_lch);
1170
1171 /*
1172  * Once the DMA queue is stopped, we can destroy it.
1173  */
1174 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1175 {
1176         if (omap_dma_in_1510_mode()) {
1177                 if (lch_head == lch_queue) {
1178                         dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1179                                                                 CCR(lch_head));
1180                         return;
1181                 }
1182                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1183                 BUG();
1184                 return;
1185         }
1186
1187         if (dma_chan[lch_head].next_lch != lch_queue ||
1188             dma_chan[lch_head].next_lch == -1) {
1189                 printk(KERN_ERR "omap_dma: trying to unlink "
1190                        "non linked channels\n");
1191                 dump_stack();
1192         }
1193
1194         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1195             (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1196                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1197                        "before unlinking\n");
1198                 dump_stack();
1199         }
1200
1201         dma_chan[lch_head].next_lch = -1;
1202 }
1203 EXPORT_SYMBOL(omap_dma_unlink_lch);
1204
1205 /*----------------------------------------------------------------------------*/
1206
1207 #ifndef CONFIG_ARCH_OMAP1
1208 /* Create chain of DMA channesls */
1209 static void create_dma_lch_chain(int lch_head, int lch_queue)
1210 {
1211         u32 l;
1212
1213         /* Check if this is the first link in chain */
1214         if (dma_chan[lch_head].next_linked_ch == -1) {
1215                 dma_chan[lch_head].next_linked_ch = lch_queue;
1216                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1217                 dma_chan[lch_queue].next_linked_ch = lch_head;
1218                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1219         }
1220
1221         /* a link exists, link the new channel in circular chain */
1222         else {
1223                 dma_chan[lch_queue].next_linked_ch =
1224                                         dma_chan[lch_head].next_linked_ch;
1225                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1226                 dma_chan[lch_head].next_linked_ch = lch_queue;
1227                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1228                                         lch_queue;
1229         }
1230
1231         l = dma_read(CLNK_CTRL(lch_head));
1232         l &= ~(0x1f);
1233         l |= lch_queue;
1234         dma_write(l, CLNK_CTRL(lch_head));
1235
1236         l = dma_read(CLNK_CTRL(lch_queue));
1237         l &= ~(0x1f);
1238         l |= (dma_chan[lch_queue].next_linked_ch);
1239         dma_write(l, CLNK_CTRL(lch_queue));
1240 }
1241
1242 /**
1243  * @brief omap_request_dma_chain : Request a chain of DMA channels
1244  *
1245  * @param dev_id - Device id using the dma channel
1246  * @param dev_name - Device name
1247  * @param callback - Call back function
1248  * @chain_id -
1249  * @no_of_chans - Number of channels requested
1250  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1251  *                                            OMAP_DMA_DYNAMIC_CHAIN
1252  * @params - Channel parameters
1253  *
1254  * @return - Success : 0
1255  *           Failure: -EINVAL/-ENOMEM
1256  */
1257 int omap_request_dma_chain(int dev_id, const char *dev_name,
1258                            void (*callback) (int lch, u16 ch_status,
1259                                              void *data),
1260                            int *chain_id, int no_of_chans, int chain_mode,
1261                            struct omap_dma_channel_params params)
1262 {
1263         int *channels;
1264         int i, err;
1265
1266         /* Is the chain mode valid ? */
1267         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1268                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1269                 printk(KERN_ERR "Invalid chain mode requested\n");
1270                 return -EINVAL;
1271         }
1272
1273         if (unlikely((no_of_chans < 1
1274                         || no_of_chans > dma_lch_count))) {
1275                 printk(KERN_ERR "Invalid Number of channels requested\n");
1276                 return -EINVAL;
1277         }
1278
1279         /* Allocate a queue to maintain the status of the channels
1280          * in the chain */
1281         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1282         if (channels == NULL) {
1283                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1284                 return -ENOMEM;
1285         }
1286
1287         /* request and reserve DMA channels for the chain */
1288         for (i = 0; i < no_of_chans; i++) {
1289                 err = omap_request_dma(dev_id, dev_name,
1290                                         callback, NULL, &channels[i]);
1291                 if (err < 0) {
1292                         int j;
1293                         for (j = 0; j < i; j++)
1294                                 omap_free_dma(channels[j]);
1295                         kfree(channels);
1296                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1297                         return err;
1298                 }
1299                 dma_chan[channels[i]].prev_linked_ch = -1;
1300                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1301
1302                 /*
1303                  * Allowing client drivers to set common parameters now,
1304                  * so that later only relevant (src_start, dest_start
1305                  * and element count) can be set
1306                  */
1307                 omap_set_dma_params(channels[i], &params);
1308         }
1309
1310         *chain_id = channels[0];
1311         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1312         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1313         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1314         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1315
1316         for (i = 0; i < no_of_chans; i++)
1317                 dma_chan[channels[i]].chain_id = *chain_id;
1318
1319         /* Reset the Queue pointers */
1320         OMAP_DMA_CHAIN_QINIT(*chain_id);
1321
1322         /* Set up the chain */
1323         if (no_of_chans == 1)
1324                 create_dma_lch_chain(channels[0], channels[0]);
1325         else {
1326                 for (i = 0; i < (no_of_chans - 1); i++)
1327                         create_dma_lch_chain(channels[i], channels[i + 1]);
1328         }
1329
1330         return 0;
1331 }
1332 EXPORT_SYMBOL(omap_request_dma_chain);
1333
1334 /**
1335  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1336  * params after setting it. Dont do this while dma is running!!
1337  *
1338  * @param chain_id - Chained logical channel id.
1339  * @param params
1340  *
1341  * @return - Success : 0
1342  *           Failure : -EINVAL
1343  */
1344 int omap_modify_dma_chain_params(int chain_id,
1345                                 struct omap_dma_channel_params params)
1346 {
1347         int *channels;
1348         u32 i;
1349
1350         /* Check for input params */
1351         if (unlikely((chain_id < 0
1352                         || chain_id >= dma_lch_count))) {
1353                 printk(KERN_ERR "Invalid chain id\n");
1354                 return -EINVAL;
1355         }
1356
1357         /* Check if the chain exists */
1358         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1359                 printk(KERN_ERR "Chain doesn't exists\n");
1360                 return -EINVAL;
1361         }
1362         channels = dma_linked_lch[chain_id].linked_dmach_q;
1363
1364         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1365                 /*
1366                  * Allowing client drivers to set common parameters now,
1367                  * so that later only relevant (src_start, dest_start
1368                  * and element count) can be set
1369                  */
1370                 omap_set_dma_params(channels[i], &params);
1371         }
1372
1373         return 0;
1374 }
1375 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1376
1377 /**
1378  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1379  *
1380  * @param chain_id
1381  *
1382  * @return - Success : 0
1383  *           Failure : -EINVAL
1384  */
1385 int omap_free_dma_chain(int chain_id)
1386 {
1387         int *channels;
1388         u32 i;
1389
1390         /* Check for input params */
1391         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1392                 printk(KERN_ERR "Invalid chain id\n");
1393                 return -EINVAL;
1394         }
1395
1396         /* Check if the chain exists */
1397         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1398                 printk(KERN_ERR "Chain doesn't exists\n");
1399                 return -EINVAL;
1400         }
1401
1402         channels = dma_linked_lch[chain_id].linked_dmach_q;
1403         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1404                 dma_chan[channels[i]].next_linked_ch = -1;
1405                 dma_chan[channels[i]].prev_linked_ch = -1;
1406                 dma_chan[channels[i]].chain_id = -1;
1407                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1408                 omap_free_dma(channels[i]);
1409         }
1410
1411         kfree(channels);
1412
1413         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1414         dma_linked_lch[chain_id].chain_mode = -1;
1415         dma_linked_lch[chain_id].chain_state = -1;
1416
1417         return (0);
1418 }
1419 EXPORT_SYMBOL(omap_free_dma_chain);
1420
1421 /**
1422  * @brief omap_dma_chain_status - Check if the chain is in
1423  * active / inactive state.
1424  * @param chain_id
1425  *
1426  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1427  *           Failure : -EINVAL
1428  */
1429 int omap_dma_chain_status(int chain_id)
1430 {
1431         /* Check for input params */
1432         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1433                 printk(KERN_ERR "Invalid chain id\n");
1434                 return -EINVAL;
1435         }
1436
1437         /* Check if the chain exists */
1438         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1439                 printk(KERN_ERR "Chain doesn't exists\n");
1440                 return -EINVAL;
1441         }
1442         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1443                         dma_linked_lch[chain_id].q_count);
1444
1445         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1446                 return OMAP_DMA_CHAIN_INACTIVE;
1447
1448         return OMAP_DMA_CHAIN_ACTIVE;
1449 }
1450 EXPORT_SYMBOL(omap_dma_chain_status);
1451
1452 /**
1453  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1454  * set the params and start the transfer.
1455  *
1456  * @param chain_id
1457  * @param src_start - buffer start address
1458  * @param dest_start - Dest address
1459  * @param elem_count
1460  * @param frame_count
1461  * @param callbk_data - channel callback parameter data.
1462  *
1463  * @return  - Success : 0
1464  *            Failure: -EINVAL/-EBUSY
1465  */
1466 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1467                         int elem_count, int frame_count, void *callbk_data)
1468 {
1469         int *channels;
1470         u32 l, lch;
1471         int start_dma = 0;
1472
1473         /*
1474          * if buffer size is less than 1 then there is
1475          * no use of starting the chain
1476          */
1477         if (elem_count < 1) {
1478                 printk(KERN_ERR "Invalid buffer size\n");
1479                 return -EINVAL;
1480         }
1481
1482         /* Check for input params */
1483         if (unlikely((chain_id < 0
1484                         || chain_id >= dma_lch_count))) {
1485                 printk(KERN_ERR "Invalid chain id\n");
1486                 return -EINVAL;
1487         }
1488
1489         /* Check if the chain exists */
1490         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1491                 printk(KERN_ERR "Chain doesn't exist\n");
1492                 return -EINVAL;
1493         }
1494
1495         /* Check if all the channels in chain are in use */
1496         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1497                 return -EBUSY;
1498
1499         /* Frame count may be negative in case of indexed transfers */
1500         channels = dma_linked_lch[chain_id].linked_dmach_q;
1501
1502         /* Get a free channel */
1503         lch = channels[dma_linked_lch[chain_id].q_tail];
1504
1505         /* Store the callback data */
1506         dma_chan[lch].data = callbk_data;
1507
1508         /* Increment the q_tail */
1509         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1510
1511         /* Set the params to the free channel */
1512         if (src_start != 0)
1513                 dma_write(src_start, CSSA(lch));
1514         if (dest_start != 0)
1515                 dma_write(dest_start, CDSA(lch));
1516
1517         /* Write the buffer size */
1518         dma_write(elem_count, CEN(lch));
1519         dma_write(frame_count, CFN(lch));
1520
1521         /*
1522          * If the chain is dynamically linked,
1523          * then we may have to start the chain if its not active
1524          */
1525         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1526
1527                 /*
1528                  * In Dynamic chain, if the chain is not started,
1529                  * queue the channel
1530                  */
1531                 if (dma_linked_lch[chain_id].chain_state ==
1532                                                 DMA_CHAIN_NOTSTARTED) {
1533                         /* Enable the link in previous channel */
1534                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1535                                                                 DMA_CH_QUEUED)
1536                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1537                         dma_chan[lch].state = DMA_CH_QUEUED;
1538                 }
1539
1540                 /*
1541                  * Chain is already started, make sure its active,
1542                  * if not then start the chain
1543                  */
1544                 else {
1545                         start_dma = 1;
1546
1547                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1548                                                         DMA_CH_STARTED) {
1549                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1550                                 dma_chan[lch].state = DMA_CH_QUEUED;
1551                                 start_dma = 0;
1552                                 if (0 == ((1 << 7) & dma_read(
1553                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1554                                         disable_lnk(dma_chan[lch].
1555                                                     prev_linked_ch);
1556                                         pr_debug("\n prev ch is stopped\n");
1557                                         start_dma = 1;
1558                                 }
1559                         }
1560
1561                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1562                                                         == DMA_CH_QUEUED) {
1563                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1564                                 dma_chan[lch].state = DMA_CH_QUEUED;
1565                                 start_dma = 0;
1566                         }
1567                         omap_enable_channel_irq(lch);
1568
1569                         l = dma_read(CCR(lch));
1570
1571                         if ((0 == (l & (1 << 24))))
1572                                 l &= ~(1 << 25);
1573                         else
1574                                 l |= (1 << 25);
1575                         if (start_dma == 1) {
1576                                 if (0 == (l & (1 << 7))) {
1577                                         l |= (1 << 7);
1578                                         dma_chan[lch].state = DMA_CH_STARTED;
1579                                         pr_debug("starting %d\n", lch);
1580                                         dma_write(l, CCR(lch));
1581                                 } else
1582                                         start_dma = 0;
1583                         } else {
1584                                 if (0 == (l & (1 << 7)))
1585                                         dma_write(l, CCR(lch));
1586                         }
1587                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1588                 }
1589         }
1590
1591         return 0;
1592 }
1593 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1594
1595 /**
1596  * @brief omap_start_dma_chain_transfers - Start the chain
1597  *
1598  * @param chain_id
1599  *
1600  * @return - Success : 0
1601  *           Failure : -EINVAL/-EBUSY
1602  */
1603 int omap_start_dma_chain_transfers(int chain_id)
1604 {
1605         int *channels;
1606         u32 l, i;
1607
1608         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1609                 printk(KERN_ERR "Invalid chain id\n");
1610                 return -EINVAL;
1611         }
1612
1613         channels = dma_linked_lch[chain_id].linked_dmach_q;
1614
1615         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1616                 printk(KERN_ERR "Chain is already started\n");
1617                 return -EBUSY;
1618         }
1619
1620         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1621                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1622                                                                         i++) {
1623                         enable_lnk(channels[i]);
1624                         omap_enable_channel_irq(channels[i]);
1625                 }
1626         } else {
1627                 omap_enable_channel_irq(channels[0]);
1628         }
1629
1630         l = dma_read(CCR(channels[0]));
1631         l |= (1 << 7);
1632         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1633         dma_chan[channels[0]].state = DMA_CH_STARTED;
1634
1635         if ((0 == (l & (1 << 24))))
1636                 l &= ~(1 << 25);
1637         else
1638                 l |= (1 << 25);
1639         dma_write(l, CCR(channels[0]));
1640
1641         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1642
1643         return 0;
1644 }
1645 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1646
1647 /**
1648  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1649  *
1650  * @param chain_id
1651  *
1652  * @return - Success : 0
1653  *           Failure : EINVAL
1654  */
1655 int omap_stop_dma_chain_transfers(int chain_id)
1656 {
1657         int *channels;
1658         u32 l, i;
1659         u32 sys_cf;
1660
1661         /* Check for input params */
1662         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1663                 printk(KERN_ERR "Invalid chain id\n");
1664                 return -EINVAL;
1665         }
1666
1667         /* Check if the chain exists */
1668         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1669                 printk(KERN_ERR "Chain doesn't exists\n");
1670                 return -EINVAL;
1671         }
1672         channels = dma_linked_lch[chain_id].linked_dmach_q;
1673
1674         /*
1675          * DMA Errata:
1676          * Special programming model needed to disable DMA before end of block
1677          */
1678         sys_cf = dma_read(OCP_SYSCONFIG);
1679         l = sys_cf;
1680         /* Middle mode reg set no Standby */
1681         l &= ~((1 << 12)|(1 << 13));
1682         dma_write(l, OCP_SYSCONFIG);
1683
1684         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1685
1686                 /* Stop the Channel transmission */
1687                 l = dma_read(CCR(channels[i]));
1688                 l &= ~(1 << 7);
1689                 dma_write(l, CCR(channels[i]));
1690
1691                 /* Disable the link in all the channels */
1692                 disable_lnk(channels[i]);
1693                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1694
1695         }
1696         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1697
1698         /* Reset the Queue pointers */
1699         OMAP_DMA_CHAIN_QINIT(chain_id);
1700
1701         /* Errata - put in the old value */
1702         dma_write(sys_cf, OCP_SYSCONFIG);
1703
1704         return 0;
1705 }
1706 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1707
1708 /* Get the index of the ongoing DMA in chain */
1709 /**
1710  * @brief omap_get_dma_chain_index - Get the element and frame index
1711  * of the ongoing DMA in chain
1712  *
1713  * @param chain_id
1714  * @param ei - Element index
1715  * @param fi - Frame index
1716  *
1717  * @return - Success : 0
1718  *           Failure : -EINVAL
1719  */
1720 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1721 {
1722         int lch;
1723         int *channels;
1724
1725         /* Check for input params */
1726         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1727                 printk(KERN_ERR "Invalid chain id\n");
1728                 return -EINVAL;
1729         }
1730
1731         /* Check if the chain exists */
1732         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1733                 printk(KERN_ERR "Chain doesn't exists\n");
1734                 return -EINVAL;
1735         }
1736         if ((!ei) || (!fi))
1737                 return -EINVAL;
1738
1739         channels = dma_linked_lch[chain_id].linked_dmach_q;
1740
1741         /* Get the current channel */
1742         lch = channels[dma_linked_lch[chain_id].q_head];
1743
1744         *ei = dma_read(CCEN(lch));
1745         *fi = dma_read(CCFN(lch));
1746
1747         return 0;
1748 }
1749 EXPORT_SYMBOL(omap_get_dma_chain_index);
1750
1751 /**
1752  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1753  * ongoing DMA in chain
1754  *
1755  * @param chain_id
1756  *
1757  * @return - Success : Destination position
1758  *           Failure : -EINVAL
1759  */
1760 int omap_get_dma_chain_dst_pos(int chain_id)
1761 {
1762         int lch;
1763         int *channels;
1764
1765         /* Check for input params */
1766         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1767                 printk(KERN_ERR "Invalid chain id\n");
1768                 return -EINVAL;
1769         }
1770
1771         /* Check if the chain exists */
1772         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1773                 printk(KERN_ERR "Chain doesn't exists\n");
1774                 return -EINVAL;
1775         }
1776
1777         channels = dma_linked_lch[chain_id].linked_dmach_q;
1778
1779         /* Get the current channel */
1780         lch = channels[dma_linked_lch[chain_id].q_head];
1781
1782         return dma_read(CDAC(lch));
1783 }
1784 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1785
1786 /**
1787  * @brief omap_get_dma_chain_src_pos - Get the source position
1788  * of the ongoing DMA in chain
1789  * @param chain_id
1790  *
1791  * @return - Success : Destination position
1792  *           Failure : -EINVAL
1793  */
1794 int omap_get_dma_chain_src_pos(int chain_id)
1795 {
1796         int lch;
1797         int *channels;
1798
1799         /* Check for input params */
1800         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1801                 printk(KERN_ERR "Invalid chain id\n");
1802                 return -EINVAL;
1803         }
1804
1805         /* Check if the chain exists */
1806         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1807                 printk(KERN_ERR "Chain doesn't exists\n");
1808                 return -EINVAL;
1809         }
1810
1811         channels = dma_linked_lch[chain_id].linked_dmach_q;
1812
1813         /* Get the current channel */
1814         lch = channels[dma_linked_lch[chain_id].q_head];
1815
1816         return dma_read(CSAC(lch));
1817 }
1818 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1819 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1820
1821 /*----------------------------------------------------------------------------*/
1822
1823 #ifdef CONFIG_ARCH_OMAP1
1824
1825 static int omap1_dma_handle_ch(int ch)
1826 {
1827         u32 csr;
1828
1829         if (enable_1510_mode && ch >= 6) {
1830                 csr = dma_chan[ch].saved_csr;
1831                 dma_chan[ch].saved_csr = 0;
1832         } else
1833                 csr = dma_read(CSR(ch));
1834         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1835                 dma_chan[ch + 6].saved_csr = csr >> 7;
1836                 csr &= 0x7f;
1837         }
1838         if ((csr & 0x3f) == 0)
1839                 return 0;
1840         if (unlikely(dma_chan[ch].dev_id == -1)) {
1841                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1842                        "%d (CSR %04x)\n", ch, csr);
1843                 return 0;
1844         }
1845         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1846                 printk(KERN_WARNING "DMA timeout with device %d\n",
1847                        dma_chan[ch].dev_id);
1848         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1849                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1850                        "with device %d\n", dma_chan[ch].dev_id);
1851         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1852                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1853         if (likely(dma_chan[ch].callback != NULL))
1854                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1855
1856         return 1;
1857 }
1858
1859 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1860 {
1861         int ch = ((int) dev_id) - 1;
1862         int handled = 0;
1863
1864         for (;;) {
1865                 int handled_now = 0;
1866
1867                 handled_now += omap1_dma_handle_ch(ch);
1868                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1869                         handled_now += omap1_dma_handle_ch(ch + 6);
1870                 if (!handled_now)
1871                         break;
1872                 handled += handled_now;
1873         }
1874
1875         return handled ? IRQ_HANDLED : IRQ_NONE;
1876 }
1877
1878 #else
1879 #define omap1_dma_irq_handler   NULL
1880 #endif
1881
1882 #ifdef CONFIG_ARCH_OMAP2PLUS
1883
1884 static int omap2_dma_handle_ch(int ch)
1885 {
1886         u32 status = dma_read(CSR(ch));
1887
1888         if (!status) {
1889                 if (printk_ratelimit())
1890                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1891                                 ch);
1892                 dma_write(1 << ch, IRQSTATUS_L0);
1893                 return 0;
1894         }
1895         if (unlikely(dma_chan[ch].dev_id == -1)) {
1896                 if (printk_ratelimit())
1897                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1898                                         "channel %d\n", status, ch);
1899                 return 0;
1900         }
1901         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1902                 printk(KERN_INFO
1903                        "DMA synchronization event drop occurred with device "
1904                        "%d\n", dma_chan[ch].dev_id);
1905         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1906                 printk(KERN_INFO "DMA transaction error with device %d\n",
1907                        dma_chan[ch].dev_id);
1908                 if (cpu_class_is_omap2()) {
1909                         /* Errata: sDMA Channel is not disabled
1910                          * after a transaction error. So we explicitely
1911                          * disable the channel
1912                          */
1913                         u32 ccr;
1914
1915                         ccr = dma_read(CCR(ch));
1916                         ccr &= ~OMAP_DMA_CCR_EN;
1917                         dma_write(ccr, CCR(ch));
1918                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1919                 }
1920         }
1921         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1922                 printk(KERN_INFO "DMA secure error with device %d\n",
1923                        dma_chan[ch].dev_id);
1924         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1925                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1926                        dma_chan[ch].dev_id);
1927
1928         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1929         dma_write(1 << ch, IRQSTATUS_L0);
1930
1931         /* If the ch is not chained then chain_id will be -1 */
1932         if (dma_chan[ch].chain_id != -1) {
1933                 int chain_id = dma_chan[ch].chain_id;
1934                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1935                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1936                         dma_chan[dma_chan[ch].next_linked_ch].state =
1937                                                         DMA_CH_STARTED;
1938                 if (dma_linked_lch[chain_id].chain_mode ==
1939                                                 OMAP_DMA_DYNAMIC_CHAIN)
1940                         disable_lnk(ch);
1941
1942                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1943                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1944
1945                 status = dma_read(CSR(ch));
1946         }
1947
1948         dma_write(status, CSR(ch));
1949
1950         if (likely(dma_chan[ch].callback != NULL))
1951                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1952
1953         return 0;
1954 }
1955
1956 /* STATUS register count is from 1-32 while our is 0-31 */
1957 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1958 {
1959         u32 val, enable_reg;
1960         int i;
1961
1962         val = dma_read(IRQSTATUS_L0);
1963         if (val == 0) {
1964                 if (printk_ratelimit())
1965                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1966                 return IRQ_HANDLED;
1967         }
1968         enable_reg = dma_read(IRQENABLE_L0);
1969         val &= enable_reg; /* Dispatch only relevant interrupts */
1970         for (i = 0; i < dma_lch_count && val != 0; i++) {
1971                 if (val & 1)
1972                         omap2_dma_handle_ch(i);
1973                 val >>= 1;
1974         }
1975
1976         return IRQ_HANDLED;
1977 }
1978
1979 static struct irqaction omap24xx_dma_irq = {
1980         .name = "DMA",
1981         .handler = omap2_dma_irq_handler,
1982         .flags = IRQF_DISABLED
1983 };
1984
1985 #else
1986 static struct irqaction omap24xx_dma_irq;
1987 #endif
1988
1989 /*----------------------------------------------------------------------------*/
1990
1991 void omap_dma_global_context_save(void)
1992 {
1993         omap_dma_global_context.dma_irqenable_l0 =
1994                 dma_read(IRQENABLE_L0);
1995         omap_dma_global_context.dma_ocp_sysconfig =
1996                 dma_read(OCP_SYSCONFIG);
1997         omap_dma_global_context.dma_gcr = dma_read(GCR);
1998 }
1999
2000 void omap_dma_global_context_restore(void)
2001 {
2002         int ch;
2003
2004         dma_write(omap_dma_global_context.dma_gcr, GCR);
2005         dma_write(omap_dma_global_context.dma_ocp_sysconfig,
2006                 OCP_SYSCONFIG);
2007         dma_write(omap_dma_global_context.dma_irqenable_l0,
2008                 IRQENABLE_L0);
2009
2010         /*
2011          * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
2012          * after secure sram context save and restore. Hence we need to
2013          * manually clear those IRQs to avoid spurious interrupts. This
2014          * affects only secure devices.
2015          */
2016         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
2017                 dma_write(0x3 , IRQSTATUS_L0);
2018
2019         for (ch = 0; ch < dma_chan_count; ch++)
2020                 if (dma_chan[ch].dev_id != -1)
2021                         omap_clear_dma(ch);
2022 }
2023
2024 /*----------------------------------------------------------------------------*/
2025
2026 static int __init omap_init_dma(void)
2027 {
2028         unsigned long base;
2029         int ch, r;
2030
2031         if (cpu_class_is_omap1()) {
2032                 base = OMAP1_DMA_BASE;
2033                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2034         } else if (cpu_is_omap24xx()) {
2035                 base = OMAP24XX_DMA4_BASE;
2036                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2037         } else if (cpu_is_omap34xx()) {
2038                 base = OMAP34XX_DMA4_BASE;
2039                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2040         } else if (cpu_is_omap44xx()) {
2041                 base = OMAP44XX_DMA4_BASE;
2042                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2043         } else {
2044                 pr_err("DMA init failed for unsupported omap\n");
2045                 return -ENODEV;
2046         }
2047
2048         omap_dma_base = ioremap(base, SZ_4K);
2049         BUG_ON(!omap_dma_base);
2050
2051         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2052                         && (omap_dma_reserve_channels <= dma_lch_count))
2053                 dma_lch_count = omap_dma_reserve_channels;
2054
2055         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2056                                 GFP_KERNEL);
2057         if (!dma_chan) {
2058                 r = -ENOMEM;
2059                 goto out_unmap;
2060         }
2061
2062         if (cpu_class_is_omap2()) {
2063                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2064                                                 dma_lch_count, GFP_KERNEL);
2065                 if (!dma_linked_lch) {
2066                         r = -ENOMEM;
2067                         goto out_free;
2068                 }
2069         }
2070
2071         if (cpu_is_omap15xx()) {
2072                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2073                 dma_chan_count = 9;
2074                 enable_1510_mode = 1;
2075         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2076                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2077                        dma_read(HW_ID));
2078                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2079                        (dma_read(CAPS_0_U) << 16) |
2080                        dma_read(CAPS_0_L),
2081                        (dma_read(CAPS_1_U) << 16) |
2082                        dma_read(CAPS_1_L),
2083                        dma_read(CAPS_2), dma_read(CAPS_3),
2084                        dma_read(CAPS_4));
2085                 if (!enable_1510_mode) {
2086                         u16 w;
2087
2088                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2089                         w = dma_read(GSCR);
2090                         w |= 1 << 3;
2091                         dma_write(w, GSCR);
2092                         dma_chan_count = 16;
2093                 } else
2094                         dma_chan_count = 9;
2095         } else if (cpu_class_is_omap2()) {
2096                 u8 revision = dma_read(REVISION) & 0xff;
2097                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2098                        revision >> 4, revision & 0xf);
2099                 dma_chan_count = dma_lch_count;
2100         } else {
2101                 dma_chan_count = 0;
2102                 return 0;
2103         }
2104
2105         spin_lock_init(&dma_chan_lock);
2106
2107         for (ch = 0; ch < dma_chan_count; ch++) {
2108                 omap_clear_dma(ch);
2109                 dma_chan[ch].dev_id = -1;
2110                 dma_chan[ch].next_lch = -1;
2111
2112                 if (ch >= 6 && enable_1510_mode)
2113                         continue;
2114
2115                 if (cpu_class_is_omap1()) {
2116                         /*
2117                          * request_irq() doesn't like dev_id (ie. ch) being
2118                          * zero, so we have to kludge around this.
2119                          */
2120                         r = request_irq(omap1_dma_irq[ch],
2121                                         omap1_dma_irq_handler, 0, "DMA",
2122                                         (void *) (ch + 1));
2123                         if (r != 0) {
2124                                 int i;
2125
2126                                 printk(KERN_ERR "unable to request IRQ %d "
2127                                        "for DMA (error %d)\n",
2128                                        omap1_dma_irq[ch], r);
2129                                 for (i = 0; i < ch; i++)
2130                                         free_irq(omap1_dma_irq[i],
2131                                                  (void *) (i + 1));
2132                                 goto out_free;
2133                         }
2134                 }
2135         }
2136
2137         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2138                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2139                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2140
2141         if (cpu_class_is_omap2()) {
2142                 int irq;
2143                 if (cpu_is_omap44xx())
2144                         irq = OMAP44XX_IRQ_SDMA_0;
2145                 else
2146                         irq = INT_24XX_SDMA_IRQ0;
2147                 setup_irq(irq, &omap24xx_dma_irq);
2148         }
2149
2150         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
2151                 /* Enable smartidle idlemodes and autoidle */
2152                 u32 v = dma_read(OCP_SYSCONFIG);
2153                 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2154                                 DMA_SYSCONFIG_SIDLEMODE_MASK |
2155                                 DMA_SYSCONFIG_AUTOIDLE);
2156                 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2157                         DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2158                         DMA_SYSCONFIG_AUTOIDLE);
2159                 dma_write(v , OCP_SYSCONFIG);
2160                 /* reserve dma channels 0 and 1 in high security devices */
2161                 if (cpu_is_omap34xx() &&
2162                         (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2163                         printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2164                                         "HS ROM code\n");
2165                         dma_chan[0].dev_id = 0;
2166                         dma_chan[1].dev_id = 1;
2167                 }
2168         }
2169
2170         return 0;
2171
2172 out_free:
2173         kfree(dma_chan);
2174
2175 out_unmap:
2176         iounmap(omap_dma_base);
2177
2178         return r;
2179 }
2180
2181 arch_initcall(omap_init_dma);
2182
2183 /*
2184  * Reserve the omap SDMA channels using cmdline bootarg
2185  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2186  */
2187 static int __init omap_dma_cmdline_reserve_ch(char *str)
2188 {
2189         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2190                 omap_dma_reserve_channels = 0;
2191         return 1;
2192 }
2193
2194 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2195
2196