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   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/hardware.h>
  31 #include <asm/dma.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/arch/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE         0x01
  47 #define OMAP_DMA_CCR_EN         (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE  (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode = 0;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (* callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126
 127 static spinlock_t dma_chan_lock;
 128 static struct omap_dma_lch *dma_chan;
 129
 130 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 131         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 132         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 133         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 134         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 135         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 136 };
 137
 138 static inline void disable_lnk(int lch);
 139 static void omap_disable_channel_irq(int lch);
 140 static inline void omap_enable_channel_irq(int lch);
 141
 142 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 143                                                 __func__);
 144
 145 #ifdef CONFIG_ARCH_OMAP15XX
 146 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 147 int omap_dma_in_1510_mode(void)
 148 {
 149         return enable_1510_mode;
 150 }
 151 #else
 152 #define omap_dma_in_1510_mode()         0
 153 #endif
 154
 155 #ifdef CONFIG_ARCH_OMAP1
 156 static inline int get_gdma_dev(int req)
 157 {
 158         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 159         int shift = ((req - 1) % 5) * 6;
 160
 161         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 162 }
 163
 164 static inline void set_gdma_dev(int req, int dev)
 165 {
 166         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 167         int shift = ((req - 1) % 5) * 6;
 168         u32 l;
 169
 170         l = omap_readl(reg);
 171         l &= ~(0x3f << shift);
 172         l |= (dev - 1) << shift;
 173         omap_writel(l, reg);
 174 }
 175 #else
 176 #define set_gdma_dev(req, dev)  do {} while (0)
 177 #endif
 178
 179 static void clear_lch_regs(int lch)
 180 {
 181         int i;
 182         u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
 183
 184         for (i = 0; i < 0x2c; i += 2)
 185                 omap_writew(0, lch_base + i);
 186 }
 187
 188 void omap_set_dma_priority(int lch, int dst_port, int priority)
 189 {
 190         unsigned long reg;
 191         u32 l;
 192
 193         if (cpu_class_is_omap1()) {
 194                 switch (dst_port) {
 195                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 196                         reg = OMAP_TC_OCPT1_PRIOR;
 197                         break;
 198                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 199                         reg = OMAP_TC_OCPT2_PRIOR;
 200                         break;
 201                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 202                         reg = OMAP_TC_EMIFF_PRIOR;
 203                         break;
 204                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 205                         reg = OMAP_TC_EMIFS_PRIOR;
 206                         break;
 207                 default:
 208                         BUG();
 209                         return;
 210                 }
 211                 l = omap_readl(reg);
 212                 l &= ~(0xf << 8);
 213                 l |= (priority & 0xf) << 8;
 214                 omap_writel(l, reg);
 215         }
 216
 217         if (cpu_class_is_omap2()) {
 218                 if (priority)
 219                         OMAP_DMA_CCR_REG(lch) |= (1 << 6);
 220                 else
 221                         OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
 222         }
 223 }
 224
 225 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 226                                   int frame_count, int sync_mode,
 227                                   int dma_trigger, int src_or_dst_synch)
 228 {
 229         OMAP_DMA_CSDP_REG(lch) &= ~0x03;
 230         OMAP_DMA_CSDP_REG(lch) |= data_type;
 231
 232         if (cpu_class_is_omap1()) {
 233                 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
 234                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 235                         OMAP_DMA_CCR_REG(lch) |= 1 << 5;
 236
 237                 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
 238                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 239                         OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
 240         }
 241
 242         if (cpu_class_is_omap2() && dma_trigger) {
 243                 u32 val = OMAP_DMA_CCR_REG(lch);
 244
 245                 val &= ~(3 << 19);
 246                 if (dma_trigger > 63)
 247                         val |= 1 << 20;
 248                 if (dma_trigger > 31)
 249                         val |= 1 << 19;
 250
 251                 val &= ~(0x1f);
 252                 val |= (dma_trigger & 0x1f);
 253
 254                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 255                         val |= 1 << 5;
 256                 else
 257                         val &= ~(1 << 5);
 258
 259                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 260                         val |= 1 << 18;
 261                 else
 262                         val &= ~(1 << 18);
 263
 264                 if (src_or_dst_synch)
 265                         val |= 1 << 24;         /* source synch */
 266                 else
 267                         val &= ~(1 << 24);      /* dest synch */
 268
 269                 OMAP_DMA_CCR_REG(lch) = val;
 270         }
 271
 272         OMAP_DMA_CEN_REG(lch) = elem_count;
 273         OMAP_DMA_CFN_REG(lch) = frame_count;
 274 }
 275
 276 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 277 {
 278         u16 w;
 279
 280         BUG_ON(omap_dma_in_1510_mode());
 281
 282         if (cpu_class_is_omap2()) {
 283                 REVISIT_24XX();
 284                 return;
 285         }
 286
 287         w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
 288         switch (mode) {
 289         case OMAP_DMA_CONSTANT_FILL:
 290                 w |= 0x01;
 291                 break;
 292         case OMAP_DMA_TRANSPARENT_COPY:
 293                 w |= 0x02;
 294                 break;
 295         case OMAP_DMA_COLOR_DIS:
 296                 break;
 297         default:
 298                 BUG();
 299         }
 300         OMAP1_DMA_CCR2_REG(lch) = w;
 301
 302         w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
 303         /* Default is channel type 2D */
 304         if (mode) {
 305                 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
 306                 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
 307                 w |= 1;         /* Channel type G */
 308         }
 309         OMAP1_DMA_LCH_CTRL_REG(lch) = w;
 310 }
 311
 312 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 313 {
 314         if (cpu_class_is_omap2()) {
 315                 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
 316                 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
 317         }
 318 }
 319
 320 /* Note that src_port is only for omap1 */
 321 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 322                              unsigned long src_start,
 323                              int src_ei, int src_fi)
 324 {
 325         if (cpu_class_is_omap1()) {
 326                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
 327                 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
 328         }
 329
 330         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
 331         OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
 332
 333         if (cpu_class_is_omap1()) {
 334                 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
 335                 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
 336         }
 337
 338         if (cpu_class_is_omap2())
 339                 OMAP2_DMA_CSSA_REG(lch) = src_start;
 340
 341         OMAP_DMA_CSEI_REG(lch) = src_ei;
 342         OMAP_DMA_CSFI_REG(lch) = src_fi;
 343 }
 344
 345 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
 346 {
 347         omap_set_dma_transfer_params(lch, params->data_type,
 348                                      params->elem_count, params->frame_count,
 349                                      params->sync_mode, params->trigger,
 350                                      params->src_or_dst_synch);
 351         omap_set_dma_src_params(lch, params->src_port,
 352                                 params->src_amode, params->src_start,
 353                                 params->src_ei, params->src_fi);
 354
 355         omap_set_dma_dest_params(lch, params->dst_port,
 356                                  params->dst_amode, params->dst_start,
 357                                  params->dst_ei, params->dst_fi);
 358         if (params->read_prio || params->write_prio)
 359                 omap_dma_set_prio_lch(lch, params->read_prio,
 360                                       params->write_prio);
 361 }
 362
 363 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 364 {
 365         if (cpu_class_is_omap2()) {
 366                 REVISIT_24XX();
 367                 return;
 368         }
 369         OMAP_DMA_CSEI_REG(lch) = eidx;
 370         OMAP_DMA_CSFI_REG(lch) = fidx;
 371 }
 372
 373 void omap_set_dma_src_data_pack(int lch, int enable)
 374 {
 375         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
 376         if (enable)
 377                 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
 378 }
 379
 380 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 381 {
 382         unsigned int burst = 0;
 383         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
 384
 385         switch (burst_mode) {
 386         case OMAP_DMA_DATA_BURST_DIS:
 387                 break;
 388         case OMAP_DMA_DATA_BURST_4:
 389                 if (cpu_class_is_omap2())
 390                         burst = 0x1;
 391                 else
 392                         burst = 0x2;
 393                 break;
 394         case OMAP_DMA_DATA_BURST_8:
 395                 if (cpu_class_is_omap2()) {
 396                         burst = 0x2;
 397                         break;
 398                 }
 399                 /* not supported by current hardware on OMAP1
 400                  * w |= (0x03 << 7);
 401                  * fall through
 402                  */
 403         case OMAP_DMA_DATA_BURST_16:
 404                 if (cpu_class_is_omap2()) {
 405                         burst = 0x3;
 406                         break;
 407                 }
 408                 /* OMAP1 don't support burst 16
 409                  * fall through
 410                  */
 411         default:
 412                 BUG();
 413         }
 414         OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
 415 }
 416
 417 /* Note that dest_port is only for OMAP1 */
 418 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 419                               unsigned long dest_start,
 420                               int dst_ei, int dst_fi)
 421 {
 422         if (cpu_class_is_omap1()) {
 423                 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
 424                 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
 425         }
 426
 427         OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
 428         OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
 429
 430         if (cpu_class_is_omap1()) {
 431                 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
 432                 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
 433         }
 434
 435         if (cpu_class_is_omap2())
 436                 OMAP2_DMA_CDSA_REG(lch) = dest_start;
 437
 438         OMAP_DMA_CDEI_REG(lch) = dst_ei;
 439         OMAP_DMA_CDFI_REG(lch) = dst_fi;
 440 }
 441
 442 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 443 {
 444         if (cpu_class_is_omap2()) {
 445                 REVISIT_24XX();
 446                 return;
 447         }
 448         OMAP_DMA_CDEI_REG(lch) = eidx;
 449         OMAP_DMA_CDFI_REG(lch) = fidx;
 450 }
 451
 452 void omap_set_dma_dest_data_pack(int lch, int enable)
 453 {
 454         OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
 455         if (enable)
 456                 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
 457 }
 458
 459 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 460 {
 461         unsigned int burst = 0;
 462         OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
 463
 464         switch (burst_mode) {
 465         case OMAP_DMA_DATA_BURST_DIS:
 466                 break;
 467         case OMAP_DMA_DATA_BURST_4:
 468                 if (cpu_class_is_omap2())
 469                         burst = 0x1;
 470                 else
 471                         burst = 0x2;
 472                 break;
 473         case OMAP_DMA_DATA_BURST_8:
 474                 if (cpu_class_is_omap2())
 475                         burst = 0x2;
 476                 else
 477                         burst = 0x3;
 478                 break;
 479         case OMAP_DMA_DATA_BURST_16:
 480                 if (cpu_class_is_omap2()) {
 481                         burst = 0x3;
 482                         break;
 483                 }
 484                 /* OMAP1 don't support burst 16
 485                  * fall through
 486                  */
 487         default:
 488                 printk(KERN_ERR "Invalid DMA burst mode\n");
 489                 BUG();
 490                 return;
 491         }
 492         OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
 493 }
 494
 495 static inline void omap_enable_channel_irq(int lch)
 496 {
 497         u32 status;
 498
 499         /* Clear CSR */
 500         if (cpu_class_is_omap1())
 501                 status = OMAP_DMA_CSR_REG(lch);
 502         else if (cpu_class_is_omap2())
 503                 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
 504
 505         /* Enable some nice interrupts. */
 506         OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
 507 }
 508
 509 static void omap_disable_channel_irq(int lch)
 510 {
 511         if (cpu_class_is_omap2())
 512                 OMAP_DMA_CICR_REG(lch) = 0;
 513 }
 514
 515 void omap_enable_dma_irq(int lch, u16 bits)
 516 {
 517         dma_chan[lch].enabled_irqs |= bits;
 518 }
 519
 520 void omap_disable_dma_irq(int lch, u16 bits)
 521 {
 522         dma_chan[lch].enabled_irqs &= ~bits;
 523 }
 524
 525 static inline void enable_lnk(int lch)
 526 {
 527         if (cpu_class_is_omap1())
 528                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
 529
 530         /* Set the ENABLE_LNK bits */
 531         if (dma_chan[lch].next_lch != -1)
 532                 OMAP_DMA_CLNK_CTRL_REG(lch) =
 533                         dma_chan[lch].next_lch | (1 << 15);
 534
 535 #ifndef CONFIG_ARCH_OMAP1
 536         if (dma_chan[lch].next_linked_ch != -1)
 537                 OMAP_DMA_CLNK_CTRL_REG(lch) =
 538                         dma_chan[lch].next_linked_ch | (1 << 15);
 539 #endif
 540 }
 541
 542 static inline void disable_lnk(int lch)
 543 {
 544         /* Disable interrupts */
 545         if (cpu_class_is_omap1()) {
 546                 OMAP_DMA_CICR_REG(lch) = 0;
 547                 /* Set the STOP_LNK bit */
 548                 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
 549         }
 550
 551         if (cpu_class_is_omap2()) {
 552                 omap_disable_channel_irq(lch);
 553                 /* Clear the ENABLE_LNK bit */
 554                 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
 555         }
 556
 557         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 558 }
 559
 560 static inline void omap2_enable_irq_lch(int lch)
 561 {
 562         u32 val;
 563
 564         if (!cpu_class_is_omap2())
 565                 return;
 566
 567         val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 568         val |= 1 << lch;
 569         omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 570 }
 571
 572 int omap_request_dma(int dev_id, const char *dev_name,
 573                      void (* callback)(int lch, u16 ch_status, void *data),
 574                      void *data, int *dma_ch_out)
 575 {
 576         int ch, free_ch = -1;
 577         unsigned long flags;
 578         struct omap_dma_lch *chan;
 579
 580         spin_lock_irqsave(&dma_chan_lock, flags);
 581         for (ch = 0; ch < dma_chan_count; ch++) {
 582                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 583                         free_ch = ch;
 584                         if (dev_id == 0)
 585                                 break;
 586                 }
 587         }
 588         if (free_ch == -1) {
 589                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 590                 return -EBUSY;
 591         }
 592         chan = dma_chan + free_ch;
 593         chan->dev_id = dev_id;
 594
 595         if (cpu_class_is_omap1())
 596                 clear_lch_regs(free_ch);
 597
 598         if (cpu_class_is_omap2())
 599                 omap_clear_dma(free_ch);
 600
 601         spin_unlock_irqrestore(&dma_chan_lock, flags);
 602
 603         chan->dev_name = dev_name;
 604         chan->callback = callback;
 605         chan->data = data;
 606 #ifndef CONFIG_ARCH_OMAP1
 607         chan->chain_id = -1;
 608         chan->next_linked_ch = -1;
 609 #endif
 610         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 611
 612         if (cpu_class_is_omap1())
 613                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 614         else if (cpu_class_is_omap2())
 615                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 616                         OMAP2_DMA_TRANS_ERR_IRQ;
 617
 618         if (cpu_is_omap16xx()) {
 619                 /* If the sync device is set, configure it dynamically. */
 620                 if (dev_id != 0) {
 621                         set_gdma_dev(free_ch + 1, dev_id);
 622                         dev_id = free_ch + 1;
 623                 }
 624                 /* Disable the 1510 compatibility mode and set the sync device
 625                  * id. */
 626                 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
 627         } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
 628                 OMAP_DMA_CCR_REG(free_ch) = dev_id;
 629         }
 630
 631         if (cpu_class_is_omap2()) {
 632                 omap2_enable_irq_lch(free_ch);
 633
 634                 omap_enable_channel_irq(free_ch);
 635                 /* Clear the CSR register and IRQ status register */
 636                 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
 637                 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
 638         }
 639
 640         *dma_ch_out = free_ch;
 641
 642         return 0;
 643 }
 644
 645 void omap_free_dma(int lch)
 646 {
 647         unsigned long flags;
 648
 649         spin_lock_irqsave(&dma_chan_lock, flags);
 650         if (dma_chan[lch].dev_id == -1) {
 651                 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
 652                        lch);
 653                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 654                 return;
 655         }
 656         dma_chan[lch].dev_id = -1;
 657         dma_chan[lch].next_lch = -1;
 658         dma_chan[lch].callback = NULL;
 659         spin_unlock_irqrestore(&dma_chan_lock, flags);
 660
 661         if (cpu_class_is_omap1()) {
 662                 /* Disable all DMA interrupts for the channel. */
 663                 OMAP_DMA_CICR_REG(lch) = 0;
 664                 /* Make sure the DMA transfer is stopped. */
 665                 OMAP_DMA_CCR_REG(lch) = 0;
 666         }
 667
 668         if (cpu_class_is_omap2()) {
 669                 u32 val;
 670                 /* Disable interrupts */
 671                 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
 672                 val &= ~(1 << lch);
 673                 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
 674
 675                 /* Clear the CSR register and IRQ status register */
 676                 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
 677                 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
 678
 679                 /* Disable all DMA interrupts for the channel. */
 680                 OMAP_DMA_CICR_REG(lch) = 0;
 681
 682                 /* Make sure the DMA transfer is stopped. */
 683                 OMAP_DMA_CCR_REG(lch) = 0;
 684                 omap_clear_dma(lch);
 685         }
 686 }
 687
 688 /**
 689  * @brief omap_dma_set_global_params : Set global priority settings for dma
 690  *
 691  * @param arb_rate
 692  * @param max_fifo_depth
 693  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 694  *                                                  DMA_THREAD_RESERVE_ONET
 695  *                                                  DMA_THREAD_RESERVE_TWOT
 696  *                                                  DMA_THREAD_RESERVE_THREET
 697  */
 698 void
 699 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 700 {
 701         u32 reg;
 702
 703         if (!cpu_class_is_omap2()) {
 704                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 705                 return;
 706         }
 707
 708         if (arb_rate == 0)
 709                 arb_rate = 1;
 710
 711         reg = (arb_rate & 0xff) << 16;
 712         reg |= (0xff & max_fifo_depth);
 713
 714         omap_writel(reg, OMAP_DMA4_GCR_REG);
 715 }
 716 EXPORT_SYMBOL(omap_dma_set_global_params);
 717
 718 /**
 719  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 720  *
 721  * @param lch
 722  * @param read_prio - Read priority
 723  * @param write_prio - Write priority
 724  * Both of the above can be set with one of the following values :
 725  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 726  */
 727 int
 728 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 729                       unsigned char write_prio)
 730 {
 731         u32 w;
 732
 733         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 734                 printk(KERN_ERR "Invalid channel id\n");
 735                 return -EINVAL;
 736         }
 737         w = OMAP_DMA_CCR_REG(lch);
 738         w &= ~((1 << 6) | (1 << 26));
 739         if (cpu_is_omap2430() || cpu_is_omap34xx())
 740                 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 741         else
 742                 w |= ((read_prio & 0x1) << 6);
 743
 744         OMAP_DMA_CCR_REG(lch) = w;
 745         return 0;
 746 }
 747 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 748
 749 /*
 750  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 751  * through omap_start_dma(). Any buffers in flight are discarded.
 752  */
 753 void omap_clear_dma(int lch)
 754 {
 755         unsigned long flags;
 756
 757         local_irq_save(flags);
 758
 759         if (cpu_class_is_omap1()) {
 760                 int status;
 761                 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 762
 763                 /* Clear pending interrupts */
 764                 status = OMAP_DMA_CSR_REG(lch);
 765         }
 766
 767         if (cpu_class_is_omap2()) {
 768                 int i;
 769                 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
 770                 for (i = 0; i < 0x44; i += 4)
 771                         omap_writel(0, lch_base + i);
 772         }
 773
 774         local_irq_restore(flags);
 775 }
 776
 777 void omap_start_dma(int lch)
 778 {
 779         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 780                 int next_lch, cur_lch;
 781                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 782
 783                 dma_chan_link_map[lch] = 1;
 784                 /* Set the link register of the first channel */
 785                 enable_lnk(lch);
 786
 787                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 788                 cur_lch = dma_chan[lch].next_lch;
 789                 do {
 790                         next_lch = dma_chan[cur_lch].next_lch;
 791
 792                         /* The loop case: we've been here already */
 793                         if (dma_chan_link_map[cur_lch])
 794                                 break;
 795                         /* Mark the current channel */
 796                         dma_chan_link_map[cur_lch] = 1;
 797
 798                         enable_lnk(cur_lch);
 799                         omap_enable_channel_irq(cur_lch);
 800
 801                         cur_lch = next_lch;
 802                 } while (next_lch != -1);
 803         } else if (cpu_class_is_omap2()) {
 804                 /* Errata: Need to write lch even if not using chaining */
 805                 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
 806         }
 807
 808         omap_enable_channel_irq(lch);
 809
 810         /* Errata: On ES2.0 BUFFERING disable must be set.
 811          * This will always fail on ES1.0 */
 812         if (cpu_is_omap24xx()) {
 813                 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 814         }
 815
 816         OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
 817
 818         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 819 }
 820
 821 void omap_stop_dma(int lch)
 822 {
 823         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 824                 int next_lch, cur_lch = lch;
 825                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 826
 827                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 828                 do {
 829                         /* The loop case: we've been here already */
 830                         if (dma_chan_link_map[cur_lch])
 831                                 break;
 832                         /* Mark the current channel */
 833                         dma_chan_link_map[cur_lch] = 1;
 834
 835                         disable_lnk(cur_lch);
 836
 837                         next_lch = dma_chan[cur_lch].next_lch;
 838                         cur_lch = next_lch;
 839                 } while (next_lch != -1);
 840
 841                 return;
 842         }
 843
 844         /* Disable all interrupts on the channel */
 845         if (cpu_class_is_omap1())
 846                 OMAP_DMA_CICR_REG(lch) = 0;
 847
 848         OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
 849         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 850 }
 851
 852 /*
 853  * Allows changing the DMA callback function or data. This may be needed if
 854  * the driver shares a single DMA channel for multiple dma triggers.
 855  */
 856 int omap_set_dma_callback(int lch,
 857                           void (* callback)(int lch, u16 ch_status, void *data),
 858                           void *data)
 859 {
 860         unsigned long flags;
 861
 862         if (lch < 0)
 863                 return -ENODEV;
 864
 865         spin_lock_irqsave(&dma_chan_lock, flags);
 866         if (dma_chan[lch].dev_id == -1) {
 867                 printk(KERN_ERR "DMA callback for not set for free channel\n");
 868                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 869                 return -EINVAL;
 870         }
 871         dma_chan[lch].callback = callback;
 872         dma_chan[lch].data = data;
 873         spin_unlock_irqrestore(&dma_chan_lock, flags);
 874
 875         return 0;
 876 }
 877
 878 /*
 879  * Returns current physical source address for the given DMA channel.
 880  * If the channel is running the caller must disable interrupts prior calling
 881  * this function and process the returned value before re-enabling interrupt to
 882  * prevent races with the interrupt handler. Note that in continuous mode there
 883  * is a chance for CSSA_L register overflow inbetween the two reads resulting
 884  * in incorrect return value.
 885  */
 886 dma_addr_t omap_get_dma_src_pos(int lch)
 887 {
 888         dma_addr_t offset = 0;
 889
 890         if (cpu_class_is_omap1())
 891                 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
 892                                        (OMAP1_DMA_CSSA_U_REG(lch) << 16));
 893
 894         if (cpu_class_is_omap2())
 895                 offset = OMAP_DMA_CSAC_REG(lch);
 896
 897         return offset;
 898 }
 899
 900 /*
 901  * Returns current physical destination address for the given DMA channel.
 902  * If the channel is running the caller must disable interrupts prior calling
 903  * this function and process the returned value before re-enabling interrupt to
 904  * prevent races with the interrupt handler. Note that in continuous mode there
 905  * is a chance for CDSA_L register overflow inbetween the two reads resulting
 906  * in incorrect return value.
 907  */
 908 dma_addr_t omap_get_dma_dst_pos(int lch)
 909 {
 910         dma_addr_t offset = 0;
 911
 912         if (cpu_class_is_omap1())
 913                 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
 914                                        (OMAP1_DMA_CDSA_U_REG(lch) << 16));
 915
 916         if (cpu_class_is_omap2())
 917                 offset = OMAP_DMA_CDAC_REG(lch);
 918
 919         return offset;
 920 }
 921
 922 /*
 923  * Returns current source transfer counting for the given DMA channel.
 924  * Can be used to monitor the progress of a transfer inside a block.
 925  * It must be called with disabled interrupts.
 926  */
 927 int omap_get_dma_src_addr_counter(int lch)
 928 {
 929         return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
 930 }
 931
 932 int omap_dma_running(void)
 933 {
 934         int lch;
 935
 936         /* Check if LCD DMA is running */
 937         if (cpu_is_omap16xx())
 938                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
 939                         return 1;
 940
 941         for (lch = 0; lch < dma_chan_count; lch++)
 942                 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
 943                         return 1;
 944
 945         return 0;
 946 }
 947
 948 /*
 949  * lch_queue DMA will start right after lch_head one is finished.
 950  * For this DMA link to start, you still need to start (see omap_start_dma)
 951  * the first one. That will fire up the entire queue.
 952  */
 953 void omap_dma_link_lch (int lch_head, int lch_queue)
 954 {
 955         if (omap_dma_in_1510_mode()) {
 956                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 957                 BUG();
 958                 return;
 959         }
 960
 961         if ((dma_chan[lch_head].dev_id == -1) ||
 962             (dma_chan[lch_queue].dev_id == -1)) {
 963                 printk(KERN_ERR "omap_dma: trying to link "
 964                        "non requested channels\n");
 965                 dump_stack();
 966         }
 967
 968         dma_chan[lch_head].next_lch = lch_queue;
 969 }
 970
 971 /*
 972  * Once the DMA queue is stopped, we can destroy it.
 973  */
 974 void omap_dma_unlink_lch (int lch_head, int lch_queue)
 975 {
 976         if (omap_dma_in_1510_mode()) {
 977                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
 978                 BUG();
 979                 return;
 980         }
 981
 982         if (dma_chan[lch_head].next_lch != lch_queue ||
 983             dma_chan[lch_head].next_lch == -1) {
 984                 printk(KERN_ERR "omap_dma: trying to unlink "
 985                        "non linked channels\n");
 986                 dump_stack();
 987         }
 988
 989
 990         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
 991             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
 992                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
 993                        "before unlinking\n");
 994                 dump_stack();
 995         }
 996
 997         dma_chan[lch_head].next_lch = -1;
 998 }
 999
1000 #ifndef CONFIG_ARCH_OMAP1
1001 /* Create chain of DMA channesls */
1002 static void create_dma_lch_chain(int lch_head, int lch_queue)
1003 {
1004         u32 w;
1005
1006         /* Check if this is the first link in chain */
1007         if (dma_chan[lch_head].next_linked_ch == -1) {
1008                 dma_chan[lch_head].next_linked_ch = lch_queue;
1009                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1010                 dma_chan[lch_queue].next_linked_ch = lch_head;
1011                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1012         }
1013
1014         /* a link exists, link the new channel in circular chain */
1015         else {
1016                 dma_chan[lch_queue].next_linked_ch =
1017                                         dma_chan[lch_head].next_linked_ch;
1018                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1019                 dma_chan[lch_head].next_linked_ch = lch_queue;
1020                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1021                                         lch_queue;
1022         }
1023
1024         w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
1025         w &= ~(0x1f);
1026         w |= lch_queue;
1027         OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
1028
1029         w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
1030         w &= ~(0x1f);
1031         w |= (dma_chan[lch_queue].next_linked_ch);
1032         OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
1033 }
1034
1035 /**
1036  * @brief omap_request_dma_chain : Request a chain of DMA channels
1037  *
1038  * @param dev_id - Device id using the dma channel
1039  * @param dev_name - Device name
1040  * @param callback - Call back function
1041  * @chain_id -
1042  * @no_of_chans - Number of channels requested
1043  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1044  *                                            OMAP_DMA_DYNAMIC_CHAIN
1045  * @params - Channel parameters
1046  *
1047  * @return - Succes : 0
1048  *           Failure: -EINVAL/-ENOMEM
1049  */
1050 int omap_request_dma_chain(int dev_id, const char *dev_name,
1051                            void (*callback) (int chain_id, u16 ch_status,
1052                                              void *data),
1053                            int *chain_id, int no_of_chans, int chain_mode,
1054                            struct omap_dma_channel_params params)
1055 {
1056         int *channels;
1057         int i, err;
1058
1059         /* Is the chain mode valid ? */
1060         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1061                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1062                 printk(KERN_ERR "Invalid chain mode requested\n");
1063                 return -EINVAL;
1064         }
1065
1066         if (unlikely((no_of_chans < 1
1067                         || no_of_chans > dma_lch_count))) {
1068                 printk(KERN_ERR "Invalid Number of channels requested\n");
1069                 return -EINVAL;
1070         }
1071
1072         /* Allocate a queue to maintain the status of the channels
1073          * in the chain */
1074         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1075         if (channels == NULL) {
1076                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1077                 return -ENOMEM;
1078         }
1079
1080         /* request and reserve DMA channels for the chain */
1081         for (i = 0; i < no_of_chans; i++) {
1082                 err = omap_request_dma(dev_id, dev_name,
1083                                         callback, 0, &channels[i]);
1084                 if (err < 0) {
1085                         int j;
1086                         for (j = 0; j < i; j++)
1087                                 omap_free_dma(channels[j]);
1088                         kfree(channels);
1089                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1090                         return err;
1091                 }
1092                 dma_chan[channels[i]].prev_linked_ch = -1;
1093                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1094
1095                 /*
1096                  * Allowing client drivers to set common parameters now,
1097                  * so that later only relevant (src_start, dest_start
1098                  * and element count) can be set
1099                  */
1100                 omap_set_dma_params(channels[i], &params);
1101         }
1102
1103         *chain_id = channels[0];
1104         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1105         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1106         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1107         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1108
1109         for (i = 0; i < no_of_chans; i++)
1110                 dma_chan[channels[i]].chain_id = *chain_id;
1111
1112         /* Reset the Queue pointers */
1113         OMAP_DMA_CHAIN_QINIT(*chain_id);
1114
1115         /* Set up the chain */
1116         if (no_of_chans == 1)
1117                 create_dma_lch_chain(channels[0], channels[0]);
1118         else {
1119                 for (i = 0; i < (no_of_chans - 1); i++)
1120                         create_dma_lch_chain(channels[i], channels[i + 1]);
1121         }
1122         return 0;
1123 }
1124 EXPORT_SYMBOL(omap_request_dma_chain);
1125
1126 /**
1127  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1128  * params after setting it. Dont do this while dma is running!!
1129  *
1130  * @param chain_id - Chained logical channel id.
1131  * @param params
1132  *
1133  * @return - Success : 0
1134  *           Failure : -EINVAL
1135  */
1136 int omap_modify_dma_chain_params(int chain_id,
1137                                 struct omap_dma_channel_params params)
1138 {
1139         int *channels;
1140         u32 i;
1141
1142         /* Check for input params */
1143         if (unlikely((chain_id < 0
1144                         || chain_id >= dma_lch_count))) {
1145                 printk(KERN_ERR "Invalid chain id\n");
1146                 return -EINVAL;
1147         }
1148
1149         /* Check if the chain exists */
1150         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1151                 printk(KERN_ERR "Chain doesn't exists\n");
1152                 return -EINVAL;
1153         }
1154         channels = dma_linked_lch[chain_id].linked_dmach_q;
1155
1156         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1157                 /*
1158                  * Allowing client drivers to set common parameters now,
1159                  * so that later only relevant (src_start, dest_start
1160                  * and element count) can be set
1161                  */
1162                 omap_set_dma_params(channels[i], &params);
1163         }
1164         return 0;
1165 }
1166 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1167
1168 /**
1169  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1170  *
1171  * @param chain_id
1172  *
1173  * @return - Success : 0
1174  *           Failure : -EINVAL
1175  */
1176 int omap_free_dma_chain(int chain_id)
1177 {
1178         int *channels;
1179         u32 i;
1180
1181         /* Check for input params */
1182         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1183                 printk(KERN_ERR "Invalid chain id\n");
1184                 return -EINVAL;
1185         }
1186
1187         /* Check if the chain exists */
1188         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1189                 printk(KERN_ERR "Chain doesn't exists\n");
1190                 return -EINVAL;
1191         }
1192
1193         channels = dma_linked_lch[chain_id].linked_dmach_q;
1194         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1195                 dma_chan[channels[i]].next_linked_ch = -1;
1196                 dma_chan[channels[i]].prev_linked_ch = -1;
1197                 dma_chan[channels[i]].chain_id = -1;
1198                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1199                 omap_free_dma(channels[i]);
1200         }
1201
1202         kfree(channels);
1203
1204         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1205         dma_linked_lch[chain_id].chain_mode = -1;
1206         dma_linked_lch[chain_id].chain_state = -1;
1207         return (0);
1208 }
1209 EXPORT_SYMBOL(omap_free_dma_chain);
1210
1211 /**
1212  * @brief omap_dma_chain_status - Check if the chain is in
1213  * active / inactive state.
1214  * @param chain_id
1215  *
1216  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1217  *           Failure : -EINVAL
1218  */
1219 int omap_dma_chain_status(int chain_id)
1220 {
1221         /* Check for input params */
1222         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1223                 printk(KERN_ERR "Invalid chain id\n");
1224                 return -EINVAL;
1225         }
1226
1227         /* Check if the chain exists */
1228         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1229                 printk(KERN_ERR "Chain doesn't exists\n");
1230                 return -EINVAL;
1231         }
1232         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1233                         dma_linked_lch[chain_id].q_count);
1234
1235         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1236                 return OMAP_DMA_CHAIN_INACTIVE;
1237         return OMAP_DMA_CHAIN_ACTIVE;
1238 }
1239 EXPORT_SYMBOL(omap_dma_chain_status);
1240
1241 /**
1242  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1243  * set the params and start the transfer.
1244  *
1245  * @param chain_id
1246  * @param src_start - buffer start address
1247  * @param dest_start - Dest address
1248  * @param elem_count
1249  * @param frame_count
1250  * @param callbk_data - channel callback parameter data.
1251  *
1252  * @return  - Success : 0
1253  *            Failure: -EINVAL/-EBUSY
1254  */
1255 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1256                         int elem_count, int frame_count, void *callbk_data)
1257 {
1258         int *channels;
1259         u32 w, lch;
1260         int start_dma = 0;
1261
1262         /* if buffer size is less than 1 then there is
1263          * no use of starting the chain */
1264         if (elem_count < 1) {
1265                 printk(KERN_ERR "Invalid buffer size\n");
1266                 return -EINVAL;
1267         }
1268
1269         /* Check for input params */
1270         if (unlikely((chain_id < 0
1271                         || chain_id >= dma_lch_count))) {
1272                 printk(KERN_ERR "Invalid chain id\n");
1273                 return -EINVAL;
1274         }
1275
1276         /* Check if the chain exists */
1277         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1278                 printk(KERN_ERR "Chain doesn't exist\n");
1279                 return -EINVAL;
1280         }
1281
1282         /* Check if all the channels in chain are in use */
1283         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1284                 return -EBUSY;
1285
1286         /* Frame count may be negative in case of indexed transfers */
1287         channels = dma_linked_lch[chain_id].linked_dmach_q;
1288
1289         /* Get a free channel */
1290         lch = channels[dma_linked_lch[chain_id].q_tail];
1291
1292         /* Store the callback data */
1293         dma_chan[lch].data = callbk_data;
1294
1295         /* Increment the q_tail */
1296         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1297
1298         /* Set the params to the free channel */
1299         if (src_start != 0)
1300                 OMAP2_DMA_CSSA_REG(lch) = src_start;
1301         if (dest_start != 0)
1302                 OMAP2_DMA_CDSA_REG(lch) = dest_start;
1303
1304         /* Write the buffer size */
1305         OMAP_DMA_CEN_REG(lch) = elem_count;
1306         OMAP_DMA_CFN_REG(lch) = frame_count;
1307
1308         /* If the chain is dynamically linked,
1309          * then we may have to start the chain if its not active */
1310         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1311
1312                 /* In Dynamic chain, if the chain is not started,
1313                  * queue the channel */
1314                 if (dma_linked_lch[chain_id].chain_state ==
1315                                                 DMA_CHAIN_NOTSTARTED) {
1316                         /* Enable the link in previous channel */
1317                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1318                                                                 DMA_CH_QUEUED)
1319                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1320                         dma_chan[lch].state = DMA_CH_QUEUED;
1321                 }
1322
1323                 /* Chain is already started, make sure its active,
1324                  * if not then start the chain */
1325                 else {
1326                         start_dma = 1;
1327
1328                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1329                                                         DMA_CH_STARTED) {
1330                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1331                                 dma_chan[lch].state = DMA_CH_QUEUED;
1332                                 start_dma = 0;
1333                                 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
1334                                         (dma_chan[lch].prev_linked_ch)))) {
1335                                         disable_lnk(dma_chan[lch].
1336                                                     prev_linked_ch);
1337                                         pr_debug("\n prev ch is stopped\n");
1338                                         start_dma = 1;
1339                                 }
1340                         }
1341
1342                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1343                                                         == DMA_CH_QUEUED) {
1344                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1345                                 dma_chan[lch].state = DMA_CH_QUEUED;
1346                                 start_dma = 0;
1347                         }
1348                         omap_enable_channel_irq(lch);
1349
1350                         w = OMAP_DMA_CCR_REG(lch);
1351
1352                         if ((0 == (w & (1 << 24))))
1353                                 w &= ~(1 << 25);
1354                         else
1355                                 w |= (1 << 25);
1356                         if (start_dma == 1) {
1357                                 if (0 == (w & (1 << 7))) {
1358                                         w |= (1 << 7);
1359                                         dma_chan[lch].state = DMA_CH_STARTED;
1360                                         pr_debug("starting %d\n", lch);
1361                                         OMAP_DMA_CCR_REG(lch) = w;
1362                                 } else
1363                                         start_dma = 0;
1364                         } else {
1365                                 if (0 == (w & (1 << 7)))
1366                                         OMAP_DMA_CCR_REG(lch) = w;
1367                         }
1368                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1369                 }
1370         }
1371         return 0;
1372 }
1373 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1374
1375 /**
1376  * @brief omap_start_dma_chain_transfers - Start the chain
1377  *
1378  * @param chain_id
1379  *
1380  * @return - Success : 0
1381  *           Failure : -EINVAL/-EBUSY
1382  */
1383 int omap_start_dma_chain_transfers(int chain_id)
1384 {
1385         int *channels;
1386         u32 w, i;
1387
1388         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1389                 printk(KERN_ERR "Invalid chain id\n");
1390                 return -EINVAL;
1391         }
1392
1393         channels = dma_linked_lch[chain_id].linked_dmach_q;
1394
1395         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1396                 printk(KERN_ERR "Chain is already started\n");
1397                 return -EBUSY;
1398         }
1399
1400         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1401                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1402                                                                         i++) {
1403                         enable_lnk(channels[i]);
1404                         omap_enable_channel_irq(channels[i]);
1405                 }
1406         } else {
1407                 omap_enable_channel_irq(channels[0]);
1408         }
1409
1410         w = OMAP_DMA_CCR_REG(channels[0]);
1411         w |= (1 << 7);
1412         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1413         dma_chan[channels[0]].state = DMA_CH_STARTED;
1414
1415         if ((0 == (w & (1 << 24))))
1416                 w &= ~(1 << 25);
1417         else
1418                 w |= (1 << 25);
1419         OMAP_DMA_CCR_REG(channels[0]) = w;
1420
1421         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1422         return 0;
1423 }
1424 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1425
1426 /**
1427  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1428  *
1429  * @param chain_id
1430  *
1431  * @return - Success : 0
1432  *           Failure : EINVAL
1433  */
1434 int omap_stop_dma_chain_transfers(int chain_id)
1435 {
1436         int *channels;
1437         u32 w, i;
1438         u32 sys_cf;
1439
1440         /* Check for input params */
1441         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1442                 printk(KERN_ERR "Invalid chain id\n");
1443                 return -EINVAL;
1444         }
1445
1446         /* Check if the chain exists */
1447         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1448                 printk(KERN_ERR "Chain doesn't exists\n");
1449                 return -EINVAL;
1450         }
1451         channels = dma_linked_lch[chain_id].linked_dmach_q;
1452
1453         /* DMA Errata:
1454          * Special programming model needed to disable DMA before end of block
1455          */
1456         sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
1457         w = sys_cf;
1458         /* Middle mode reg set no Standby */
1459         w &= ~((1 << 12)|(1 << 13));
1460         omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
1461
1462         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1463
1464                 /* Stop the Channel transmission */
1465                 w = OMAP_DMA_CCR_REG(channels[i]);
1466                 w &= ~(1 << 7);
1467                 OMAP_DMA_CCR_REG(channels[i]) = w;
1468
1469                 /* Disable the link in all the channels */
1470                 disable_lnk(channels[i]);
1471                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1472
1473         }
1474         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1475
1476         /* Reset the Queue pointers */
1477         OMAP_DMA_CHAIN_QINIT(chain_id);
1478
1479         /* Errata - put in the old value */
1480         omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
1481         return 0;
1482 }
1483 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1484
1485 /* Get the index of the ongoing DMA in chain */
1486 /**
1487  * @brief omap_get_dma_chain_index - Get the element and frame index
1488  * of the ongoing DMA in chain
1489  *
1490  * @param chain_id
1491  * @param ei - Element index
1492  * @param fi - Frame index
1493  *
1494  * @return - Success : 0
1495  *           Failure : -EINVAL
1496  */
1497 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1498 {
1499         int lch;
1500         int *channels;
1501
1502         /* Check for input params */
1503         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1504                 printk(KERN_ERR "Invalid chain id\n");
1505                 return -EINVAL;
1506         }
1507
1508         /* Check if the chain exists */
1509         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1510                 printk(KERN_ERR "Chain doesn't exists\n");
1511                 return -EINVAL;
1512         }
1513         if ((!ei) || (!fi))
1514                 return -EINVAL;
1515
1516         channels = dma_linked_lch[chain_id].linked_dmach_q;
1517
1518         /* Get the current channel */
1519         lch = channels[dma_linked_lch[chain_id].q_head];
1520
1521         *ei = OMAP2_DMA_CCEN_REG(lch);
1522         *fi = OMAP2_DMA_CCFN_REG(lch);
1523
1524         return 0;
1525 }
1526 EXPORT_SYMBOL(omap_get_dma_chain_index);
1527
1528 /**
1529  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1530  * ongoing DMA in chain
1531  *
1532  * @param chain_id
1533  *
1534  * @return - Success : Destination position
1535  *           Failure : -EINVAL
1536  */
1537 int omap_get_dma_chain_dst_pos(int chain_id)
1538 {
1539         int lch;
1540         int *channels;
1541
1542         /* Check for input params */
1543         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1544                 printk(KERN_ERR "Invalid chain id\n");
1545                 return -EINVAL;
1546         }
1547
1548         /* Check if the chain exists */
1549         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1550                 printk(KERN_ERR "Chain doesn't exists\n");
1551                 return -EINVAL;
1552         }
1553
1554         channels = dma_linked_lch[chain_id].linked_dmach_q;
1555
1556         /* Get the current channel */
1557         lch = channels[dma_linked_lch[chain_id].q_head];
1558
1559         return (OMAP_DMA_CDAC_REG(lch));
1560 }
1561 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1562
1563 /**
1564  * @brief omap_get_dma_chain_src_pos - Get the source position
1565  * of the ongoing DMA in chain
1566  * @param chain_id
1567  *
1568  * @return - Success : Destination position
1569  *           Failure : -EINVAL
1570  */
1571 int omap_get_dma_chain_src_pos(int chain_id)
1572 {
1573         int lch;
1574         int *channels;
1575
1576         /* Check for input params */
1577         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1578                 printk(KERN_ERR "Invalid chain id\n");
1579                 return -EINVAL;
1580         }
1581
1582         /* Check if the chain exists */
1583         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1584                 printk(KERN_ERR "Chain doesn't exists\n");
1585                 return -EINVAL;
1586         }
1587
1588         channels = dma_linked_lch[chain_id].linked_dmach_q;
1589
1590         /* Get the current channel */
1591         lch = channels[dma_linked_lch[chain_id].q_head];
1592
1593         return (OMAP_DMA_CSAC_REG(lch));
1594 }
1595 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1596 #endif
1597
1598 /*----------------------------------------------------------------------------*/
1599
1600 #ifdef CONFIG_ARCH_OMAP1
1601
1602 static int omap1_dma_handle_ch(int ch)
1603 {
1604         u16 csr;
1605
1606         if (enable_1510_mode && ch >= 6) {
1607                 csr = dma_chan[ch].saved_csr;
1608                 dma_chan[ch].saved_csr = 0;
1609         } else
1610                 csr = OMAP_DMA_CSR_REG(ch);
1611         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1612                 dma_chan[ch + 6].saved_csr = csr >> 7;
1613                 csr &= 0x7f;
1614         }
1615         if ((csr & 0x3f) == 0)
1616                 return 0;
1617         if (unlikely(dma_chan[ch].dev_id == -1)) {
1618                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1619                        "%d (CSR %04x)\n", ch, csr);
1620                 return 0;
1621         }
1622         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1623                 printk(KERN_WARNING "DMA timeout with device %d\n",
1624                        dma_chan[ch].dev_id);
1625         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1626                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1627                        "with device %d\n", dma_chan[ch].dev_id);
1628         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1629                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1630         if (likely(dma_chan[ch].callback != NULL))
1631                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1632         return 1;
1633 }
1634
1635 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1636 {
1637         int ch = ((int) dev_id) - 1;
1638         int handled = 0;
1639
1640         for (;;) {
1641                 int handled_now = 0;
1642
1643                 handled_now += omap1_dma_handle_ch(ch);
1644                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1645                         handled_now += omap1_dma_handle_ch(ch + 6);
1646                 if (!handled_now)
1647                         break;
1648                 handled += handled_now;
1649         }
1650
1651         return handled ? IRQ_HANDLED : IRQ_NONE;
1652 }
1653
1654 #else
1655 #define omap1_dma_irq_handler   NULL
1656 #endif
1657
1658 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1659
1660 static int omap2_dma_handle_ch(int ch)
1661 {
1662         u32 status = OMAP_DMA_CSR_REG(ch);
1663
1664         if (!status) {
1665                 if (printk_ratelimit())
1666                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
1667                 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
1668                 return 0;
1669         }
1670         if (unlikely(dma_chan[ch].dev_id == -1)) {
1671                 if (printk_ratelimit())
1672                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1673                                         "channel %d\n", status, ch);
1674                 return 0;
1675         }
1676         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1677                 printk(KERN_INFO
1678                        "DMA synchronization event drop occurred with device "
1679                        "%d\n", dma_chan[ch].dev_id);
1680         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
1681                 printk(KERN_INFO "DMA transaction error with device %d\n",
1682                        dma_chan[ch].dev_id);
1683         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1684                 printk(KERN_INFO "DMA secure error with device %d\n",
1685                        dma_chan[ch].dev_id);
1686         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1687                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1688                        dma_chan[ch].dev_id);
1689
1690         OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
1691         omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
1692
1693         /* If the ch is not chained then chain_id will be -1 */
1694         if (dma_chan[ch].chain_id != -1) {
1695                 int chain_id = dma_chan[ch].chain_id;
1696                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1697                 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
1698                         dma_chan[dma_chan[ch].next_linked_ch].state =
1699                                                         DMA_CH_STARTED;
1700                 if (dma_linked_lch[chain_id].chain_mode ==
1701                                                 OMAP_DMA_DYNAMIC_CHAIN)
1702                         disable_lnk(ch);
1703
1704                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1705                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1706
1707                 status = OMAP_DMA_CSR_REG(ch);
1708         }
1709
1710         if (likely(dma_chan[ch].callback != NULL))
1711                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1712
1713         OMAP_DMA_CSR_REG(ch) = status;
1714
1715         return 0;
1716 }
1717
1718 /* STATUS register count is from 1-32 while our is 0-31 */
1719 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1720 {
1721         u32 val;
1722         int i;
1723
1724         val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
1725         if (val == 0) {
1726                 if (printk_ratelimit())
1727                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1728                 return IRQ_HANDLED;
1729         }
1730         for (i = 0; i < dma_lch_count && val != 0; i++) {
1731                 if (val & 1)
1732                         omap2_dma_handle_ch(i);
1733                 val >>= 1;
1734         }
1735
1736         return IRQ_HANDLED;
1737 }
1738
1739 static struct irqaction omap24xx_dma_irq = {
1740         .name = "DMA",
1741         .handler = omap2_dma_irq_handler,
1742         .flags = IRQF_DISABLED
1743 };
1744
1745 #else
1746 static struct irqaction omap24xx_dma_irq;
1747 #endif
1748
1749 /*----------------------------------------------------------------------------*/
1750
1751 static struct lcd_dma_info {
1752         spinlock_t lock;
1753         int reserved;
1754         void (* callback)(u16 status, void *data);
1755         void *cb_data;
1756
1757         int active;
1758         unsigned long addr, size;
1759         int rotate, data_type, xres, yres;
1760         int vxres;
1761         int mirror;
1762         int xscale, yscale;
1763         int ext_ctrl;
1764         int src_port;
1765         int single_transfer;
1766 } lcd_dma;
1767
1768 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1769                          int data_type)
1770 {
1771         lcd_dma.addr = addr;
1772         lcd_dma.data_type = data_type;
1773         lcd_dma.xres = fb_xres;
1774         lcd_dma.yres = fb_yres;
1775 }
1776
1777 void omap_set_lcd_dma_src_port(int port)
1778 {
1779         lcd_dma.src_port = port;
1780 }
1781
1782 void omap_set_lcd_dma_ext_controller(int external)
1783 {
1784         lcd_dma.ext_ctrl = external;
1785 }
1786
1787 void omap_set_lcd_dma_single_transfer(int single)
1788 {
1789         lcd_dma.single_transfer = single;
1790 }
1791
1792
1793 void omap_set_lcd_dma_b1_rotation(int rotate)
1794 {
1795         if (omap_dma_in_1510_mode()) {
1796                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1797                 BUG();
1798                 return;
1799         }
1800         lcd_dma.rotate = rotate;
1801 }
1802
1803 void omap_set_lcd_dma_b1_mirror(int mirror)
1804 {
1805         if (omap_dma_in_1510_mode()) {
1806                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1807                 BUG();
1808         }
1809         lcd_dma.mirror = mirror;
1810 }
1811
1812 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1813 {
1814         if (omap_dma_in_1510_mode()) {
1815                 printk(KERN_ERR "DMA virtual resulotion is not supported "
1816                                 "in 1510 mode\n");
1817                 BUG();
1818         }
1819         lcd_dma.vxres = vxres;
1820 }
1821
1822 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1823 {
1824         if (omap_dma_in_1510_mode()) {
1825                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1826                 BUG();
1827         }
1828         lcd_dma.xscale = xscale;
1829         lcd_dma.yscale = yscale;
1830 }
1831
1832 static void set_b1_regs(void)
1833 {
1834         unsigned long top, bottom;
1835         int es;
1836         u16 w;
1837         unsigned long en, fn;
1838         long ei, fi;
1839         unsigned long vxres;
1840         unsigned int xscale, yscale;
1841
1842         switch (lcd_dma.data_type) {
1843         case OMAP_DMA_DATA_TYPE_S8:
1844                 es = 1;
1845                 break;
1846         case OMAP_DMA_DATA_TYPE_S16:
1847                 es = 2;
1848                 break;
1849         case OMAP_DMA_DATA_TYPE_S32:
1850                 es = 4;
1851                 break;
1852         default:
1853                 BUG();
1854                 return;
1855         }
1856
1857         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1858         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1859         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1860         BUG_ON(vxres < lcd_dma.xres);
1861 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1862 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1863         switch (lcd_dma.rotate) {
1864         case 0:
1865                 if (!lcd_dma.mirror) {
1866                         top = PIXADDR(0, 0);
1867                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1868                         /* 1510 DMA requires the bottom address to be 2 more
1869                          * than the actual last memory access location. */
1870                         if (omap_dma_in_1510_mode() &&
1871                             lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1872                                 bottom += 2;
1873                         ei = PIXSTEP(0, 0, 1, 0);
1874                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1875                 } else {
1876                         top = PIXADDR(lcd_dma.xres - 1, 0);
1877                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1878                         ei = PIXSTEP(1, 0, 0, 0);
1879                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1880                 }
1881                 en = lcd_dma.xres;
1882                 fn = lcd_dma.yres;
1883                 break;
1884         case 90:
1885                 if (!lcd_dma.mirror) {
1886                         top = PIXADDR(0, lcd_dma.yres - 1);
1887                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1888                         ei = PIXSTEP(0, 1, 0, 0);
1889                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1890                 } else {
1891                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1892                         bottom = PIXADDR(0, 0);
1893                         ei = PIXSTEP(0, 1, 0, 0);
1894                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1895                 }
1896                 en = lcd_dma.yres;
1897                 fn = lcd_dma.xres;
1898                 break;
1899         case 180:
1900                 if (!lcd_dma.mirror) {
1901                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1902                         bottom = PIXADDR(0, 0);
1903                         ei = PIXSTEP(1, 0, 0, 0);
1904                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1905                 } else {
1906                         top = PIXADDR(0, lcd_dma.yres - 1);
1907                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
1908                         ei = PIXSTEP(0, 0, 1, 0);
1909                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1910                 }
1911                 en = lcd_dma.xres;
1912                 fn = lcd_dma.yres;
1913                 break;
1914         case 270:
1915                 if (!lcd_dma.mirror) {
1916                         top = PIXADDR(lcd_dma.xres - 1, 0);
1917                         bottom = PIXADDR(0, lcd_dma.yres - 1);
1918                         ei = PIXSTEP(0, 0, 0, 1);
1919                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1920                 } else {
1921                         top = PIXADDR(0, 0);
1922                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1923                         ei = PIXSTEP(0, 0, 0, 1);
1924                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1925                 }
1926                 en = lcd_dma.yres;
1927                 fn = lcd_dma.xres;
1928                 break;
1929         default:
1930                 BUG();
1931                 return; /* Suppress warning about uninitialized vars */
1932         }
1933
1934         if (omap_dma_in_1510_mode()) {
1935                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1936                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1937                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1938                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1939
1940                 return;
1941         }
1942
1943         /* 1610 regs */
1944         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1945         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1946         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1947         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1948
1949         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1950         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1951
1952         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1953         w &= ~0x03;
1954         w |= lcd_dma.data_type;
1955         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1956
1957         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1958         /* Always set the source port as SDRAM for now*/
1959         w &= ~(0x03 << 6);
1960         if (lcd_dma.callback != NULL)
1961                 w |= 1 << 1;            /* Block interrupt enable */
1962         else
1963                 w &= ~(1 << 1);
1964         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1965
1966         if (!(lcd_dma.rotate || lcd_dma.mirror ||
1967               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1968                 return;
1969
1970         w = omap_readw(OMAP1610_DMA_LCD_CCR);
1971         /* Set the double-indexed addressing mode */
1972         w |= (0x03 << 12);
1973         omap_writew(w, OMAP1610_DMA_LCD_CCR);
1974
1975         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1976         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1977         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1978 }
1979
1980 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1981 {
1982         u16 w;
1983
1984         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1985         if (unlikely(!(w & (1 << 3)))) {
1986                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1987                 return IRQ_NONE;
1988         }
1989         /* Ack the IRQ */
1990         w |= (1 << 3);
1991         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1992         lcd_dma.active = 0;
1993         if (lcd_dma.callback != NULL)
1994                 lcd_dma.callback(w, lcd_dma.cb_data);
1995
1996         return IRQ_HANDLED;
1997 }
1998
1999 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2000                          void *data)
2001 {
2002         spin_lock_irq(&lcd_dma.lock);
2003         if (lcd_dma.reserved) {
2004                 spin_unlock_irq(&lcd_dma.lock);
2005                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2006                 BUG();
2007                 return -EBUSY;
2008         }
2009         lcd_dma.reserved = 1;
2010         spin_unlock_irq(&lcd_dma.lock);
2011         lcd_dma.callback = callback;
2012         lcd_dma.cb_data = data;
2013         lcd_dma.active = 0;
2014         lcd_dma.single_transfer = 0;
2015         lcd_dma.rotate = 0;
2016         lcd_dma.vxres = 0;
2017         lcd_dma.mirror = 0;
2018         lcd_dma.xscale = 0;
2019         lcd_dma.yscale = 0;
2020         lcd_dma.ext_ctrl = 0;
2021         lcd_dma.src_port = 0;
2022
2023         return 0;
2024 }
2025
2026 void omap_free_lcd_dma(void)
2027 {
2028         spin_lock(&lcd_dma.lock);
2029         if (!lcd_dma.reserved) {
2030                 spin_unlock(&lcd_dma.lock);
2031                 printk(KERN_ERR "LCD DMA is not reserved\n");
2032                 BUG();
2033                 return;
2034         }
2035         if (!enable_1510_mode)
2036                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2037                             OMAP1610_DMA_LCD_CCR);
2038         lcd_dma.reserved = 0;
2039         spin_unlock(&lcd_dma.lock);
2040 }
2041
2042 void omap_enable_lcd_dma(void)
2043 {
2044         u16 w;
2045
2046         /* Set the Enable bit only if an external controller is
2047          * connected. Otherwise the OMAP internal controller will
2048          * start the transfer when it gets enabled.
2049          */
2050         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2051                 return;
2052
2053         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2054         w |= 1 << 8;
2055         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2056
2057         lcd_dma.active = 1;
2058
2059         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2060         w |= 1 << 7;
2061         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2062 }
2063
2064 void omap_setup_lcd_dma(void)
2065 {
2066         BUG_ON(lcd_dma.active);
2067         if (!enable_1510_mode) {
2068                 /* Set some reasonable defaults */
2069                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2070                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2071                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2072         }
2073         set_b1_regs();
2074         if (!enable_1510_mode) {
2075                 u16 w;
2076
2077                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2078                 /* If DMA was already active set the end_prog bit to have
2079                  * the programmed register set loaded into the active
2080                  * register set.
2081                  */
2082                 w |= 1 << 11;           /* End_prog */
2083                 if (!lcd_dma.single_transfer)
2084                         w |= (3 << 8);  /* Auto_init, repeat */
2085                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2086         }
2087 }
2088
2089 void omap_stop_lcd_dma(void)
2090 {
2091         u16 w;
2092
2093         lcd_dma.active = 0;
2094         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2095                 return;
2096
2097         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2098         w &= ~(1 << 7);
2099         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2100
2101         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2102         w &= ~(1 << 8);
2103         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2104 }
2105
2106 /*----------------------------------------------------------------------------*/
2107
2108 static int __init omap_init_dma(void)
2109 {
2110         int ch, r;
2111
2112         if (cpu_class_is_omap1())
2113                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2114         else
2115                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2116
2117         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2118                                 GFP_KERNEL);
2119         if (!dma_chan)
2120                 return -ENOMEM;
2121
2122         if (cpu_class_is_omap2()) {
2123                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2124                                                 dma_lch_count, GFP_KERNEL);
2125                 if (!dma_linked_lch) {
2126                         kfree(dma_chan);
2127                         return -ENOMEM;
2128                 }
2129         }
2130
2131         if (cpu_is_omap15xx()) {
2132                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2133                 dma_chan_count = 9;
2134                 enable_1510_mode = 1;
2135         } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2136                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2137                        omap_readw(OMAP_DMA_HW_ID));
2138                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2139                        (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
2140                        omap_readw(OMAP_DMA_CAPS_0_L),
2141                        (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
2142                        omap_readw(OMAP_DMA_CAPS_1_L),
2143                        omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
2144                        omap_readw(OMAP_DMA_CAPS_4));
2145                 if (!enable_1510_mode) {
2146                         u16 w;
2147
2148                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2149                         w = omap_readw(OMAP_DMA_GSCR);
2150                         w |= 1 << 3;
2151                         omap_writew(w, OMAP_DMA_GSCR);
2152                         dma_chan_count = 16;
2153                 } else
2154                         dma_chan_count = 9;
2155                 if (cpu_is_omap16xx()) {
2156                         u16 w;
2157
2158                         /* this would prevent OMAP sleep */
2159                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2160                         w &= ~(1 << 8);
2161                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2162                 }
2163         } else if (cpu_class_is_omap2()) {
2164                 u8 revision = omap_readb(OMAP_DMA4_REVISION);
2165                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2166                        revision >> 4, revision & 0xf);
2167                 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2168         } else {
2169                 dma_chan_count = 0;
2170                 return 0;
2171         }
2172
2173         spin_lock_init(&lcd_dma.lock);
2174         spin_lock_init(&dma_chan_lock);
2175
2176         for (ch = 0; ch < dma_chan_count; ch++) {
2177                 omap_clear_dma(ch);
2178                 dma_chan[ch].dev_id = -1;
2179                 dma_chan[ch].next_lch = -1;
2180
2181                 if (ch >= 6 && enable_1510_mode)
2182                         continue;
2183
2184                 if (cpu_class_is_omap1()) {
2185                         /* request_irq() doesn't like dev_id (ie. ch) being
2186                          * zero, so we have to kludge around this. */
2187                         r = request_irq(omap1_dma_irq[ch],
2188                                         omap1_dma_irq_handler, 0, "DMA",
2189                                         (void *) (ch + 1));
2190                         if (r != 0) {
2191                                 int i;
2192
2193                                 printk(KERN_ERR "unable to request IRQ %d "
2194                                        "for DMA (error %d)\n",
2195                                        omap1_dma_irq[ch], r);
2196                                 for (i = 0; i < ch; i++)
2197                                         free_irq(omap1_dma_irq[i],
2198                                                  (void *) (i + 1));
2199                                 return r;
2200                         }
2201                 }
2202         }
2203
2204         if (cpu_is_omap2430() || cpu_is_omap34xx())
2205                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2206                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2207
2208         if (cpu_class_is_omap2())
2209                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2210
2211         /* FIXME: Update LCD DMA to work on 24xx */
2212         if (cpu_class_is_omap1()) {
2213                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2214                                 "LCD DMA", NULL);
2215                 if (r != 0) {
2216                         int i;
2217
2218                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2219                                "(error %d)\n", r);
2220                         for (i = 0; i < dma_chan_count; i++)
2221                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2222                         return r;
2223                 }
2224         }
2225
2226         return 0;
2227 }
2228
2229 arch_initcall(omap_init_dma);
2230
2231 EXPORT_SYMBOL(omap_get_dma_src_pos);
2232 EXPORT_SYMBOL(omap_get_dma_dst_pos);
2233 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2234 EXPORT_SYMBOL(omap_clear_dma);
2235 EXPORT_SYMBOL(omap_set_dma_priority);
2236 EXPORT_SYMBOL(omap_request_dma);
2237 EXPORT_SYMBOL(omap_free_dma);
2238 EXPORT_SYMBOL(omap_start_dma);
2239 EXPORT_SYMBOL(omap_stop_dma);
2240 EXPORT_SYMBOL(omap_set_dma_callback);
2241 EXPORT_SYMBOL(omap_enable_dma_irq);
2242 EXPORT_SYMBOL(omap_disable_dma_irq);
2243
2244 EXPORT_SYMBOL(omap_set_dma_transfer_params);
2245 EXPORT_SYMBOL(omap_set_dma_color_mode);
2246 EXPORT_SYMBOL(omap_set_dma_write_mode);
2247
2248 EXPORT_SYMBOL(omap_set_dma_src_params);
2249 EXPORT_SYMBOL(omap_set_dma_src_index);
2250 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2251 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2252
2253 EXPORT_SYMBOL(omap_set_dma_dest_params);
2254 EXPORT_SYMBOL(omap_set_dma_dest_index);
2255 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2256 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2257
2258 EXPORT_SYMBOL(omap_set_dma_params);
2259
2260 EXPORT_SYMBOL(omap_dma_link_lch);
2261 EXPORT_SYMBOL(omap_dma_unlink_lch);
2262
2263 EXPORT_SYMBOL(omap_request_lcd_dma);
2264 EXPORT_SYMBOL(omap_free_lcd_dma);
2265 EXPORT_SYMBOL(omap_enable_lcd_dma);
2266 EXPORT_SYMBOL(omap_setup_lcd_dma);
2267 EXPORT_SYMBOL(omap_stop_lcd_dma);
2268 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2269 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2270 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2271 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2272 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2273 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2274 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2275