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   1 /*
   2  * linux/arch/arm/plat-omap/dma.c
   3  *
   4  * Copyright (C) 2003 - 2008 Nokia Corporation
   5  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   7  * Graphics DMA and LCD DMA graphics tranformations
   8  * by Imre Deak <imre.deak@nokia.com>
   9  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  10  * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Support functions for the OMAP internal DMA channels.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  *
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/sched.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/io.h>
  29
  30 #include <asm/system.h>
  31 #include <mach/hardware.h>
  32 #include <mach/dma.h>
  33
  34 #include <mach/tc.h>
  35
  36 #undef DEBUG
  37
  38 #ifndef CONFIG_ARCH_OMAP1
  39 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
  40         DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
  41 };
  42
  43 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
  44 #endif
  45
  46 #define OMAP_DMA_ACTIVE                 0x01
  47 #define OMAP_DMA_CCR_EN                 (1 << 7)
  48 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
  49
  50 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
  51
  52 static int enable_1510_mode;
  53
  54 struct omap_dma_lch {
  55         int next_lch;
  56         int dev_id;
  57         u16 saved_csr;
  58         u16 enabled_irqs;
  59         const char *dev_name;
  60         void (*callback)(int lch, u16 ch_status, void *data);
  61         void *data;
  62
  63 #ifndef CONFIG_ARCH_OMAP1
  64         /* required for Dynamic chaining */
  65         int prev_linked_ch;
  66         int next_linked_ch;
  67         int state;
  68         int chain_id;
  69
  70         int status;
  71 #endif
  72         long flags;
  73 };
  74
  75 struct dma_link_info {
  76         int *linked_dmach_q;
  77         int no_of_lchs_linked;
  78
  79         int q_count;
  80         int q_tail;
  81         int q_head;
  82
  83         int chain_state;
  84         int chain_mode;
  85
  86 };
  87
  88 static struct dma_link_info *dma_linked_lch;
  89
  90 #ifndef CONFIG_ARCH_OMAP1
  91
  92 /* Chain handling macros */
  93 #define OMAP_DMA_CHAIN_QINIT(chain_id)                                  \
  94         do {                                                            \
  95                 dma_linked_lch[chain_id].q_head =                       \
  96                 dma_linked_lch[chain_id].q_tail =                       \
  97                 dma_linked_lch[chain_id].q_count = 0;                   \
  98         } while (0)
  99 #define OMAP_DMA_CHAIN_QFULL(chain_id)                                  \
 100                 (dma_linked_lch[chain_id].no_of_lchs_linked ==          \
 101                 dma_linked_lch[chain_id].q_count)
 102 #define OMAP_DMA_CHAIN_QLAST(chain_id)                                  \
 103         do {                                                            \
 104                 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) ==      \
 105                 dma_linked_lch[chain_id].q_count)                       \
 106         } while (0)
 107 #define OMAP_DMA_CHAIN_QEMPTY(chain_id)                                 \
 108                 (0 == dma_linked_lch[chain_id].q_count)
 109 #define __OMAP_DMA_CHAIN_INCQ(end)                                      \
 110         ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
 111 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id)                               \
 112         do {                                                            \
 113                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
 114                 dma_linked_lch[chain_id].q_count--;                     \
 115         } while (0)
 116
 117 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id)                               \
 118         do {                                                            \
 119                 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
 120                 dma_linked_lch[chain_id].q_count++; \
 121         } while (0)
 122 #endif
 123
 124 static int dma_lch_count;
 125 static int dma_chan_count;
 126 static int omap_dma_reserve_channels;
 127
 128 static spinlock_t dma_chan_lock;
 129 static struct omap_dma_lch *dma_chan;
 130 static void __iomem *omap_dma_base;
 131
 132 static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
 133         INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
 134         INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
 135         INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
 136         INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
 137         INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
 138 };
 139
 140 static inline void disable_lnk(int lch);
 141 static void omap_disable_channel_irq(int lch);
 142 static inline void omap_enable_channel_irq(int lch);
 143
 144 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
 145                                                 __func__);
 146
 147 #define dma_read(reg)                                                   \
 148 ({                                                                      \
 149         u32 __val;                                                      \
 150         if (cpu_class_is_omap1())                                       \
 151                 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
 152         else                                                            \
 153                 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
 154         __val;                                                          \
 155 })
 156
 157 #define dma_write(val, reg)                                             \
 158 ({                                                                      \
 159         if (cpu_class_is_omap1())                                       \
 160                 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
 161         else                                                            \
 162                 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
 163 })
 164
 165 #ifdef CONFIG_ARCH_OMAP15XX
 166 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 167 int omap_dma_in_1510_mode(void)
 168 {
 169         return enable_1510_mode;
 170 }
 171 #else
 172 #define omap_dma_in_1510_mode()         0
 173 #endif
 174
 175 #ifdef CONFIG_ARCH_OMAP1
 176 static inline int get_gdma_dev(int req)
 177 {
 178         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 179         int shift = ((req - 1) % 5) * 6;
 180
 181         return ((omap_readl(reg) >> shift) & 0x3f) + 1;
 182 }
 183
 184 static inline void set_gdma_dev(int req, int dev)
 185 {
 186         u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
 187         int shift = ((req - 1) % 5) * 6;
 188         u32 l;
 189
 190         l = omap_readl(reg);
 191         l &= ~(0x3f << shift);
 192         l |= (dev - 1) << shift;
 193         omap_writel(l, reg);
 194 }
 195 #else
 196 #define set_gdma_dev(req, dev)  do {} while (0)
 197 #endif
 198
 199 /* Omap1 only */
 200 static void clear_lch_regs(int lch)
 201 {
 202         int i;
 203         void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
 204
 205         for (i = 0; i < 0x2c; i += 2)
 206                 __raw_writew(0, lch_base + i);
 207 }
 208
 209 void omap_set_dma_priority(int lch, int dst_port, int priority)
 210 {
 211         unsigned long reg;
 212         u32 l;
 213
 214         if (cpu_class_is_omap1()) {
 215                 switch (dst_port) {
 216                 case OMAP_DMA_PORT_OCP_T1:      /* FFFECC00 */
 217                         reg = OMAP_TC_OCPT1_PRIOR;
 218                         break;
 219                 case OMAP_DMA_PORT_OCP_T2:      /* FFFECCD0 */
 220                         reg = OMAP_TC_OCPT2_PRIOR;
 221                         break;
 222                 case OMAP_DMA_PORT_EMIFF:       /* FFFECC08 */
 223                         reg = OMAP_TC_EMIFF_PRIOR;
 224                         break;
 225                 case OMAP_DMA_PORT_EMIFS:       /* FFFECC04 */
 226                         reg = OMAP_TC_EMIFS_PRIOR;
 227                         break;
 228                 default:
 229                         BUG();
 230                         return;
 231                 }
 232                 l = omap_readl(reg);
 233                 l &= ~(0xf << 8);
 234                 l |= (priority & 0xf) << 8;
 235                 omap_writel(l, reg);
 236         }
 237
 238         if (cpu_class_is_omap2()) {
 239                 u32 ccr;
 240
 241                 ccr = dma_read(CCR(lch));
 242                 if (priority)
 243                         ccr |= (1 << 6);
 244                 else
 245                         ccr &= ~(1 << 6);
 246                 dma_write(ccr, CCR(lch));
 247         }
 248 }
 249 EXPORT_SYMBOL(omap_set_dma_priority);
 250
 251 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 252                                   int frame_count, int sync_mode,
 253                                   int dma_trigger, int src_or_dst_synch)
 254 {
 255         u32 l;
 256
 257         l = dma_read(CSDP(lch));
 258         l &= ~0x03;
 259         l |= data_type;
 260         dma_write(l, CSDP(lch));
 261
 262         if (cpu_class_is_omap1()) {
 263                 u16 ccr;
 264
 265                 ccr = dma_read(CCR(lch));
 266                 ccr &= ~(1 << 5);
 267                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
 268                         ccr |= 1 << 5;
 269                 dma_write(ccr, CCR(lch));
 270
 271                 ccr = dma_read(CCR2(lch));
 272                 ccr &= ~(1 << 2);
 273                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
 274                         ccr |= 1 << 2;
 275                 dma_write(ccr, CCR2(lch));
 276         }
 277
 278         if (cpu_class_is_omap2() && dma_trigger) {
 279                 u32 val;
 280
 281                 val = dma_read(CCR(lch));
 282
 283                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
 284                 val &= ~((3 << 19) | 0x1f);
 285                 val |= (dma_trigger & ~0x1f) << 14;
 286                 val |= dma_trigger & 0x1f;
 287
 288                 if (sync_mode & OMAP_DMA_SYNC_FRAME)
 289                         val |= 1 << 5;
 290                 else
 291                         val &= ~(1 << 5);
 292
 293                 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
 294                         val |= 1 << 18;
 295                 else
 296                         val &= ~(1 << 18);
 297
 298                 if (src_or_dst_synch)
 299                         val |= 1 << 24;         /* source synch */
 300                 else
 301                         val &= ~(1 << 24);      /* dest synch */
 302
 303                 dma_write(val, CCR(lch));
 304         }
 305
 306         dma_write(elem_count, CEN(lch));
 307         dma_write(frame_count, CFN(lch));
 308 }
 309 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 310
 311 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
 312 {
 313         BUG_ON(omap_dma_in_1510_mode());
 314
 315         if (cpu_class_is_omap1()) {
 316                 u16 w;
 317
 318                 w = dma_read(CCR2(lch));
 319                 w &= ~0x03;
 320
 321                 switch (mode) {
 322                 case OMAP_DMA_CONSTANT_FILL:
 323                         w |= 0x01;
 324                         break;
 325                 case OMAP_DMA_TRANSPARENT_COPY:
 326                         w |= 0x02;
 327                         break;
 328                 case OMAP_DMA_COLOR_DIS:
 329                         break;
 330                 default:
 331                         BUG();
 332                 }
 333                 dma_write(w, CCR2(lch));
 334
 335                 w = dma_read(LCH_CTRL(lch));
 336                 w &= ~0x0f;
 337                 /* Default is channel type 2D */
 338                 if (mode) {
 339                         dma_write((u16)color, COLOR_L(lch));
 340                         dma_write((u16)(color >> 16), COLOR_U(lch));
 341                         w |= 1;         /* Channel type G */
 342                 }
 343                 dma_write(w, LCH_CTRL(lch));
 344         }
 345
 346         if (cpu_class_is_omap2()) {
 347                 u32 val;
 348
 349                 val = dma_read(CCR(lch));
 350                 val &= ~((1 << 17) | (1 << 16));
 351
 352                 switch (mode) {
 353                 case OMAP_DMA_CONSTANT_FILL:
 354                         val |= 1 << 16;
 355                         break;
 356                 case OMAP_DMA_TRANSPARENT_COPY:
 357                         val |= 1 << 17;
 358                         break;
 359                 case OMAP_DMA_COLOR_DIS:
 360                         break;
 361                 default:
 362                         BUG();
 363                 }
 364                 dma_write(val, CCR(lch));
 365
 366                 color &= 0xffffff;
 367                 dma_write(color, COLOR(lch));
 368         }
 369 }
 370 EXPORT_SYMBOL(omap_set_dma_color_mode);
 371
 372 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
 373 {
 374         if (cpu_class_is_omap2()) {
 375                 u32 csdp;
 376
 377                 csdp = dma_read(CSDP(lch));
 378                 csdp &= ~(0x3 << 16);
 379                 csdp |= (mode << 16);
 380                 dma_write(csdp, CSDP(lch));
 381         }
 382 }
 383 EXPORT_SYMBOL(omap_set_dma_write_mode);
 384
 385 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
 386 {
 387         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
 388                 u32 l;
 389
 390                 l = dma_read(LCH_CTRL(lch));
 391                 l &= ~0x7;
 392                 l |= mode;
 393                 dma_write(l, LCH_CTRL(lch));
 394         }
 395 }
 396 EXPORT_SYMBOL(omap_set_dma_channel_mode);
 397
 398 /* Note that src_port is only for omap1 */
 399 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 400                              unsigned long src_start,
 401                              int src_ei, int src_fi)
 402 {
 403         u32 l;
 404
 405         if (cpu_class_is_omap1()) {
 406                 u16 w;
 407
 408                 w = dma_read(CSDP(lch));
 409                 w &= ~(0x1f << 2);
 410                 w |= src_port << 2;
 411                 dma_write(w, CSDP(lch));
 412         }
 413
 414         l = dma_read(CCR(lch));
 415         l &= ~(0x03 << 12);
 416         l |= src_amode << 12;
 417         dma_write(l, CCR(lch));
 418
 419         if (cpu_class_is_omap1()) {
 420                 dma_write(src_start >> 16, CSSA_U(lch));
 421                 dma_write((u16)src_start, CSSA_L(lch));
 422         }
 423
 424         if (cpu_class_is_omap2())
 425                 dma_write(src_start, CSSA(lch));
 426
 427         dma_write(src_ei, CSEI(lch));
 428         dma_write(src_fi, CSFI(lch));
 429 }
 430 EXPORT_SYMBOL(omap_set_dma_src_params);
 431
 432 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
 433 {
 434         omap_set_dma_transfer_params(lch, params->data_type,
 435                                      params->elem_count, params->frame_count,
 436                                      params->sync_mode, params->trigger,
 437                                      params->src_or_dst_synch);
 438         omap_set_dma_src_params(lch, params->src_port,
 439                                 params->src_amode, params->src_start,
 440                                 params->src_ei, params->src_fi);
 441
 442         omap_set_dma_dest_params(lch, params->dst_port,
 443                                  params->dst_amode, params->dst_start,
 444                                  params->dst_ei, params->dst_fi);
 445         if (params->read_prio || params->write_prio)
 446                 omap_dma_set_prio_lch(lch, params->read_prio,
 447                                       params->write_prio);
 448 }
 449 EXPORT_SYMBOL(omap_set_dma_params);
 450
 451 void omap_set_dma_src_index(int lch, int eidx, int fidx)
 452 {
 453         if (cpu_class_is_omap2())
 454                 return;
 455
 456         dma_write(eidx, CSEI(lch));
 457         dma_write(fidx, CSFI(lch));
 458 }
 459 EXPORT_SYMBOL(omap_set_dma_src_index);
 460
 461 void omap_set_dma_src_data_pack(int lch, int enable)
 462 {
 463         u32 l;
 464
 465         l = dma_read(CSDP(lch));
 466         l &= ~(1 << 6);
 467         if (enable)
 468                 l |= (1 << 6);
 469         dma_write(l, CSDP(lch));
 470 }
 471 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 472
 473 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 474 {
 475         unsigned int burst = 0;
 476         u32 l;
 477
 478         l = dma_read(CSDP(lch));
 479         l &= ~(0x03 << 7);
 480
 481         switch (burst_mode) {
 482         case OMAP_DMA_DATA_BURST_DIS:
 483                 break;
 484         case OMAP_DMA_DATA_BURST_4:
 485                 if (cpu_class_is_omap2())
 486                         burst = 0x1;
 487                 else
 488                         burst = 0x2;
 489                 break;
 490         case OMAP_DMA_DATA_BURST_8:
 491                 if (cpu_class_is_omap2()) {
 492                         burst = 0x2;
 493                         break;
 494                 }
 495                 /* not supported by current hardware on OMAP1
 496                  * w |= (0x03 << 7);
 497                  * fall through
 498                  */
 499         case OMAP_DMA_DATA_BURST_16:
 500                 if (cpu_class_is_omap2()) {
 501                         burst = 0x3;
 502                         break;
 503                 }
 504                 /* OMAP1 don't support burst 16
 505                  * fall through
 506                  */
 507         default:
 508                 BUG();
 509         }
 510
 511         l |= (burst << 7);
 512         dma_write(l, CSDP(lch));
 513 }
 514 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 515
 516 /* Note that dest_port is only for OMAP1 */
 517 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 518                               unsigned long dest_start,
 519                               int dst_ei, int dst_fi)
 520 {
 521         u32 l;
 522
 523         if (cpu_class_is_omap1()) {
 524                 l = dma_read(CSDP(lch));
 525                 l &= ~(0x1f << 9);
 526                 l |= dest_port << 9;
 527                 dma_write(l, CSDP(lch));
 528         }
 529
 530         l = dma_read(CCR(lch));
 531         l &= ~(0x03 << 14);
 532         l |= dest_amode << 14;
 533         dma_write(l, CCR(lch));
 534
 535         if (cpu_class_is_omap1()) {
 536                 dma_write(dest_start >> 16, CDSA_U(lch));
 537                 dma_write(dest_start, CDSA_L(lch));
 538         }
 539
 540         if (cpu_class_is_omap2())
 541                 dma_write(dest_start, CDSA(lch));
 542
 543         dma_write(dst_ei, CDEI(lch));
 544         dma_write(dst_fi, CDFI(lch));
 545 }
 546 EXPORT_SYMBOL(omap_set_dma_dest_params);
 547
 548 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
 549 {
 550         if (cpu_class_is_omap2())
 551                 return;
 552
 553         dma_write(eidx, CDEI(lch));
 554         dma_write(fidx, CDFI(lch));
 555 }
 556 EXPORT_SYMBOL(omap_set_dma_dest_index);
 557
 558 void omap_set_dma_dest_data_pack(int lch, int enable)
 559 {
 560         u32 l;
 561
 562         l = dma_read(CSDP(lch));
 563         l &= ~(1 << 13);
 564         if (enable)
 565                 l |= 1 << 13;
 566         dma_write(l, CSDP(lch));
 567 }
 568 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 569
 570 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
 571 {
 572         unsigned int burst = 0;
 573         u32 l;
 574
 575         l = dma_read(CSDP(lch));
 576         l &= ~(0x03 << 14);
 577
 578         switch (burst_mode) {
 579         case OMAP_DMA_DATA_BURST_DIS:
 580                 break;
 581         case OMAP_DMA_DATA_BURST_4:
 582                 if (cpu_class_is_omap2())
 583                         burst = 0x1;
 584                 else
 585                         burst = 0x2;
 586                 break;
 587         case OMAP_DMA_DATA_BURST_8:
 588                 if (cpu_class_is_omap2())
 589                         burst = 0x2;
 590                 else
 591                         burst = 0x3;
 592                 break;
 593         case OMAP_DMA_DATA_BURST_16:
 594                 if (cpu_class_is_omap2()) {
 595                         burst = 0x3;
 596                         break;
 597                 }
 598                 /* OMAP1 don't support burst 16
 599                  * fall through
 600                  */
 601         default:
 602                 printk(KERN_ERR "Invalid DMA burst mode\n");
 603                 BUG();
 604                 return;
 605         }
 606         l |= (burst << 14);
 607         dma_write(l, CSDP(lch));
 608 }
 609 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 610
 611 static inline void omap_enable_channel_irq(int lch)
 612 {
 613         u32 status;
 614
 615         /* Clear CSR */
 616         if (cpu_class_is_omap1())
 617                 status = dma_read(CSR(lch));
 618         else if (cpu_class_is_omap2())
 619                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 620
 621         /* Enable some nice interrupts. */
 622         dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
 623 }
 624
 625 static void omap_disable_channel_irq(int lch)
 626 {
 627         if (cpu_class_is_omap2())
 628                 dma_write(0, CICR(lch));
 629 }
 630
 631 void omap_enable_dma_irq(int lch, u16 bits)
 632 {
 633         dma_chan[lch].enabled_irqs |= bits;
 634 }
 635 EXPORT_SYMBOL(omap_enable_dma_irq);
 636
 637 void omap_disable_dma_irq(int lch, u16 bits)
 638 {
 639         dma_chan[lch].enabled_irqs &= ~bits;
 640 }
 641 EXPORT_SYMBOL(omap_disable_dma_irq);
 642
 643 static inline void enable_lnk(int lch)
 644 {
 645         u32 l;
 646
 647         l = dma_read(CLNK_CTRL(lch));
 648
 649         if (cpu_class_is_omap1())
 650                 l &= ~(1 << 14);
 651
 652         /* Set the ENABLE_LNK bits */
 653         if (dma_chan[lch].next_lch != -1)
 654                 l = dma_chan[lch].next_lch | (1 << 15);
 655
 656 #ifndef CONFIG_ARCH_OMAP1
 657         if (cpu_class_is_omap2())
 658                 if (dma_chan[lch].next_linked_ch != -1)
 659                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 660 #endif
 661
 662         dma_write(l, CLNK_CTRL(lch));
 663 }
 664
 665 static inline void disable_lnk(int lch)
 666 {
 667         u32 l;
 668
 669         l = dma_read(CLNK_CTRL(lch));
 670
 671         /* Disable interrupts */
 672         if (cpu_class_is_omap1()) {
 673                 dma_write(0, CICR(lch));
 674                 /* Set the STOP_LNK bit */
 675                 l |= 1 << 14;
 676         }
 677
 678         if (cpu_class_is_omap2()) {
 679                 omap_disable_channel_irq(lch);
 680                 /* Clear the ENABLE_LNK bit */
 681                 l &= ~(1 << 15);
 682         }
 683
 684         dma_write(l, CLNK_CTRL(lch));
 685         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 686 }
 687
 688 static inline void omap2_enable_irq_lch(int lch)
 689 {
 690         u32 val;
 691
 692         if (!cpu_class_is_omap2())
 693                 return;
 694
 695         val = dma_read(IRQENABLE_L0);
 696         val |= 1 << lch;
 697         dma_write(val, IRQENABLE_L0);
 698 }
 699
 700 int omap_request_dma(int dev_id, const char *dev_name,
 701                      void (*callback)(int lch, u16 ch_status, void *data),
 702                      void *data, int *dma_ch_out)
 703 {
 704         int ch, free_ch = -1;
 705         unsigned long flags;
 706         struct omap_dma_lch *chan;
 707
 708         spin_lock_irqsave(&dma_chan_lock, flags);
 709         for (ch = 0; ch < dma_chan_count; ch++) {
 710                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
 711                         free_ch = ch;
 712                         if (dev_id == 0)
 713                                 break;
 714                 }
 715         }
 716         if (free_ch == -1) {
 717                 spin_unlock_irqrestore(&dma_chan_lock, flags);
 718                 return -EBUSY;
 719         }
 720         chan = dma_chan + free_ch;
 721         chan->dev_id = dev_id;
 722
 723         if (cpu_class_is_omap1())
 724                 clear_lch_regs(free_ch);
 725
 726         if (cpu_class_is_omap2())
 727                 omap_clear_dma(free_ch);
 728
 729         spin_unlock_irqrestore(&dma_chan_lock, flags);
 730
 731         chan->dev_name = dev_name;
 732         chan->callback = callback;
 733         chan->data = data;
 734         chan->flags = 0;
 735
 736 #ifndef CONFIG_ARCH_OMAP1
 737         if (cpu_class_is_omap2()) {
 738                 chan->chain_id = -1;
 739                 chan->next_linked_ch = -1;
 740         }
 741 #endif
 742
 743         chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
 744
 745         if (cpu_class_is_omap1())
 746                 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
 747         else if (cpu_class_is_omap2())
 748                 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
 749                         OMAP2_DMA_TRANS_ERR_IRQ;
 750
 751         if (cpu_is_omap16xx()) {
 752                 /* If the sync device is set, configure it dynamically. */
 753                 if (dev_id != 0) {
 754                         set_gdma_dev(free_ch + 1, dev_id);
 755                         dev_id = free_ch + 1;
 756                 }
 757                 /*
 758                  * Disable the 1510 compatibility mode and set the sync device
 759                  * id.
 760                  */
 761                 dma_write(dev_id | (1 << 10), CCR(free_ch));
 762         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
 763                 dma_write(dev_id, CCR(free_ch));
 764         }
 765
 766         if (cpu_class_is_omap2()) {
 767                 omap2_enable_irq_lch(free_ch);
 768                 omap_enable_channel_irq(free_ch);
 769                 /* Clear the CSR register and IRQ status register */
 770                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
 771                 dma_write(1 << free_ch, IRQSTATUS_L0);
 772         }
 773
 774         *dma_ch_out = free_ch;
 775
 776         return 0;
 777 }
 778 EXPORT_SYMBOL(omap_request_dma);
 779
 780 void omap_free_dma(int lch)
 781 {
 782         unsigned long flags;
 783
 784         if (dma_chan[lch].dev_id == -1) {
 785                 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
 786                        lch);
 787                 return;
 788         }
 789
 790         if (cpu_class_is_omap1()) {
 791                 /* Disable all DMA interrupts for the channel. */
 792                 dma_write(0, CICR(lch));
 793                 /* Make sure the DMA transfer is stopped. */
 794                 dma_write(0, CCR(lch));
 795         }
 796
 797         if (cpu_class_is_omap2()) {
 798                 u32 val;
 799                 /* Disable interrupts */
 800                 val = dma_read(IRQENABLE_L0);
 801                 val &= ~(1 << lch);
 802                 dma_write(val, IRQENABLE_L0);
 803
 804                 /* Clear the CSR register and IRQ status register */
 805                 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
 806                 dma_write(1 << lch, IRQSTATUS_L0);
 807
 808                 /* Disable all DMA interrupts for the channel. */
 809                 dma_write(0, CICR(lch));
 810
 811                 /* Make sure the DMA transfer is stopped. */
 812                 dma_write(0, CCR(lch));
 813                 omap_clear_dma(lch);
 814         }
 815
 816         spin_lock_irqsave(&dma_chan_lock, flags);
 817         dma_chan[lch].dev_id = -1;
 818         dma_chan[lch].next_lch = -1;
 819         dma_chan[lch].callback = NULL;
 820         spin_unlock_irqrestore(&dma_chan_lock, flags);
 821 }
 822 EXPORT_SYMBOL(omap_free_dma);
 823
 824 /**
 825  * @brief omap_dma_set_global_params : Set global priority settings for dma
 826  *
 827  * @param arb_rate
 828  * @param max_fifo_depth
 829  * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
 830  *                                                  DMA_THREAD_RESERVE_ONET
 831  *                                                  DMA_THREAD_RESERVE_TWOT
 832  *                                                  DMA_THREAD_RESERVE_THREET
 833  */
 834 void
 835 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
 836 {
 837         u32 reg;
 838
 839         if (!cpu_class_is_omap2()) {
 840                 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
 841                 return;
 842         }
 843
 844         if (arb_rate == 0)
 845                 arb_rate = 1;
 846
 847         reg = (arb_rate & 0xff) << 16;
 848         reg |= (0xff & max_fifo_depth);
 849
 850         dma_write(reg, GCR);
 851 }
 852 EXPORT_SYMBOL(omap_dma_set_global_params);
 853
 854 /**
 855  * @brief omap_dma_set_prio_lch : Set channel wise priority settings
 856  *
 857  * @param lch
 858  * @param read_prio - Read priority
 859  * @param write_prio - Write priority
 860  * Both of the above can be set with one of the following values :
 861  *      DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
 862  */
 863 int
 864 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 865                       unsigned char write_prio)
 866 {
 867         u32 l;
 868
 869         if (unlikely((lch < 0 || lch >= dma_lch_count))) {
 870                 printk(KERN_ERR "Invalid channel id\n");
 871                 return -EINVAL;
 872         }
 873         l = dma_read(CCR(lch));
 874         l &= ~((1 << 6) | (1 << 26));
 875         if (cpu_is_omap2430() || cpu_is_omap34xx())
 876                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
 877         else
 878                 l |= ((read_prio & 0x1) << 6);
 879
 880         dma_write(l, CCR(lch));
 881
 882         return 0;
 883 }
 884 EXPORT_SYMBOL(omap_dma_set_prio_lch);
 885
 886 /*
 887  * Clears any DMA state so the DMA engine is ready to restart with new buffers
 888  * through omap_start_dma(). Any buffers in flight are discarded.
 889  */
 890 void omap_clear_dma(int lch)
 891 {
 892         unsigned long flags;
 893
 894         local_irq_save(flags);
 895
 896         if (cpu_class_is_omap1()) {
 897                 u32 l;
 898
 899                 l = dma_read(CCR(lch));
 900                 l &= ~OMAP_DMA_CCR_EN;
 901                 dma_write(l, CCR(lch));
 902
 903                 /* Clear pending interrupts */
 904                 l = dma_read(CSR(lch));
 905         }
 906
 907         if (cpu_class_is_omap2()) {
 908                 int i;
 909                 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
 910                 for (i = 0; i < 0x44; i += 4)
 911                         __raw_writel(0, lch_base + i);
 912         }
 913
 914         local_irq_restore(flags);
 915 }
 916 EXPORT_SYMBOL(omap_clear_dma);
 917
 918 void omap_start_dma(int lch)
 919 {
 920         u32 l;
 921
 922         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 923                 int next_lch, cur_lch;
 924                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 925
 926                 dma_chan_link_map[lch] = 1;
 927                 /* Set the link register of the first channel */
 928                 enable_lnk(lch);
 929
 930                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 931                 cur_lch = dma_chan[lch].next_lch;
 932                 do {
 933                         next_lch = dma_chan[cur_lch].next_lch;
 934
 935                         /* The loop case: we've been here already */
 936                         if (dma_chan_link_map[cur_lch])
 937                                 break;
 938                         /* Mark the current channel */
 939                         dma_chan_link_map[cur_lch] = 1;
 940
 941                         enable_lnk(cur_lch);
 942                         omap_enable_channel_irq(cur_lch);
 943
 944                         cur_lch = next_lch;
 945                 } while (next_lch != -1);
 946         } else if (cpu_class_is_omap2()) {
 947                 /* Errata: Need to write lch even if not using chaining */
 948                 dma_write(lch, CLNK_CTRL(lch));
 949         }
 950
 951         omap_enable_channel_irq(lch);
 952
 953         l = dma_read(CCR(lch));
 954
 955         /*
 956          * Errata: On ES2.0 BUFFERING disable must be set.
 957          * This will always fail on ES1.0
 958          */
 959         if (cpu_is_omap24xx())
 960                 l |= OMAP_DMA_CCR_EN;
 961
 962         l |= OMAP_DMA_CCR_EN;
 963         dma_write(l, CCR(lch));
 964
 965         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 966 }
 967 EXPORT_SYMBOL(omap_start_dma);
 968
 969 void omap_stop_dma(int lch)
 970 {
 971         u32 l;
 972
 973         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
 974                 int next_lch, cur_lch = lch;
 975                 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
 976
 977                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
 978                 do {
 979                         /* The loop case: we've been here already */
 980                         if (dma_chan_link_map[cur_lch])
 981                                 break;
 982                         /* Mark the current channel */
 983                         dma_chan_link_map[cur_lch] = 1;
 984
 985                         disable_lnk(cur_lch);
 986
 987                         next_lch = dma_chan[cur_lch].next_lch;
 988                         cur_lch = next_lch;
 989                 } while (next_lch != -1);
 990
 991                 return;
 992         }
 993
 994         /* Disable all interrupts on the channel */
 995         if (cpu_class_is_omap1())
 996                 dma_write(0, CICR(lch));
 997
 998         l = dma_read(CCR(lch));
 999         l &= ~OMAP_DMA_CCR_EN;
1000         dma_write(l, CCR(lch));
1001
1002         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1003 }
1004 EXPORT_SYMBOL(omap_stop_dma);
1005
1006 /*
1007  * Allows changing the DMA callback function or data. This may be needed if
1008  * the driver shares a single DMA channel for multiple dma triggers.
1009  */
1010 int omap_set_dma_callback(int lch,
1011                           void (*callback)(int lch, u16 ch_status, void *data),
1012                           void *data)
1013 {
1014         unsigned long flags;
1015
1016         if (lch < 0)
1017                 return -ENODEV;
1018
1019         spin_lock_irqsave(&dma_chan_lock, flags);
1020         if (dma_chan[lch].dev_id == -1) {
1021                 printk(KERN_ERR "DMA callback for not set for free channel\n");
1022                 spin_unlock_irqrestore(&dma_chan_lock, flags);
1023                 return -EINVAL;
1024         }
1025         dma_chan[lch].callback = callback;
1026         dma_chan[lch].data = data;
1027         spin_unlock_irqrestore(&dma_chan_lock, flags);
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL(omap_set_dma_callback);
1032
1033 /*
1034  * Returns current physical source address for the given DMA channel.
1035  * If the channel is running the caller must disable interrupts prior calling
1036  * this function and process the returned value before re-enabling interrupt to
1037  * prevent races with the interrupt handler. Note that in continuous mode there
1038  * is a chance for CSSA_L register overflow inbetween the two reads resulting
1039  * in incorrect return value.
1040  */
1041 dma_addr_t omap_get_dma_src_pos(int lch)
1042 {
1043         dma_addr_t offset = 0;
1044
1045         if (cpu_is_omap15xx())
1046                 offset = dma_read(CPC(lch));
1047         else
1048                 offset = dma_read(CSAC(lch));
1049
1050         /*
1051          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1052          * read before the DMA controller finished disabling the channel.
1053          */
1054         if (!cpu_is_omap15xx() && offset == 0)
1055                 offset = dma_read(CSAC(lch));
1056
1057         if (cpu_class_is_omap1())
1058                 offset |= (dma_read(CSSA_U(lch)) << 16);
1059
1060         return offset;
1061 }
1062 EXPORT_SYMBOL(omap_get_dma_src_pos);
1063
1064 /*
1065  * Returns current physical destination address for the given DMA channel.
1066  * If the channel is running the caller must disable interrupts prior calling
1067  * this function and process the returned value before re-enabling interrupt to
1068  * prevent races with the interrupt handler. Note that in continuous mode there
1069  * is a chance for CDSA_L register overflow inbetween the two reads resulting
1070  * in incorrect return value.
1071  */
1072 dma_addr_t omap_get_dma_dst_pos(int lch)
1073 {
1074         dma_addr_t offset = 0;
1075
1076         if (cpu_is_omap15xx())
1077                 offset = dma_read(CPC(lch));
1078         else
1079                 offset = dma_read(CDAC(lch));
1080
1081         /*
1082          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1083          * read before the DMA controller finished disabling the channel.
1084          */
1085         if (!cpu_is_omap15xx() && offset == 0)
1086                 offset = dma_read(CDAC(lch));
1087
1088         if (cpu_class_is_omap1())
1089                 offset |= (dma_read(CDSA_U(lch)) << 16);
1090
1091         return offset;
1092 }
1093 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1094
1095 int omap_get_dma_active_status(int lch)
1096 {
1097         return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
1098 }
1099 EXPORT_SYMBOL(omap_get_dma_active_status);
1100
1101 int omap_dma_running(void)
1102 {
1103         int lch;
1104
1105         /* Check if LCD DMA is running */
1106         if (cpu_is_omap16xx())
1107                 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1108                         return 1;
1109
1110         for (lch = 0; lch < dma_chan_count; lch++)
1111                 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1112                         return 1;
1113
1114         return 0;
1115 }
1116
1117 /*
1118  * lch_queue DMA will start right after lch_head one is finished.
1119  * For this DMA link to start, you still need to start (see omap_start_dma)
1120  * the first one. That will fire up the entire queue.
1121  */
1122 void omap_dma_link_lch(int lch_head, int lch_queue)
1123 {
1124         if (omap_dma_in_1510_mode()) {
1125                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1126                 BUG();
1127                 return;
1128         }
1129
1130         if ((dma_chan[lch_head].dev_id == -1) ||
1131             (dma_chan[lch_queue].dev_id == -1)) {
1132                 printk(KERN_ERR "omap_dma: trying to link "
1133                        "non requested channels\n");
1134                 dump_stack();
1135         }
1136
1137         dma_chan[lch_head].next_lch = lch_queue;
1138 }
1139 EXPORT_SYMBOL(omap_dma_link_lch);
1140
1141 /*
1142  * Once the DMA queue is stopped, we can destroy it.
1143  */
1144 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1145 {
1146         if (omap_dma_in_1510_mode()) {
1147                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1148                 BUG();
1149                 return;
1150         }
1151
1152         if (dma_chan[lch_head].next_lch != lch_queue ||
1153             dma_chan[lch_head].next_lch == -1) {
1154                 printk(KERN_ERR "omap_dma: trying to unlink "
1155                        "non linked channels\n");
1156                 dump_stack();
1157         }
1158
1159         if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1160             (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1161                 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1162                        "before unlinking\n");
1163                 dump_stack();
1164         }
1165
1166         dma_chan[lch_head].next_lch = -1;
1167 }
1168 EXPORT_SYMBOL(omap_dma_unlink_lch);
1169
1170 /*----------------------------------------------------------------------------*/
1171
1172 #ifndef CONFIG_ARCH_OMAP1
1173 /* Create chain of DMA channesls */
1174 static void create_dma_lch_chain(int lch_head, int lch_queue)
1175 {
1176         u32 l;
1177
1178         /* Check if this is the first link in chain */
1179         if (dma_chan[lch_head].next_linked_ch == -1) {
1180                 dma_chan[lch_head].next_linked_ch = lch_queue;
1181                 dma_chan[lch_head].prev_linked_ch = lch_queue;
1182                 dma_chan[lch_queue].next_linked_ch = lch_head;
1183                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1184         }
1185
1186         /* a link exists, link the new channel in circular chain */
1187         else {
1188                 dma_chan[lch_queue].next_linked_ch =
1189                                         dma_chan[lch_head].next_linked_ch;
1190                 dma_chan[lch_queue].prev_linked_ch = lch_head;
1191                 dma_chan[lch_head].next_linked_ch = lch_queue;
1192                 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1193                                         lch_queue;
1194         }
1195
1196         l = dma_read(CLNK_CTRL(lch_head));
1197         l &= ~(0x1f);
1198         l |= lch_queue;
1199         dma_write(l, CLNK_CTRL(lch_head));
1200
1201         l = dma_read(CLNK_CTRL(lch_queue));
1202         l &= ~(0x1f);
1203         l |= (dma_chan[lch_queue].next_linked_ch);
1204         dma_write(l, CLNK_CTRL(lch_queue));
1205 }
1206
1207 /**
1208  * @brief omap_request_dma_chain : Request a chain of DMA channels
1209  *
1210  * @param dev_id - Device id using the dma channel
1211  * @param dev_name - Device name
1212  * @param callback - Call back function
1213  * @chain_id -
1214  * @no_of_chans - Number of channels requested
1215  * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1216  *                                            OMAP_DMA_DYNAMIC_CHAIN
1217  * @params - Channel parameters
1218  *
1219  * @return - Succes : 0
1220  *           Failure: -EINVAL/-ENOMEM
1221  */
1222 int omap_request_dma_chain(int dev_id, const char *dev_name,
1223                            void (*callback) (int chain_id, u16 ch_status,
1224                                              void *data),
1225                            int *chain_id, int no_of_chans, int chain_mode,
1226                            struct omap_dma_channel_params params)
1227 {
1228         int *channels;
1229         int i, err;
1230
1231         /* Is the chain mode valid ? */
1232         if (chain_mode != OMAP_DMA_STATIC_CHAIN
1233                         && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1234                 printk(KERN_ERR "Invalid chain mode requested\n");
1235                 return -EINVAL;
1236         }
1237
1238         if (unlikely((no_of_chans < 1
1239                         || no_of_chans > dma_lch_count))) {
1240                 printk(KERN_ERR "Invalid Number of channels requested\n");
1241                 return -EINVAL;
1242         }
1243
1244         /* Allocate a queue to maintain the status of the channels
1245          * in the chain */
1246         channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1247         if (channels == NULL) {
1248                 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1249                 return -ENOMEM;
1250         }
1251
1252         /* request and reserve DMA channels for the chain */
1253         for (i = 0; i < no_of_chans; i++) {
1254                 err = omap_request_dma(dev_id, dev_name,
1255                                         callback, NULL, &channels[i]);
1256                 if (err < 0) {
1257                         int j;
1258                         for (j = 0; j < i; j++)
1259                                 omap_free_dma(channels[j]);
1260                         kfree(channels);
1261                         printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1262                         return err;
1263                 }
1264                 dma_chan[channels[i]].prev_linked_ch = -1;
1265                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1266
1267                 /*
1268                  * Allowing client drivers to set common parameters now,
1269                  * so that later only relevant (src_start, dest_start
1270                  * and element count) can be set
1271                  */
1272                 omap_set_dma_params(channels[i], &params);
1273         }
1274
1275         *chain_id = channels[0];
1276         dma_linked_lch[*chain_id].linked_dmach_q = channels;
1277         dma_linked_lch[*chain_id].chain_mode = chain_mode;
1278         dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1279         dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1280
1281         for (i = 0; i < no_of_chans; i++)
1282                 dma_chan[channels[i]].chain_id = *chain_id;
1283
1284         /* Reset the Queue pointers */
1285         OMAP_DMA_CHAIN_QINIT(*chain_id);
1286
1287         /* Set up the chain */
1288         if (no_of_chans == 1)
1289                 create_dma_lch_chain(channels[0], channels[0]);
1290         else {
1291                 for (i = 0; i < (no_of_chans - 1); i++)
1292                         create_dma_lch_chain(channels[i], channels[i + 1]);
1293         }
1294
1295         return 0;
1296 }
1297 EXPORT_SYMBOL(omap_request_dma_chain);
1298
1299 /**
1300  * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1301  * params after setting it. Dont do this while dma is running!!
1302  *
1303  * @param chain_id - Chained logical channel id.
1304  * @param params
1305  *
1306  * @return - Success : 0
1307  *           Failure : -EINVAL
1308  */
1309 int omap_modify_dma_chain_params(int chain_id,
1310                                 struct omap_dma_channel_params params)
1311 {
1312         int *channels;
1313         u32 i;
1314
1315         /* Check for input params */
1316         if (unlikely((chain_id < 0
1317                         || chain_id >= dma_lch_count))) {
1318                 printk(KERN_ERR "Invalid chain id\n");
1319                 return -EINVAL;
1320         }
1321
1322         /* Check if the chain exists */
1323         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1324                 printk(KERN_ERR "Chain doesn't exists\n");
1325                 return -EINVAL;
1326         }
1327         channels = dma_linked_lch[chain_id].linked_dmach_q;
1328
1329         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1330                 /*
1331                  * Allowing client drivers to set common parameters now,
1332                  * so that later only relevant (src_start, dest_start
1333                  * and element count) can be set
1334                  */
1335                 omap_set_dma_params(channels[i], &params);
1336         }
1337
1338         return 0;
1339 }
1340 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1341
1342 /**
1343  * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1344  *
1345  * @param chain_id
1346  *
1347  * @return - Success : 0
1348  *           Failure : -EINVAL
1349  */
1350 int omap_free_dma_chain(int chain_id)
1351 {
1352         int *channels;
1353         u32 i;
1354
1355         /* Check for input params */
1356         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1357                 printk(KERN_ERR "Invalid chain id\n");
1358                 return -EINVAL;
1359         }
1360
1361         /* Check if the chain exists */
1362         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1363                 printk(KERN_ERR "Chain doesn't exists\n");
1364                 return -EINVAL;
1365         }
1366
1367         channels = dma_linked_lch[chain_id].linked_dmach_q;
1368         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1369                 dma_chan[channels[i]].next_linked_ch = -1;
1370                 dma_chan[channels[i]].prev_linked_ch = -1;
1371                 dma_chan[channels[i]].chain_id = -1;
1372                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1373                 omap_free_dma(channels[i]);
1374         }
1375
1376         kfree(channels);
1377
1378         dma_linked_lch[chain_id].linked_dmach_q = NULL;
1379         dma_linked_lch[chain_id].chain_mode = -1;
1380         dma_linked_lch[chain_id].chain_state = -1;
1381
1382         return (0);
1383 }
1384 EXPORT_SYMBOL(omap_free_dma_chain);
1385
1386 /**
1387  * @brief omap_dma_chain_status - Check if the chain is in
1388  * active / inactive state.
1389  * @param chain_id
1390  *
1391  * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1392  *           Failure : -EINVAL
1393  */
1394 int omap_dma_chain_status(int chain_id)
1395 {
1396         /* Check for input params */
1397         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1398                 printk(KERN_ERR "Invalid chain id\n");
1399                 return -EINVAL;
1400         }
1401
1402         /* Check if the chain exists */
1403         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1404                 printk(KERN_ERR "Chain doesn't exists\n");
1405                 return -EINVAL;
1406         }
1407         pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1408                         dma_linked_lch[chain_id].q_count);
1409
1410         if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1411                 return OMAP_DMA_CHAIN_INACTIVE;
1412
1413         return OMAP_DMA_CHAIN_ACTIVE;
1414 }
1415 EXPORT_SYMBOL(omap_dma_chain_status);
1416
1417 /**
1418  * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1419  * set the params and start the transfer.
1420  *
1421  * @param chain_id
1422  * @param src_start - buffer start address
1423  * @param dest_start - Dest address
1424  * @param elem_count
1425  * @param frame_count
1426  * @param callbk_data - channel callback parameter data.
1427  *
1428  * @return  - Success : 0
1429  *            Failure: -EINVAL/-EBUSY
1430  */
1431 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1432                         int elem_count, int frame_count, void *callbk_data)
1433 {
1434         int *channels;
1435         u32 l, lch;
1436         int start_dma = 0;
1437
1438         /*
1439          * if buffer size is less than 1 then there is
1440          * no use of starting the chain
1441          */
1442         if (elem_count < 1) {
1443                 printk(KERN_ERR "Invalid buffer size\n");
1444                 return -EINVAL;
1445         }
1446
1447         /* Check for input params */
1448         if (unlikely((chain_id < 0
1449                         || chain_id >= dma_lch_count))) {
1450                 printk(KERN_ERR "Invalid chain id\n");
1451                 return -EINVAL;
1452         }
1453
1454         /* Check if the chain exists */
1455         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1456                 printk(KERN_ERR "Chain doesn't exist\n");
1457                 return -EINVAL;
1458         }
1459
1460         /* Check if all the channels in chain are in use */
1461         if (OMAP_DMA_CHAIN_QFULL(chain_id))
1462                 return -EBUSY;
1463
1464         /* Frame count may be negative in case of indexed transfers */
1465         channels = dma_linked_lch[chain_id].linked_dmach_q;
1466
1467         /* Get a free channel */
1468         lch = channels[dma_linked_lch[chain_id].q_tail];
1469
1470         /* Store the callback data */
1471         dma_chan[lch].data = callbk_data;
1472
1473         /* Increment the q_tail */
1474         OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1475
1476         /* Set the params to the free channel */
1477         if (src_start != 0)
1478                 dma_write(src_start, CSSA(lch));
1479         if (dest_start != 0)
1480                 dma_write(dest_start, CDSA(lch));
1481
1482         /* Write the buffer size */
1483         dma_write(elem_count, CEN(lch));
1484         dma_write(frame_count, CFN(lch));
1485
1486         /*
1487          * If the chain is dynamically linked,
1488          * then we may have to start the chain if its not active
1489          */
1490         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1491
1492                 /*
1493                  * In Dynamic chain, if the chain is not started,
1494                  * queue the channel
1495                  */
1496                 if (dma_linked_lch[chain_id].chain_state ==
1497                                                 DMA_CHAIN_NOTSTARTED) {
1498                         /* Enable the link in previous channel */
1499                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1500                                                                 DMA_CH_QUEUED)
1501                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1502                         dma_chan[lch].state = DMA_CH_QUEUED;
1503                 }
1504
1505                 /*
1506                  * Chain is already started, make sure its active,
1507                  * if not then start the chain
1508                  */
1509                 else {
1510                         start_dma = 1;
1511
1512                         if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1513                                                         DMA_CH_STARTED) {
1514                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1515                                 dma_chan[lch].state = DMA_CH_QUEUED;
1516                                 start_dma = 0;
1517                                 if (0 == ((1 << 7) & dma_read(
1518                                         CCR(dma_chan[lch].prev_linked_ch)))) {
1519                                         disable_lnk(dma_chan[lch].
1520                                                     prev_linked_ch);
1521                                         pr_debug("\n prev ch is stopped\n");
1522                                         start_dma = 1;
1523                                 }
1524                         }
1525
1526                         else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1527                                                         == DMA_CH_QUEUED) {
1528                                 enable_lnk(dma_chan[lch].prev_linked_ch);
1529                                 dma_chan[lch].state = DMA_CH_QUEUED;
1530                                 start_dma = 0;
1531                         }
1532                         omap_enable_channel_irq(lch);
1533
1534                         l = dma_read(CCR(lch));
1535
1536                         if ((0 == (l & (1 << 24))))
1537                                 l &= ~(1 << 25);
1538                         else
1539                                 l |= (1 << 25);
1540                         if (start_dma == 1) {
1541                                 if (0 == (l & (1 << 7))) {
1542                                         l |= (1 << 7);
1543                                         dma_chan[lch].state = DMA_CH_STARTED;
1544                                         pr_debug("starting %d\n", lch);
1545                                         dma_write(l, CCR(lch));
1546                                 } else
1547                                         start_dma = 0;
1548                         } else {
1549                                 if (0 == (l & (1 << 7)))
1550                                         dma_write(l, CCR(lch));
1551                         }
1552                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1553                 }
1554         }
1555
1556         return 0;
1557 }
1558 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1559
1560 /**
1561  * @brief omap_start_dma_chain_transfers - Start the chain
1562  *
1563  * @param chain_id
1564  *
1565  * @return - Success : 0
1566  *           Failure : -EINVAL/-EBUSY
1567  */
1568 int omap_start_dma_chain_transfers(int chain_id)
1569 {
1570         int *channels;
1571         u32 l, i;
1572
1573         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1574                 printk(KERN_ERR "Invalid chain id\n");
1575                 return -EINVAL;
1576         }
1577
1578         channels = dma_linked_lch[chain_id].linked_dmach_q;
1579
1580         if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1581                 printk(KERN_ERR "Chain is already started\n");
1582                 return -EBUSY;
1583         }
1584
1585         if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1586                 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1587                                                                         i++) {
1588                         enable_lnk(channels[i]);
1589                         omap_enable_channel_irq(channels[i]);
1590                 }
1591         } else {
1592                 omap_enable_channel_irq(channels[0]);
1593         }
1594
1595         l = dma_read(CCR(channels[0]));
1596         l |= (1 << 7);
1597         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1598         dma_chan[channels[0]].state = DMA_CH_STARTED;
1599
1600         if ((0 == (l & (1 << 24))))
1601                 l &= ~(1 << 25);
1602         else
1603                 l |= (1 << 25);
1604         dma_write(l, CCR(channels[0]));
1605
1606         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1607
1608         return 0;
1609 }
1610 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1611
1612 /**
1613  * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1614  *
1615  * @param chain_id
1616  *
1617  * @return - Success : 0
1618  *           Failure : EINVAL
1619  */
1620 int omap_stop_dma_chain_transfers(int chain_id)
1621 {
1622         int *channels;
1623         u32 l, i;
1624         u32 sys_cf;
1625
1626         /* Check for input params */
1627         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1628                 printk(KERN_ERR "Invalid chain id\n");
1629                 return -EINVAL;
1630         }
1631
1632         /* Check if the chain exists */
1633         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1634                 printk(KERN_ERR "Chain doesn't exists\n");
1635                 return -EINVAL;
1636         }
1637         channels = dma_linked_lch[chain_id].linked_dmach_q;
1638
1639         /*
1640          * DMA Errata:
1641          * Special programming model needed to disable DMA before end of block
1642          */
1643         sys_cf = dma_read(OCP_SYSCONFIG);
1644         l = sys_cf;
1645         /* Middle mode reg set no Standby */
1646         l &= ~((1 << 12)|(1 << 13));
1647         dma_write(l, OCP_SYSCONFIG);
1648
1649         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1650
1651                 /* Stop the Channel transmission */
1652                 l = dma_read(CCR(channels[i]));
1653                 l &= ~(1 << 7);
1654                 dma_write(l, CCR(channels[i]));
1655
1656                 /* Disable the link in all the channels */
1657                 disable_lnk(channels[i]);
1658                 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1659
1660         }
1661         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1662
1663         /* Reset the Queue pointers */
1664         OMAP_DMA_CHAIN_QINIT(chain_id);
1665
1666         /* Errata - put in the old value */
1667         dma_write(sys_cf, OCP_SYSCONFIG);
1668
1669         return 0;
1670 }
1671 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1672
1673 /* Get the index of the ongoing DMA in chain */
1674 /**
1675  * @brief omap_get_dma_chain_index - Get the element and frame index
1676  * of the ongoing DMA in chain
1677  *
1678  * @param chain_id
1679  * @param ei - Element index
1680  * @param fi - Frame index
1681  *
1682  * @return - Success : 0
1683  *           Failure : -EINVAL
1684  */
1685 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1686 {
1687         int lch;
1688         int *channels;
1689
1690         /* Check for input params */
1691         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1692                 printk(KERN_ERR "Invalid chain id\n");
1693                 return -EINVAL;
1694         }
1695
1696         /* Check if the chain exists */
1697         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1698                 printk(KERN_ERR "Chain doesn't exists\n");
1699                 return -EINVAL;
1700         }
1701         if ((!ei) || (!fi))
1702                 return -EINVAL;
1703
1704         channels = dma_linked_lch[chain_id].linked_dmach_q;
1705
1706         /* Get the current channel */
1707         lch = channels[dma_linked_lch[chain_id].q_head];
1708
1709         *ei = dma_read(CCEN(lch));
1710         *fi = dma_read(CCFN(lch));
1711
1712         return 0;
1713 }
1714 EXPORT_SYMBOL(omap_get_dma_chain_index);
1715
1716 /**
1717  * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1718  * ongoing DMA in chain
1719  *
1720  * @param chain_id
1721  *
1722  * @return - Success : Destination position
1723  *           Failure : -EINVAL
1724  */
1725 int omap_get_dma_chain_dst_pos(int chain_id)
1726 {
1727         int lch;
1728         int *channels;
1729
1730         /* Check for input params */
1731         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1732                 printk(KERN_ERR "Invalid chain id\n");
1733                 return -EINVAL;
1734         }
1735
1736         /* Check if the chain exists */
1737         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1738                 printk(KERN_ERR "Chain doesn't exists\n");
1739                 return -EINVAL;
1740         }
1741
1742         channels = dma_linked_lch[chain_id].linked_dmach_q;
1743
1744         /* Get the current channel */
1745         lch = channels[dma_linked_lch[chain_id].q_head];
1746
1747         return dma_read(CDAC(lch));
1748 }
1749 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1750
1751 /**
1752  * @brief omap_get_dma_chain_src_pos - Get the source position
1753  * of the ongoing DMA in chain
1754  * @param chain_id
1755  *
1756  * @return - Success : Destination position
1757  *           Failure : -EINVAL
1758  */
1759 int omap_get_dma_chain_src_pos(int chain_id)
1760 {
1761         int lch;
1762         int *channels;
1763
1764         /* Check for input params */
1765         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1766                 printk(KERN_ERR "Invalid chain id\n");
1767                 return -EINVAL;
1768         }
1769
1770         /* Check if the chain exists */
1771         if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1772                 printk(KERN_ERR "Chain doesn't exists\n");
1773                 return -EINVAL;
1774         }
1775
1776         channels = dma_linked_lch[chain_id].linked_dmach_q;
1777
1778         /* Get the current channel */
1779         lch = channels[dma_linked_lch[chain_id].q_head];
1780
1781         return dma_read(CSAC(lch));
1782 }
1783 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1784 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
1785
1786 /*----------------------------------------------------------------------------*/
1787
1788 #ifdef CONFIG_ARCH_OMAP1
1789
1790 static int omap1_dma_handle_ch(int ch)
1791 {
1792         u32 csr;
1793
1794         if (enable_1510_mode && ch >= 6) {
1795                 csr = dma_chan[ch].saved_csr;
1796                 dma_chan[ch].saved_csr = 0;
1797         } else
1798                 csr = dma_read(CSR(ch));
1799         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1800                 dma_chan[ch + 6].saved_csr = csr >> 7;
1801                 csr &= 0x7f;
1802         }
1803         if ((csr & 0x3f) == 0)
1804                 return 0;
1805         if (unlikely(dma_chan[ch].dev_id == -1)) {
1806                 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1807                        "%d (CSR %04x)\n", ch, csr);
1808                 return 0;
1809         }
1810         if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1811                 printk(KERN_WARNING "DMA timeout with device %d\n",
1812                        dma_chan[ch].dev_id);
1813         if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1814                 printk(KERN_WARNING "DMA synchronization event drop occurred "
1815                        "with device %d\n", dma_chan[ch].dev_id);
1816         if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1817                 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1818         if (likely(dma_chan[ch].callback != NULL))
1819                 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1820
1821         return 1;
1822 }
1823
1824 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1825 {
1826         int ch = ((int) dev_id) - 1;
1827         int handled = 0;
1828
1829         for (;;) {
1830                 int handled_now = 0;
1831
1832                 handled_now += omap1_dma_handle_ch(ch);
1833                 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1834                         handled_now += omap1_dma_handle_ch(ch + 6);
1835                 if (!handled_now)
1836                         break;
1837                 handled += handled_now;
1838         }
1839
1840         return handled ? IRQ_HANDLED : IRQ_NONE;
1841 }
1842
1843 #else
1844 #define omap1_dma_irq_handler   NULL
1845 #endif
1846
1847 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1848
1849 static int omap2_dma_handle_ch(int ch)
1850 {
1851         u32 status = dma_read(CSR(ch));
1852
1853         if (!status) {
1854                 if (printk_ratelimit())
1855                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1856                                 ch);
1857                 dma_write(1 << ch, IRQSTATUS_L0);
1858                 return 0;
1859         }
1860         if (unlikely(dma_chan[ch].dev_id == -1)) {
1861                 if (printk_ratelimit())
1862                         printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1863                                         "channel %d\n", status, ch);
1864                 return 0;
1865         }
1866         if (unlikely(status & OMAP_DMA_DROP_IRQ))
1867                 printk(KERN_INFO
1868                        "DMA synchronization event drop occurred with device "
1869                        "%d\n", dma_chan[ch].dev_id);
1870         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1871                 printk(KERN_INFO "DMA transaction error with device %d\n",
1872                        dma_chan[ch].dev_id);
1873                 if (cpu_class_is_omap2()) {
1874                         /* Errata: sDMA Channel is not disabled
1875                          * after a transaction error. So we explicitely
1876                          * disable the channel
1877                          */
1878                         u32 ccr;
1879
1880                         ccr = dma_read(CCR(ch));
1881                         ccr &= ~OMAP_DMA_CCR_EN;
1882                         dma_write(ccr, CCR(ch));
1883                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1884                 }
1885         }
1886         if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1887                 printk(KERN_INFO "DMA secure error with device %d\n",
1888                        dma_chan[ch].dev_id);
1889         if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1890                 printk(KERN_INFO "DMA misaligned error with device %d\n",
1891                        dma_chan[ch].dev_id);
1892
1893         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1894         dma_write(1 << ch, IRQSTATUS_L0);
1895
1896         /* If the ch is not chained then chain_id will be -1 */
1897         if (dma_chan[ch].chain_id != -1) {
1898                 int chain_id = dma_chan[ch].chain_id;
1899                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1900                 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1901                         dma_chan[dma_chan[ch].next_linked_ch].state =
1902                                                         DMA_CH_STARTED;
1903                 if (dma_linked_lch[chain_id].chain_mode ==
1904                                                 OMAP_DMA_DYNAMIC_CHAIN)
1905                         disable_lnk(ch);
1906
1907                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1908                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1909
1910                 status = dma_read(CSR(ch));
1911         }
1912
1913         dma_write(status, CSR(ch));
1914
1915         if (likely(dma_chan[ch].callback != NULL))
1916                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1917
1918         return 0;
1919 }
1920
1921 /* STATUS register count is from 1-32 while our is 0-31 */
1922 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1923 {
1924         u32 val, enable_reg;
1925         int i;
1926
1927         val = dma_read(IRQSTATUS_L0);
1928         if (val == 0) {
1929                 if (printk_ratelimit())
1930                         printk(KERN_WARNING "Spurious DMA IRQ\n");
1931                 return IRQ_HANDLED;
1932         }
1933         enable_reg = dma_read(IRQENABLE_L0);
1934         val &= enable_reg; /* Dispatch only relevant interrupts */
1935         for (i = 0; i < dma_lch_count && val != 0; i++) {
1936                 if (val & 1)
1937                         omap2_dma_handle_ch(i);
1938                 val >>= 1;
1939         }
1940
1941         return IRQ_HANDLED;
1942 }
1943
1944 static struct irqaction omap24xx_dma_irq = {
1945         .name = "DMA",
1946         .handler = omap2_dma_irq_handler,
1947         .flags = IRQF_DISABLED
1948 };
1949
1950 #else
1951 static struct irqaction omap24xx_dma_irq;
1952 #endif
1953
1954 /*----------------------------------------------------------------------------*/
1955
1956 static struct lcd_dma_info {
1957         spinlock_t lock;
1958         int reserved;
1959         void (*callback)(u16 status, void *data);
1960         void *cb_data;
1961
1962         int active;
1963         unsigned long addr, size;
1964         int rotate, data_type, xres, yres;
1965         int vxres;
1966         int mirror;
1967         int xscale, yscale;
1968         int ext_ctrl;
1969         int src_port;
1970         int single_transfer;
1971 } lcd_dma;
1972
1973 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1974                          int data_type)
1975 {
1976         lcd_dma.addr = addr;
1977         lcd_dma.data_type = data_type;
1978         lcd_dma.xres = fb_xres;
1979         lcd_dma.yres = fb_yres;
1980 }
1981 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1982
1983 void omap_set_lcd_dma_src_port(int port)
1984 {
1985         lcd_dma.src_port = port;
1986 }
1987
1988 void omap_set_lcd_dma_ext_controller(int external)
1989 {
1990         lcd_dma.ext_ctrl = external;
1991 }
1992 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1993
1994 void omap_set_lcd_dma_single_transfer(int single)
1995 {
1996         lcd_dma.single_transfer = single;
1997 }
1998 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1999
2000 void omap_set_lcd_dma_b1_rotation(int rotate)
2001 {
2002         if (omap_dma_in_1510_mode()) {
2003                 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2004                 BUG();
2005                 return;
2006         }
2007         lcd_dma.rotate = rotate;
2008 }
2009 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2010
2011 void omap_set_lcd_dma_b1_mirror(int mirror)
2012 {
2013         if (omap_dma_in_1510_mode()) {
2014                 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2015                 BUG();
2016         }
2017         lcd_dma.mirror = mirror;
2018 }
2019 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2020
2021 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2022 {
2023         if (omap_dma_in_1510_mode()) {
2024                 printk(KERN_ERR "DMA virtual resulotion is not supported "
2025                                 "in 1510 mode\n");
2026                 BUG();
2027         }
2028         lcd_dma.vxres = vxres;
2029 }
2030 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2031
2032 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2033 {
2034         if (omap_dma_in_1510_mode()) {
2035                 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2036                 BUG();
2037         }
2038         lcd_dma.xscale = xscale;
2039         lcd_dma.yscale = yscale;
2040 }
2041 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2042
2043 static void set_b1_regs(void)
2044 {
2045         unsigned long top, bottom;
2046         int es;
2047         u16 w;
2048         unsigned long en, fn;
2049         long ei, fi;
2050         unsigned long vxres;
2051         unsigned int xscale, yscale;
2052
2053         switch (lcd_dma.data_type) {
2054         case OMAP_DMA_DATA_TYPE_S8:
2055                 es = 1;
2056                 break;
2057         case OMAP_DMA_DATA_TYPE_S16:
2058                 es = 2;
2059                 break;
2060         case OMAP_DMA_DATA_TYPE_S32:
2061                 es = 4;
2062                 break;
2063         default:
2064                 BUG();
2065                 return;
2066         }
2067
2068         vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2069         xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2070         yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2071         BUG_ON(vxres < lcd_dma.xres);
2072
2073 #define PIXADDR(x, y) (lcd_dma.addr +                                   \
2074                 ((y) * vxres * yscale + (x) * xscale) * es)
2075 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2076
2077         switch (lcd_dma.rotate) {
2078         case 0:
2079                 if (!lcd_dma.mirror) {
2080                         top = PIXADDR(0, 0);
2081                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2082                         /* 1510 DMA requires the bottom address to be 2 more
2083                          * than the actual last memory access location. */
2084                         if (omap_dma_in_1510_mode() &&
2085                                 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2086                                         bottom += 2;
2087                         ei = PIXSTEP(0, 0, 1, 0);
2088                         fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2089                 } else {
2090                         top = PIXADDR(lcd_dma.xres - 1, 0);
2091                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2092                         ei = PIXSTEP(1, 0, 0, 0);
2093                         fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2094                 }
2095                 en = lcd_dma.xres;
2096                 fn = lcd_dma.yres;
2097                 break;
2098         case 90:
2099                 if (!lcd_dma.mirror) {
2100                         top = PIXADDR(0, lcd_dma.yres - 1);
2101                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2102                         ei = PIXSTEP(0, 1, 0, 0);
2103                         fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2104                 } else {
2105                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2106                         bottom = PIXADDR(0, 0);
2107                         ei = PIXSTEP(0, 1, 0, 0);
2108                         fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2109                 }
2110                 en = lcd_dma.yres;
2111                 fn = lcd_dma.xres;
2112                 break;
2113         case 180:
2114                 if (!lcd_dma.mirror) {
2115                         top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2116                         bottom = PIXADDR(0, 0);
2117                         ei = PIXSTEP(1, 0, 0, 0);
2118                         fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2119                 } else {
2120                         top = PIXADDR(0, lcd_dma.yres - 1);
2121                         bottom = PIXADDR(lcd_dma.xres - 1, 0);
2122                         ei = PIXSTEP(0, 0, 1, 0);
2123                         fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2124                 }
2125                 en = lcd_dma.xres;
2126                 fn = lcd_dma.yres;
2127                 break;
2128         case 270:
2129                 if (!lcd_dma.mirror) {
2130                         top = PIXADDR(lcd_dma.xres - 1, 0);
2131                         bottom = PIXADDR(0, lcd_dma.yres - 1);
2132                         ei = PIXSTEP(0, 0, 0, 1);
2133                         fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2134                 } else {
2135                         top = PIXADDR(0, 0);
2136                         bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2137                         ei = PIXSTEP(0, 0, 0, 1);
2138                         fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2139                 }
2140                 en = lcd_dma.yres;
2141                 fn = lcd_dma.xres;
2142                 break;
2143         default:
2144                 BUG();
2145                 return; /* Suppress warning about uninitialized vars */
2146         }
2147
2148         if (omap_dma_in_1510_mode()) {
2149                 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2150                 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2151                 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2152                 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2153
2154                 return;
2155         }
2156
2157         /* 1610 regs */
2158         omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2159         omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2160         omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2161         omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2162
2163         omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2164         omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2165
2166         w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2167         w &= ~0x03;
2168         w |= lcd_dma.data_type;
2169         omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2170
2171         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2172         /* Always set the source port as SDRAM for now*/
2173         w &= ~(0x03 << 6);
2174         if (lcd_dma.callback != NULL)
2175                 w |= 1 << 1;            /* Block interrupt enable */
2176         else
2177                 w &= ~(1 << 1);
2178         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2179
2180         if (!(lcd_dma.rotate || lcd_dma.mirror ||
2181               lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2182                 return;
2183
2184         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2185         /* Set the double-indexed addressing mode */
2186         w |= (0x03 << 12);
2187         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2188
2189         omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2190         omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2191         omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2192 }
2193
2194 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
2195 {
2196         u16 w;
2197
2198         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2199         if (unlikely(!(w & (1 << 3)))) {
2200                 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2201                 return IRQ_NONE;
2202         }
2203         /* Ack the IRQ */
2204         w |= (1 << 3);
2205         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2206         lcd_dma.active = 0;
2207         if (lcd_dma.callback != NULL)
2208                 lcd_dma.callback(w, lcd_dma.cb_data);
2209
2210         return IRQ_HANDLED;
2211 }
2212
2213 int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
2214                          void *data)
2215 {
2216         spin_lock_irq(&lcd_dma.lock);
2217         if (lcd_dma.reserved) {
2218                 spin_unlock_irq(&lcd_dma.lock);
2219                 printk(KERN_ERR "LCD DMA channel already reserved\n");
2220                 BUG();
2221                 return -EBUSY;
2222         }
2223         lcd_dma.reserved = 1;
2224         spin_unlock_irq(&lcd_dma.lock);
2225         lcd_dma.callback = callback;
2226         lcd_dma.cb_data = data;
2227         lcd_dma.active = 0;
2228         lcd_dma.single_transfer = 0;
2229         lcd_dma.rotate = 0;
2230         lcd_dma.vxres = 0;
2231         lcd_dma.mirror = 0;
2232         lcd_dma.xscale = 0;
2233         lcd_dma.yscale = 0;
2234         lcd_dma.ext_ctrl = 0;
2235         lcd_dma.src_port = 0;
2236
2237         return 0;
2238 }
2239 EXPORT_SYMBOL(omap_request_lcd_dma);
2240
2241 void omap_free_lcd_dma(void)
2242 {
2243         spin_lock(&lcd_dma.lock);
2244         if (!lcd_dma.reserved) {
2245                 spin_unlock(&lcd_dma.lock);
2246                 printk(KERN_ERR "LCD DMA is not reserved\n");
2247                 BUG();
2248                 return;
2249         }
2250         if (!enable_1510_mode)
2251                 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2252                             OMAP1610_DMA_LCD_CCR);
2253         lcd_dma.reserved = 0;
2254         spin_unlock(&lcd_dma.lock);
2255 }
2256 EXPORT_SYMBOL(omap_free_lcd_dma);
2257
2258 void omap_enable_lcd_dma(void)
2259 {
2260         u16 w;
2261
2262         /*
2263          * Set the Enable bit only if an external controller is
2264          * connected. Otherwise the OMAP internal controller will
2265          * start the transfer when it gets enabled.
2266          */
2267         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2268                 return;
2269
2270         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2271         w |= 1 << 8;
2272         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2273
2274         lcd_dma.active = 1;
2275
2276         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2277         w |= 1 << 7;
2278         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2279 }
2280 EXPORT_SYMBOL(omap_enable_lcd_dma);
2281
2282 void omap_setup_lcd_dma(void)
2283 {
2284         BUG_ON(lcd_dma.active);
2285         if (!enable_1510_mode) {
2286                 /* Set some reasonable defaults */
2287                 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2288                 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2289                 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2290         }
2291         set_b1_regs();
2292         if (!enable_1510_mode) {
2293                 u16 w;
2294
2295                 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2296                 /*
2297                  * If DMA was already active set the end_prog bit to have
2298                  * the programmed register set loaded into the active
2299                  * register set.
2300                  */
2301                 w |= 1 << 11;           /* End_prog */
2302                 if (!lcd_dma.single_transfer)
2303                         w |= (3 << 8);  /* Auto_init, repeat */
2304                 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2305         }
2306 }
2307 EXPORT_SYMBOL(omap_setup_lcd_dma);
2308
2309 void omap_stop_lcd_dma(void)
2310 {
2311         u16 w;
2312
2313         lcd_dma.active = 0;
2314         if (enable_1510_mode || !lcd_dma.ext_ctrl)
2315                 return;
2316
2317         w = omap_readw(OMAP1610_DMA_LCD_CCR);
2318         w &= ~(1 << 7);
2319         omap_writew(w, OMAP1610_DMA_LCD_CCR);
2320
2321         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2322         w &= ~(1 << 8);
2323         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2324 }
2325 EXPORT_SYMBOL(omap_stop_lcd_dma);
2326
2327 /*----------------------------------------------------------------------------*/
2328
2329 static int __init omap_init_dma(void)
2330 {
2331         int ch, r;
2332
2333         if (cpu_class_is_omap1()) {
2334                 omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
2335                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2336         } else if (cpu_is_omap24xx()) {
2337                 omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
2338                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2339         } else if (cpu_is_omap34xx()) {
2340                 omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
2341                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2342         } else {
2343                 pr_err("DMA init failed for unsupported omap\n");
2344                 return -ENODEV;
2345         }
2346
2347         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2348                         && (omap_dma_reserve_channels <= dma_lch_count))
2349                 dma_lch_count = omap_dma_reserve_channels;
2350
2351         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2352                                 GFP_KERNEL);
2353         if (!dma_chan)
2354                 return -ENOMEM;
2355
2356         if (cpu_class_is_omap2()) {
2357                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2358                                                 dma_lch_count, GFP_KERNEL);
2359                 if (!dma_linked_lch) {
2360                         kfree(dma_chan);
2361                         return -ENOMEM;
2362                 }
2363         }
2364
2365         if (cpu_is_omap15xx()) {
2366                 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2367                 dma_chan_count = 9;
2368                 enable_1510_mode = 1;
2369         } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2370                 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2371                        dma_read(HW_ID));
2372                 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2373                        (dma_read(CAPS_0_U) << 16) |
2374                        dma_read(CAPS_0_L),
2375                        (dma_read(CAPS_1_U) << 16) |
2376                        dma_read(CAPS_1_L),
2377                        dma_read(CAPS_2), dma_read(CAPS_3),
2378                        dma_read(CAPS_4));
2379                 if (!enable_1510_mode) {
2380                         u16 w;
2381
2382                         /* Disable OMAP 3.0/3.1 compatibility mode. */
2383                         w = dma_read(GSCR);
2384                         w |= 1 << 3;
2385                         dma_write(w, GSCR);
2386                         dma_chan_count = 16;
2387                 } else
2388                         dma_chan_count = 9;
2389                 if (cpu_is_omap16xx()) {
2390                         u16 w;
2391
2392                         /* this would prevent OMAP sleep */
2393                         w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2394                         w &= ~(1 << 8);
2395                         omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2396                 }
2397         } else if (cpu_class_is_omap2()) {
2398                 u8 revision = dma_read(REVISION) & 0xff;
2399                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2400                        revision >> 4, revision & 0xf);
2401                 dma_chan_count = dma_lch_count;
2402         } else {
2403                 dma_chan_count = 0;
2404                 return 0;
2405         }
2406
2407         spin_lock_init(&lcd_dma.lock);
2408         spin_lock_init(&dma_chan_lock);
2409
2410         for (ch = 0; ch < dma_chan_count; ch++) {
2411                 omap_clear_dma(ch);
2412                 dma_chan[ch].dev_id = -1;
2413                 dma_chan[ch].next_lch = -1;
2414
2415                 if (ch >= 6 && enable_1510_mode)
2416                         continue;
2417
2418                 if (cpu_class_is_omap1()) {
2419                         /*
2420                          * request_irq() doesn't like dev_id (ie. ch) being
2421                          * zero, so we have to kludge around this.
2422                          */
2423                         r = request_irq(omap1_dma_irq[ch],
2424                                         omap1_dma_irq_handler, 0, "DMA",
2425                                         (void *) (ch + 1));
2426                         if (r != 0) {
2427                                 int i;
2428
2429                                 printk(KERN_ERR "unable to request IRQ %d "
2430                                        "for DMA (error %d)\n",
2431                                        omap1_dma_irq[ch], r);
2432                                 for (i = 0; i < ch; i++)
2433                                         free_irq(omap1_dma_irq[i],
2434                                                  (void *) (i + 1));
2435                                 return r;
2436                         }
2437                 }
2438         }
2439
2440         if (cpu_is_omap2430() || cpu_is_omap34xx())
2441                 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2442                                 DMA_DEFAULT_FIFO_DEPTH, 0);
2443
2444         if (cpu_class_is_omap2())
2445                 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
2446
2447         /* FIXME: Update LCD DMA to work on 24xx */
2448         if (cpu_class_is_omap1()) {
2449                 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2450                                 "LCD DMA", NULL);
2451                 if (r != 0) {
2452                         int i;
2453
2454                         printk(KERN_ERR "unable to request IRQ for LCD DMA "
2455                                "(error %d)\n", r);
2456                         for (i = 0; i < dma_chan_count; i++)
2457                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2458                         return r;
2459                 }
2460         }
2461
2462         return 0;
2463 }
2464
2465 arch_initcall(omap_init_dma);
2466
2467 /*
2468  * Reserve the omap SDMA channels using cmdline bootarg
2469  * "omap_dma_reserve_ch=". The valid range is 1 to 32
2470  */
2471 static int __init omap_dma_cmdline_reserve_ch(char *str)
2472 {
2473         if (get_option(&str, &omap_dma_reserve_channels) != 1)
2474                 omap_dma_reserve_channels = 0;
2475         return 1;
2476 }
2477
2478 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2479
2480