2 * linux/arch/arm/mm/fault-armv.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2002 Russell King
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/vmalloc.h>
17 #include <linux/init.h>
18 #include <linux/pagemap.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cachetype.h>
23 #include <asm/pgtable.h>
24 #include <asm/tlbflush.h>
28 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
31 * We take the easy way out of this problem - we make the
32 * PTE uncacheable. However, we leave the write buffer on.
34 * Note that the pte lock held when calling update_mmu_cache must also
35 * guard the pte (somewhere else in the same mm) that we modify here.
36 * Therefore those configurations which might call adjust_pte (those
37 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
39 static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
40 unsigned long pfn, pte_t *ptep)
46 * If this page is present, it's actually being shared.
48 ret = pte_present(entry);
51 * If this page isn't present, or is already setup to
52 * fault (ie, is old), we can safely ignore any issues.
54 if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
55 flush_cache_page(vma, address, pfn);
56 outer_flush_range((pfn << PAGE_SHIFT),
57 (pfn << PAGE_SHIFT) + PAGE_SIZE);
58 pte_val(entry) &= ~L_PTE_MT_MASK;
59 pte_val(entry) |= shared_pte_mask;
60 set_pte_at(vma->vm_mm, address, ptep, entry);
61 flush_tlb_page(vma, address);
67 static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
76 pgd = pgd_offset(vma->vm_mm, address);
77 if (pgd_none_or_clear_bad(pgd))
80 pmd = pmd_offset(pgd, address);
81 if (pmd_none_or_clear_bad(pmd))
85 * This is called while another page table is mapped, so we
86 * must use the nested version. This also means we need to
87 * open-code the spin-locking.
89 ptl = pte_lockptr(vma->vm_mm, pmd);
90 pte = pte_offset_map_nested(pmd, address);
93 ret = do_adjust_pte(vma, address, pfn, pte);
96 pte_unmap_nested(pte);
102 make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
104 struct mm_struct *mm = vma->vm_mm;
105 struct vm_area_struct *mpnt;
106 struct prio_tree_iter iter;
107 unsigned long offset;
111 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
114 * If we have any shared mappings that are in the same mm
115 * space, then we need to handle them specially to maintain
118 flush_dcache_mmap_lock(mapping);
119 vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
121 * If this VMA is not in our MM, we can ignore it.
122 * Note that we intentionally mask out the VMA
123 * that we are fixing up.
125 if (mpnt->vm_mm != mm || mpnt == vma)
127 if (!(mpnt->vm_flags & VM_MAYSHARE))
129 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
130 aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
132 flush_dcache_mmap_unlock(mapping);
134 adjust_pte(vma, addr, pfn);
136 flush_cache_page(vma, addr, pfn);
140 * Take care of architecture specific things when placing a new PTE into
141 * a page table, or changing an existing PTE. Basically, there are two
142 * things that we need to take care of:
144 * 1. If PG_dcache_dirty is set for the page, we need to ensure
145 * that any cache entries for the kernels virtual memory
146 * range are written back to the page.
147 * 2. If we have multiple shared mappings of the same space in
148 * an object, we need to deal with the cache aliasing issues.
150 * Note that the pte lock will be held.
152 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
155 unsigned long pfn = pte_pfn(*ptep);
156 struct address_space *mapping;
163 * The zero page is never written to, so never has any dirty
164 * cache lines, and therefore never needs to be flushed.
166 page = pfn_to_page(pfn);
167 if (page == ZERO_PAGE(0))
170 mapping = page_mapping(page);
172 if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
173 __flush_dcache_page(mapping, page);
177 make_coherent(mapping, vma, addr, pfn);
178 else if (vma->vm_flags & VM_EXEC)
179 __flush_icache_all();
184 * Check whether the write buffer has physical address aliasing
185 * issues. If it has, we need to avoid them for the case where
186 * we have several shared mappings of the same object in user
189 static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
191 register unsigned long zero = 0, one = 1, val;
205 void __init check_writebuffer_bugs(void)
211 printk(KERN_INFO "CPU: Testing write buffer coherency: ");
213 page = alloc_page(GFP_KERNEL);
215 unsigned long *p1, *p2;
216 pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
217 L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
219 p1 = vmap(&page, 1, VM_IOREMAP, prot);
220 p2 = vmap(&page, 1, VM_IOREMAP, prot);
223 v = check_writebuffer(p1, p2);
224 reason = "enabling work-around";
226 reason = "unable to map memory\n";
233 reason = "unable to grab page\n";
237 printk("failed, %s\n", reason);
238 shared_pte_mask = L_PTE_MT_UNCACHED;