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   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/clocksource.h>
  32 #include <linux/clockchips.h>
  33 #include <linux/cnt32_to_63.h>
  34 #include <linux/io.h>
  35
  36 #include <asm/clkdev.h>
  37 #include <asm/system.h>
  38 #include <asm/irq.h>
  39 #include <asm/leds.h>
  40 #include <asm/hardware/arm_timer.h>
  41 #include <asm/hardware/icst.h>
  42 #include <asm/hardware/vic.h>
  43 #include <asm/mach-types.h>
  44
  45 #include <asm/mach/arch.h>
  46 #include <asm/mach/flash.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/map.h>
  50 #include <mach/clkdev.h>
  51 #include <mach/hardware.h>
  52 #include <mach/platform.h>
  53
  54 #include "core.h"
  55
  56 /*
  57  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  58  * is the (PA >> 12).
  59  *
  60  * Setup a VA for the Versatile Vectored Interrupt Controller.
  61  */
  62 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  63 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  64
  65 static void sic_mask_irq(unsigned int irq)
  66 {
  67         irq -= IRQ_SIC_START;
  68         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  69 }
  70
  71 static void sic_unmask_irq(unsigned int irq)
  72 {
  73         irq -= IRQ_SIC_START;
  74         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  75 }
  76
  77 static struct irq_chip sic_chip = {
  78         .name   = "SIC",
  79         .ack    = sic_mask_irq,
  80         .mask   = sic_mask_irq,
  81         .unmask = sic_unmask_irq,
  82 };
  83
  84 static void
  85 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  86 {
  87         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  88
  89         if (status == 0) {
  90                 do_bad_IRQ(irq, desc);
  91                 return;
  92         }
  93
  94         do {
  95                 irq = ffs(status) - 1;
  96                 status &= ~(1 << irq);
  97
  98                 irq += IRQ_SIC_START;
  99
 100                 generic_handle_irq(irq);
 101         } while (status);
 102 }
 103
 104 #if 1
 105 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 106 #define IRQ_AACI        IRQ_VICSOURCE24
 107 #define IRQ_ETH         IRQ_VICSOURCE25
 108 #define PIC_MASK        0xFFD00000
 109 #else
 110 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 111 #define IRQ_AACI        IRQ_SIC_AACI
 112 #define IRQ_ETH         IRQ_SIC_ETH
 113 #define PIC_MASK        0
 114 #endif
 115
 116 void __init versatile_init_irq(void)
 117 {
 118         unsigned int i;
 119
 120         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 121
 122         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 123
 124         /* Do second interrupt controller */
 125         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 126
 127         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 128                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 129                         set_irq_chip(i, &sic_chip);
 130                         set_irq_handler(i, handle_level_irq);
 131                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 132                 }
 133         }
 134
 135         /*
 136          * Interrupts on secondary controller from 0 to 8 are routed to
 137          * source 31 on PIC.
 138          * Interrupts from 21 to 31 are routed directly to the VIC on
 139          * the corresponding number on primary controller. This is controlled
 140          * by setting PIC_ENABLEx.
 141          */
 142         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 143 }
 144
 145 static struct map_desc versatile_io_desc[] __initdata = {
 146         {
 147                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 148                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE
 151         }, {
 152                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 153                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 154                 .length         = SZ_4K,
 155                 .type           = MT_DEVICE
 156         }, {
 157                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 158                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 159                 .length         = SZ_4K,
 160                 .type           = MT_DEVICE
 161         }, {
 162                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 163                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 164                 .length         = SZ_4K * 9,
 165                 .type           = MT_DEVICE
 166         },
 167 #ifdef CONFIG_MACH_VERSATILE_AB
 168         {
 169                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 170                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 171                 .length         = SZ_4K,
 172                 .type           = MT_DEVICE
 173         }, {
 174                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 175                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 176                 .length         = SZ_64M,
 177                 .type           = MT_DEVICE
 178         },
 179 #endif
 180 #ifdef CONFIG_DEBUG_LL
 181         {
 182                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 183                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 184                 .length         = SZ_4K,
 185                 .type           = MT_DEVICE
 186         },
 187 #endif
 188 #ifdef CONFIG_PCI
 189         {
 190                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 191                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 192                 .length         = SZ_4K,
 193                 .type           = MT_DEVICE
 194         }, {
 195                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 196                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 197                 .length         = VERSATILE_PCI_BASE_SIZE,
 198                 .type           = MT_DEVICE
 199         }, {
 200                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 201                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 202                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 203                 .type           = MT_DEVICE
 204         },
 205 #if 0
 206         {
 207                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 208                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 209                 .length         = SZ_16M,
 210                 .type           = MT_DEVICE
 211         }, {
 212                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 213                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 214                 .length         = SZ_16M,
 215                 .type           = MT_DEVICE
 216         }, {
 217                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 218                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 219                 .length         = SZ_16M,
 220                 .type           = MT_DEVICE
 221         },
 222 #endif
 223 #endif
 224 };
 225
 226 void __init versatile_map_io(void)
 227 {
 228         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 229 }
 230
 231 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 232
 233 /*
 234  * This is the Versatile sched_clock implementation.  This has
 235  * a resolution of 41.7ns, and a maximum value of about 35583 days.
 236  *
 237  * The return value is guaranteed to be monotonic in that range as
 238  * long as there is always less than 89 seconds between successive
 239  * calls to this function.
 240  */
 241 unsigned long long sched_clock(void)
 242 {
 243         unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
 244
 245         /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
 246         v *= 125<<1;
 247         do_div(v, 3<<1);
 248
 249         return v;
 250 }
 251
 252
 253 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 254
 255 static int versatile_flash_init(void)
 256 {
 257         u32 val;
 258
 259         val = __raw_readl(VERSATILE_FLASHCTRL);
 260         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 261         __raw_writel(val, VERSATILE_FLASHCTRL);
 262
 263         return 0;
 264 }
 265
 266 static void versatile_flash_exit(void)
 267 {
 268         u32 val;
 269
 270         val = __raw_readl(VERSATILE_FLASHCTRL);
 271         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 272         __raw_writel(val, VERSATILE_FLASHCTRL);
 273 }
 274
 275 static void versatile_flash_set_vpp(int on)
 276 {
 277         u32 val;
 278
 279         val = __raw_readl(VERSATILE_FLASHCTRL);
 280         if (on)
 281                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 282         else
 283                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 284         __raw_writel(val, VERSATILE_FLASHCTRL);
 285 }
 286
 287 static struct flash_platform_data versatile_flash_data = {
 288         .map_name               = "cfi_probe",
 289         .width                  = 4,
 290         .init                   = versatile_flash_init,
 291         .exit                   = versatile_flash_exit,
 292         .set_vpp                = versatile_flash_set_vpp,
 293 };
 294
 295 static struct resource versatile_flash_resource = {
 296         .start                  = VERSATILE_FLASH_BASE,
 297         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 298         .flags                  = IORESOURCE_MEM,
 299 };
 300
 301 static struct platform_device versatile_flash_device = {
 302         .name                   = "armflash",
 303         .id                     = 0,
 304         .dev                    = {
 305                 .platform_data  = &versatile_flash_data,
 306         },
 307         .num_resources          = 1,
 308         .resource               = &versatile_flash_resource,
 309 };
 310
 311 static struct resource smc91x_resources[] = {
 312         [0] = {
 313                 .start          = VERSATILE_ETH_BASE,
 314                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 315                 .flags          = IORESOURCE_MEM,
 316         },
 317         [1] = {
 318                 .start          = IRQ_ETH,
 319                 .end            = IRQ_ETH,
 320                 .flags          = IORESOURCE_IRQ,
 321         },
 322 };
 323
 324 static struct platform_device smc91x_device = {
 325         .name           = "smc91x",
 326         .id             = 0,
 327         .num_resources  = ARRAY_SIZE(smc91x_resources),
 328         .resource       = smc91x_resources,
 329 };
 330
 331 static struct resource versatile_i2c_resource = {
 332         .start                  = VERSATILE_I2C_BASE,
 333         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 334         .flags                  = IORESOURCE_MEM,
 335 };
 336
 337 static struct platform_device versatile_i2c_device = {
 338         .name                   = "versatile-i2c",
 339         .id                     = 0,
 340         .num_resources          = 1,
 341         .resource               = &versatile_i2c_resource,
 342 };
 343
 344 static struct i2c_board_info versatile_i2c_board_info[] = {
 345         {
 346                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 347         },
 348 };
 349
 350 static int __init versatile_i2c_init(void)
 351 {
 352         return i2c_register_board_info(0, versatile_i2c_board_info,
 353                                        ARRAY_SIZE(versatile_i2c_board_info));
 354 }
 355 arch_initcall(versatile_i2c_init);
 356
 357 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 358
 359 unsigned int mmc_status(struct device *dev)
 360 {
 361         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 362         u32 mask;
 363
 364         if (adev->res.start == VERSATILE_MMCI0_BASE)
 365                 mask = 1;
 366         else
 367                 mask = 2;
 368
 369         return readl(VERSATILE_SYSMCI) & mask;
 370 }
 371
 372 static struct mmci_platform_data mmc0_plat_data = {
 373         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 374         .status         = mmc_status,
 375         .gpio_wp        = -1,
 376         .gpio_cd        = -1,
 377 };
 378
 379 /*
 380  * Clock handling
 381  */
 382 static const struct icst_params versatile_oscvco_params = {
 383         .ref            = 24000000,
 384         .vco_max        = ICST307_VCO_MAX,
 385         .vco_min        = ICST307_VCO_MIN,
 386         .vd_min         = 4 + 8,
 387         .vd_max         = 511 + 8,
 388         .rd_min         = 1 + 2,
 389         .rd_max         = 127 + 2,
 390         .s2div          = icst307_s2div,
 391         .idx2s          = icst307_idx2s,
 392 };
 393
 394 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 395 {
 396         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 397         void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
 398         u32 val;
 399
 400         val = readl(sys + clk->oscoff) & ~0x7ffff;
 401         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 402
 403         writel(0xa05f, sys_lock);
 404         writel(val, sys + clk->oscoff);
 405         writel(0, sys_lock);
 406 }
 407
 408 static struct clk osc4_clk = {
 409         .params = &versatile_oscvco_params,
 410         .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
 411         .setvco = versatile_oscvco_set,
 412 };
 413
 414 /*
 415  * These are fixed clocks.
 416  */
 417 static struct clk ref24_clk = {
 418         .rate   = 24000000,
 419 };
 420
 421 static struct clk_lookup lookups[] = {
 422         {       /* UART0 */
 423                 .dev_id         = "dev:f1",
 424                 .clk            = &ref24_clk,
 425         }, {    /* UART1 */
 426                 .dev_id         = "dev:f2",
 427                 .clk            = &ref24_clk,
 428         }, {    /* UART2 */
 429                 .dev_id         = "dev:f3",
 430                 .clk            = &ref24_clk,
 431         }, {    /* UART3 */
 432                 .dev_id         = "fpga:09",
 433                 .clk            = &ref24_clk,
 434         }, {    /* KMI0 */
 435                 .dev_id         = "fpga:06",
 436                 .clk            = &ref24_clk,
 437         }, {    /* KMI1 */
 438                 .dev_id         = "fpga:07",
 439                 .clk            = &ref24_clk,
 440         }, {    /* MMC0 */
 441                 .dev_id         = "fpga:05",
 442                 .clk            = &ref24_clk,
 443         }, {    /* MMC1 */
 444                 .dev_id         = "fpga:0b",
 445                 .clk            = &ref24_clk,
 446         }, {    /* CLCD */
 447                 .dev_id         = "dev:20",
 448                 .clk            = &osc4_clk,
 449         }
 450 };
 451
 452 /*
 453  * CLCD support.
 454  */
 455 #define SYS_CLCD_MODE_MASK      (3 << 0)
 456 #define SYS_CLCD_MODE_888       (0 << 0)
 457 #define SYS_CLCD_MODE_5551      (1 << 0)
 458 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 459 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 460 #define SYS_CLCD_NLCDIOON       (1 << 2)
 461 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 462 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 463 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 464 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 465 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 466 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 467 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 468 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 469
 470 static struct clcd_panel vga = {
 471         .mode           = {
 472                 .name           = "VGA",
 473                 .refresh        = 60,
 474                 .xres           = 640,
 475                 .yres           = 480,
 476                 .pixclock       = 39721,
 477                 .left_margin    = 40,
 478                 .right_margin   = 24,
 479                 .upper_margin   = 32,
 480                 .lower_margin   = 11,
 481                 .hsync_len      = 96,
 482                 .vsync_len      = 2,
 483                 .sync           = 0,
 484                 .vmode          = FB_VMODE_NONINTERLACED,
 485         },
 486         .width          = -1,
 487         .height         = -1,
 488         .tim2           = TIM2_BCD | TIM2_IPC,
 489         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 490         .bpp            = 16,
 491 };
 492
 493 static struct clcd_panel sanyo_3_8_in = {
 494         .mode           = {
 495                 .name           = "Sanyo QVGA",
 496                 .refresh        = 116,
 497                 .xres           = 320,
 498                 .yres           = 240,
 499                 .pixclock       = 100000,
 500                 .left_margin    = 6,
 501                 .right_margin   = 6,
 502                 .upper_margin   = 5,
 503                 .lower_margin   = 5,
 504                 .hsync_len      = 6,
 505                 .vsync_len      = 6,
 506                 .sync           = 0,
 507                 .vmode          = FB_VMODE_NONINTERLACED,
 508         },
 509         .width          = -1,
 510         .height         = -1,
 511         .tim2           = TIM2_BCD,
 512         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 513         .bpp            = 16,
 514 };
 515
 516 static struct clcd_panel sanyo_2_5_in = {
 517         .mode           = {
 518                 .name           = "Sanyo QVGA Portrait",
 519                 .refresh        = 116,
 520                 .xres           = 240,
 521                 .yres           = 320,
 522                 .pixclock       = 100000,
 523                 .left_margin    = 20,
 524                 .right_margin   = 10,
 525                 .upper_margin   = 2,
 526                 .lower_margin   = 2,
 527                 .hsync_len      = 10,
 528                 .vsync_len      = 2,
 529                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 530                 .vmode          = FB_VMODE_NONINTERLACED,
 531         },
 532         .width          = -1,
 533         .height         = -1,
 534         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 535         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 536         .bpp            = 16,
 537 };
 538
 539 static struct clcd_panel epson_2_2_in = {
 540         .mode           = {
 541                 .name           = "Epson QCIF",
 542                 .refresh        = 390,
 543                 .xres           = 176,
 544                 .yres           = 220,
 545                 .pixclock       = 62500,
 546                 .left_margin    = 3,
 547                 .right_margin   = 2,
 548                 .upper_margin   = 1,
 549                 .lower_margin   = 0,
 550                 .hsync_len      = 3,
 551                 .vsync_len      = 2,
 552                 .sync           = 0,
 553                 .vmode          = FB_VMODE_NONINTERLACED,
 554         },
 555         .width          = -1,
 556         .height         = -1,
 557         .tim2           = TIM2_BCD | TIM2_IPC,
 558         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 559         .bpp            = 16,
 560 };
 561
 562 /*
 563  * Detect which LCD panel is connected, and return the appropriate
 564  * clcd_panel structure.  Note: we do not have any information on
 565  * the required timings for the 8.4in panel, so we presently assume
 566  * VGA timings.
 567  */
 568 static struct clcd_panel *versatile_clcd_panel(void)
 569 {
 570         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 571         struct clcd_panel *panel = &vga;
 572         u32 val;
 573
 574         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 575         if (val == SYS_CLCD_ID_SANYO_3_8)
 576                 panel = &sanyo_3_8_in;
 577         else if (val == SYS_CLCD_ID_SANYO_2_5)
 578                 panel = &sanyo_2_5_in;
 579         else if (val == SYS_CLCD_ID_EPSON_2_2)
 580                 panel = &epson_2_2_in;
 581         else if (val == SYS_CLCD_ID_VGA)
 582                 panel = &vga;
 583         else {
 584                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 585                         val);
 586                 panel = &vga;
 587         }
 588
 589         return panel;
 590 }
 591
 592 /*
 593  * Disable all display connectors on the interface module.
 594  */
 595 static void versatile_clcd_disable(struct clcd_fb *fb)
 596 {
 597         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 598         u32 val;
 599
 600         val = readl(sys_clcd);
 601         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 602         writel(val, sys_clcd);
 603
 604 #ifdef CONFIG_MACH_VERSATILE_AB
 605         /*
 606          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 607          */
 608         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 609                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 610                 unsigned long ctrl;
 611
 612                 ctrl = readl(versatile_ib2_ctrl);
 613                 ctrl &= ~0x01;
 614                 writel(ctrl, versatile_ib2_ctrl);
 615         }
 616 #endif
 617 }
 618
 619 /*
 620  * Enable the relevant connector on the interface module.
 621  */
 622 static void versatile_clcd_enable(struct clcd_fb *fb)
 623 {
 624         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 625         u32 val;
 626
 627         val = readl(sys_clcd);
 628         val &= ~SYS_CLCD_MODE_MASK;
 629
 630         switch (fb->fb.var.green.length) {
 631         case 5:
 632                 val |= SYS_CLCD_MODE_5551;
 633                 break;
 634         case 6:
 635                 val |= SYS_CLCD_MODE_565_RLSB;
 636                 break;
 637         case 8:
 638                 val |= SYS_CLCD_MODE_888;
 639                 break;
 640         }
 641
 642         /*
 643          * Set the MUX
 644          */
 645         writel(val, sys_clcd);
 646
 647         /*
 648          * And now enable the PSUs
 649          */
 650         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 651         writel(val, sys_clcd);
 652
 653 #ifdef CONFIG_MACH_VERSATILE_AB
 654         /*
 655          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 656          */
 657         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 658                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 659                 unsigned long ctrl;
 660
 661                 ctrl = readl(versatile_ib2_ctrl);
 662                 ctrl |= 0x01;
 663                 writel(ctrl, versatile_ib2_ctrl);
 664         }
 665 #endif
 666 }
 667
 668 static unsigned long framesize = SZ_1M;
 669
 670 static int versatile_clcd_setup(struct clcd_fb *fb)
 671 {
 672         dma_addr_t dma;
 673
 674         fb->panel               = versatile_clcd_panel();
 675
 676         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 677                                                     &dma, GFP_KERNEL);
 678         if (!fb->fb.screen_base) {
 679                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 680                 return -ENOMEM;
 681         }
 682
 683         fb->fb.fix.smem_start   = dma;
 684         fb->fb.fix.smem_len     = framesize;
 685
 686         return 0;
 687 }
 688
 689 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 690 {
 691         return dma_mmap_writecombine(&fb->dev->dev, vma,
 692                                      fb->fb.screen_base,
 693                                      fb->fb.fix.smem_start,
 694                                      fb->fb.fix.smem_len);
 695 }
 696
 697 static void versatile_clcd_remove(struct clcd_fb *fb)
 698 {
 699         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 700                               fb->fb.screen_base, fb->fb.fix.smem_start);
 701 }
 702
 703 static struct clcd_board clcd_plat_data = {
 704         .name           = "Versatile",
 705         .check          = clcdfb_check,
 706         .decode         = clcdfb_decode,
 707         .disable        = versatile_clcd_disable,
 708         .enable         = versatile_clcd_enable,
 709         .setup          = versatile_clcd_setup,
 710         .mmap           = versatile_clcd_mmap,
 711         .remove         = versatile_clcd_remove,
 712 };
 713
 714 static struct pl061_platform_data gpio0_plat_data = {
 715         .gpio_base      = 0,
 716         .irq_base       = IRQ_GPIO0_START,
 717 };
 718
 719 static struct pl061_platform_data gpio1_plat_data = {
 720         .gpio_base      = 8,
 721         .irq_base       = IRQ_GPIO1_START,
 722 };
 723
 724 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 725 #define AACI_DMA        { 0x80, 0x81 }
 726 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 727 #define MMCI0_DMA       { 0x84, 0 }
 728 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 729 #define KMI0_DMA        { 0, 0 }
 730 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 731 #define KMI1_DMA        { 0, 0 }
 732
 733 /*
 734  * These devices are connected directly to the multi-layer AHB switch
 735  */
 736 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 737 #define SMC_DMA         { 0, 0 }
 738 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 739 #define MPMC_DMA        { 0, 0 }
 740 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 741 #define CLCD_DMA        { 0, 0 }
 742 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 743 #define DMAC_DMA        { 0, 0 }
 744
 745 /*
 746  * These devices are connected via the core APB bridge
 747  */
 748 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 749 #define SCTL_DMA        { 0, 0 }
 750 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 751 #define WATCHDOG_DMA    { 0, 0 }
 752 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 753 #define GPIO0_DMA       { 0, 0 }
 754 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 755 #define GPIO1_DMA       { 0, 0 }
 756 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 757 #define RTC_DMA         { 0, 0 }
 758
 759 /*
 760  * These devices are connected via the DMA APB bridge
 761  */
 762 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 763 #define SCI_DMA         { 7, 6 }
 764 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 765 #define UART0_DMA       { 15, 14 }
 766 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 767 #define UART1_DMA       { 13, 12 }
 768 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 769 #define UART2_DMA       { 11, 10 }
 770 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 771 #define SSP_DMA         { 9, 8 }
 772
 773 /* FPGA Primecells */
 774 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 775 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 776 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 777 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 778
 779 /* DevChip Primecells */
 780 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 781 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 782 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 783 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 784 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 785 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 786 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 787 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 788 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 789 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 790 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 791 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 792 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 793 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 794
 795 static struct amba_device *amba_devs[] __initdata = {
 796         &dmac_device,
 797         &uart0_device,
 798         &uart1_device,
 799         &uart2_device,
 800         &smc_device,
 801         &mpmc_device,
 802         &clcd_device,
 803         &sctl_device,
 804         &wdog_device,
 805         &gpio0_device,
 806         &gpio1_device,
 807         &rtc_device,
 808         &sci0_device,
 809         &ssp0_device,
 810         &aaci_device,
 811         &mmc0_device,
 812         &kmi0_device,
 813         &kmi1_device,
 814 };
 815
 816 #ifdef CONFIG_LEDS
 817 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 818
 819 static void versatile_leds_event(led_event_t ledevt)
 820 {
 821         unsigned long flags;
 822         u32 val;
 823
 824         local_irq_save(flags);
 825         val = readl(VA_LEDS_BASE);
 826
 827         switch (ledevt) {
 828         case led_idle_start:
 829                 val = val & ~VERSATILE_SYS_LED0;
 830                 break;
 831
 832         case led_idle_end:
 833                 val = val | VERSATILE_SYS_LED0;
 834                 break;
 835
 836         case led_timer:
 837                 val = val ^ VERSATILE_SYS_LED1;
 838                 break;
 839
 840         case led_halted:
 841                 val = 0;
 842                 break;
 843
 844         default:
 845                 break;
 846         }
 847
 848         writel(val, VA_LEDS_BASE);
 849         local_irq_restore(flags);
 850 }
 851 #endif  /* CONFIG_LEDS */
 852
 853 void __init versatile_init(void)
 854 {
 855         int i;
 856
 857         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 858
 859         platform_device_register(&versatile_flash_device);
 860         platform_device_register(&versatile_i2c_device);
 861         platform_device_register(&smc91x_device);
 862
 863         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 864                 struct amba_device *d = amba_devs[i];
 865                 amba_device_register(d, &iomem_resource);
 866         }
 867
 868 #ifdef CONFIG_LEDS
 869         leds_event = versatile_leds_event;
 870 #endif
 871 }
 872
 873 /*
 874  * Where is the timer (VA)?
 875  */
 876 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 877 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 878 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 879 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 880 #define VA_IC_BASE               __io_address(VERSATILE_VIC_BASE)
 881
 882 /*
 883  * How long is the timer interval?
 884  */
 885 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 886 #if TIMER_INTERVAL >= 0x100000
 887 #define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
 888 #define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
 889 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 890 #elif TIMER_INTERVAL >= 0x10000
 891 #define TIMER_RELOAD    (TIMER_INTERVAL >> 4)           /* Divide by 16 */
 892 #define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
 893 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 894 #else
 895 #define TIMER_RELOAD    (TIMER_INTERVAL)
 896 #define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
 897 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 898 #endif
 899
 900 static void timer_set_mode(enum clock_event_mode mode,
 901                            struct clock_event_device *clk)
 902 {
 903         unsigned long ctrl;
 904
 905         switch(mode) {
 906         case CLOCK_EVT_MODE_PERIODIC:
 907                 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
 908
 909                 ctrl = TIMER_CTRL_PERIODIC;
 910                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
 911                 break;
 912         case CLOCK_EVT_MODE_ONESHOT:
 913                 /* period set, and timer enabled in 'next_event' hook */
 914                 ctrl = TIMER_CTRL_ONESHOT;
 915                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
 916                 break;
 917         case CLOCK_EVT_MODE_UNUSED:
 918         case CLOCK_EVT_MODE_SHUTDOWN:
 919         default:
 920                 ctrl = 0;
 921         }
 922
 923         writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
 924 }
 925
 926 static int timer_set_next_event(unsigned long evt,
 927                                 struct clock_event_device *unused)
 928 {
 929         unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
 930
 931         writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
 932         writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
 933
 934         return 0;
 935 }
 936
 937 static struct clock_event_device timer0_clockevent =     {
 938         .name           = "timer0",
 939         .shift          = 32,
 940         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 941         .set_mode       = timer_set_mode,
 942         .set_next_event = timer_set_next_event,
 943 };
 944
 945 /*
 946  * IRQ handler for the timer
 947  */
 948 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
 949 {
 950         struct clock_event_device *evt = &timer0_clockevent;
 951
 952         writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
 953
 954         evt->event_handler(evt);
 955
 956         return IRQ_HANDLED;
 957 }
 958
 959 static struct irqaction versatile_timer_irq = {
 960         .name           = "Versatile Timer Tick",
 961         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 962         .handler        = versatile_timer_interrupt,
 963 };
 964
 965 static cycle_t versatile_get_cycles(struct clocksource *cs)
 966 {
 967         return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
 968 }
 969
 970 static struct clocksource clocksource_versatile = {
 971         .name           = "timer3",
 972         .rating         = 200,
 973         .read           = versatile_get_cycles,
 974         .mask           = CLOCKSOURCE_MASK(32),
 975         .shift          = 20,
 976         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 977 };
 978
 979 static int __init versatile_clocksource_init(void)
 980 {
 981         /* setup timer3 as free-running clocksource */
 982         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 983         writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
 984         writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
 985         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 986                TIMER3_VA_BASE + TIMER_CTRL);
 987
 988         clocksource_versatile.mult =
 989                 clocksource_khz2mult(1000, clocksource_versatile.shift);
 990         clocksource_register(&clocksource_versatile);
 991
 992         return 0;
 993 }
 994
 995 /*
 996  * Set up timer interrupt, and return the current time in seconds.
 997  */
 998 static void __init versatile_timer_init(void)
 999 {
1000         u32 val;
1001
1002         /*
1003          * set clock frequency:
1004          *      VERSATILE_REFCLK is 32KHz
1005          *      VERSATILE_TIMCLK is 1MHz
1006          */
1007         val = readl(__io_address(VERSATILE_SCTL_BASE));
1008         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
1009                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
1010                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
1011                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
1012                __io_address(VERSATILE_SCTL_BASE));
1013
1014         /*
1015          * Initialise to a known state (all timers off)
1016          */
1017         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
1018         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
1019         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
1020         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
1021
1022         /*
1023          * Make irqs happen for the system timer
1024          */
1025         setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
1026
1027         versatile_clocksource_init();
1028
1029         timer0_clockevent.mult =
1030                 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
1031         timer0_clockevent.max_delta_ns =
1032                 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
1033         timer0_clockevent.min_delta_ns =
1034                 clockevent_delta2ns(0xf, &timer0_clockevent);
1035
1036         timer0_clockevent.cpumask = cpumask_of(0);
1037         clockevents_register_device(&timer0_clockevent);
1038 }
1039
1040 struct sys_timer versatile_timer = {
1041         .init           = versatile_timer_init,
1042 };
1043