SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/cnt32_to_63.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/clkdev.h>
  35 #include <asm/system.h>
  36 #include <asm/irq.h>
  37 #include <asm/leds.h>
  38 #include <asm/hardware/arm_timer.h>
  39 #include <asm/hardware/icst.h>
  40 #include <asm/hardware/vic.h>
  41 #include <asm/mach-types.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/flash.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/time.h>
  47 #include <asm/mach/map.h>
  48 #include <mach/clkdev.h>
  49 #include <mach/hardware.h>
  50 #include <mach/platform.h>
  51 #include <plat/timer-sp.h>
  52
  53 #include "core.h"
  54
  55 /*
  56  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  57  * is the (PA >> 12).
  58  *
  59  * Setup a VA for the Versatile Vectored Interrupt Controller.
  60  */
  61 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  62 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  63
  64 static void sic_mask_irq(unsigned int irq)
  65 {
  66         irq -= IRQ_SIC_START;
  67         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  68 }
  69
  70 static void sic_unmask_irq(unsigned int irq)
  71 {
  72         irq -= IRQ_SIC_START;
  73         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  74 }
  75
  76 static struct irq_chip sic_chip = {
  77         .name   = "SIC",
  78         .ack    = sic_mask_irq,
  79         .mask   = sic_mask_irq,
  80         .unmask = sic_unmask_irq,
  81 };
  82
  83 static void
  84 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  85 {
  86         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  87
  88         if (status == 0) {
  89                 do_bad_IRQ(irq, desc);
  90                 return;
  91         }
  92
  93         do {
  94                 irq = ffs(status) - 1;
  95                 status &= ~(1 << irq);
  96
  97                 irq += IRQ_SIC_START;
  98
  99                 generic_handle_irq(irq);
 100         } while (status);
 101 }
 102
 103 #if 1
 104 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 105 #define IRQ_AACI        IRQ_VICSOURCE24
 106 #define IRQ_ETH         IRQ_VICSOURCE25
 107 #define PIC_MASK        0xFFD00000
 108 #else
 109 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 110 #define IRQ_AACI        IRQ_SIC_AACI
 111 #define IRQ_ETH         IRQ_SIC_ETH
 112 #define PIC_MASK        0
 113 #endif
 114
 115 void __init versatile_init_irq(void)
 116 {
 117         unsigned int i;
 118
 119         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 120
 121         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 122
 123         /* Do second interrupt controller */
 124         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 125
 126         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 127                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 128                         set_irq_chip(i, &sic_chip);
 129                         set_irq_handler(i, handle_level_irq);
 130                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 131                 }
 132         }
 133
 134         /*
 135          * Interrupts on secondary controller from 0 to 8 are routed to
 136          * source 31 on PIC.
 137          * Interrupts from 21 to 31 are routed directly to the VIC on
 138          * the corresponding number on primary controller. This is controlled
 139          * by setting PIC_ENABLEx.
 140          */
 141         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 142 }
 143
 144 static struct map_desc versatile_io_desc[] __initdata = {
 145         {
 146                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 147                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 148                 .length         = SZ_4K,
 149                 .type           = MT_DEVICE
 150         }, {
 151                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 152                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE
 155         }, {
 156                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 157                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 158                 .length         = SZ_4K,
 159                 .type           = MT_DEVICE
 160         }, {
 161                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 162                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 163                 .length         = SZ_4K * 9,
 164                 .type           = MT_DEVICE
 165         },
 166 #ifdef CONFIG_MACH_VERSATILE_AB
 167         {
 168                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 169                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 170                 .length         = SZ_4K,
 171                 .type           = MT_DEVICE
 172         }, {
 173                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 174                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 175                 .length         = SZ_64M,
 176                 .type           = MT_DEVICE
 177         },
 178 #endif
 179 #ifdef CONFIG_DEBUG_LL
 180         {
 181                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 182                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 183                 .length         = SZ_4K,
 184                 .type           = MT_DEVICE
 185         },
 186 #endif
 187 #ifdef CONFIG_PCI
 188         {
 189                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 190                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 191                 .length         = SZ_4K,
 192                 .type           = MT_DEVICE
 193         }, {
 194                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 195                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 196                 .length         = VERSATILE_PCI_BASE_SIZE,
 197                 .type           = MT_DEVICE
 198         }, {
 199                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 200                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 201                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 202                 .type           = MT_DEVICE
 203         },
 204 #if 0
 205         {
 206                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 207                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 208                 .length         = SZ_16M,
 209                 .type           = MT_DEVICE
 210         }, {
 211                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 212                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 213                 .length         = SZ_16M,
 214                 .type           = MT_DEVICE
 215         }, {
 216                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 217                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 218                 .length         = SZ_16M,
 219                 .type           = MT_DEVICE
 220         },
 221 #endif
 222 #endif
 223 };
 224
 225 void __init versatile_map_io(void)
 226 {
 227         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 228 }
 229
 230 #define VERSATILE_REFCOUNTER    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
 231
 232 /*
 233  * This is the Versatile sched_clock implementation.  This has
 234  * a resolution of 41.7ns, and a maximum value of about 35583 days.
 235  *
 236  * The return value is guaranteed to be monotonic in that range as
 237  * long as there is always less than 89 seconds between successive
 238  * calls to this function.
 239  */
 240 unsigned long long sched_clock(void)
 241 {
 242         unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
 243
 244         /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
 245         v *= 125<<1;
 246         do_div(v, 3<<1);
 247
 248         return v;
 249 }
 250
 251
 252 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 253
 254 static int versatile_flash_init(void)
 255 {
 256         u32 val;
 257
 258         val = __raw_readl(VERSATILE_FLASHCTRL);
 259         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 260         __raw_writel(val, VERSATILE_FLASHCTRL);
 261
 262         return 0;
 263 }
 264
 265 static void versatile_flash_exit(void)
 266 {
 267         u32 val;
 268
 269         val = __raw_readl(VERSATILE_FLASHCTRL);
 270         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 271         __raw_writel(val, VERSATILE_FLASHCTRL);
 272 }
 273
 274 static void versatile_flash_set_vpp(int on)
 275 {
 276         u32 val;
 277
 278         val = __raw_readl(VERSATILE_FLASHCTRL);
 279         if (on)
 280                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 281         else
 282                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 283         __raw_writel(val, VERSATILE_FLASHCTRL);
 284 }
 285
 286 static struct flash_platform_data versatile_flash_data = {
 287         .map_name               = "cfi_probe",
 288         .width                  = 4,
 289         .init                   = versatile_flash_init,
 290         .exit                   = versatile_flash_exit,
 291         .set_vpp                = versatile_flash_set_vpp,
 292 };
 293
 294 static struct resource versatile_flash_resource = {
 295         .start                  = VERSATILE_FLASH_BASE,
 296         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 297         .flags                  = IORESOURCE_MEM,
 298 };
 299
 300 static struct platform_device versatile_flash_device = {
 301         .name                   = "armflash",
 302         .id                     = 0,
 303         .dev                    = {
 304                 .platform_data  = &versatile_flash_data,
 305         },
 306         .num_resources          = 1,
 307         .resource               = &versatile_flash_resource,
 308 };
 309
 310 static struct resource smc91x_resources[] = {
 311         [0] = {
 312                 .start          = VERSATILE_ETH_BASE,
 313                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 314                 .flags          = IORESOURCE_MEM,
 315         },
 316         [1] = {
 317                 .start          = IRQ_ETH,
 318                 .end            = IRQ_ETH,
 319                 .flags          = IORESOURCE_IRQ,
 320         },
 321 };
 322
 323 static struct platform_device smc91x_device = {
 324         .name           = "smc91x",
 325         .id             = 0,
 326         .num_resources  = ARRAY_SIZE(smc91x_resources),
 327         .resource       = smc91x_resources,
 328 };
 329
 330 static struct resource versatile_i2c_resource = {
 331         .start                  = VERSATILE_I2C_BASE,
 332         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 333         .flags                  = IORESOURCE_MEM,
 334 };
 335
 336 static struct platform_device versatile_i2c_device = {
 337         .name                   = "versatile-i2c",
 338         .id                     = 0,
 339         .num_resources          = 1,
 340         .resource               = &versatile_i2c_resource,
 341 };
 342
 343 static struct i2c_board_info versatile_i2c_board_info[] = {
 344         {
 345                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 346         },
 347 };
 348
 349 static int __init versatile_i2c_init(void)
 350 {
 351         return i2c_register_board_info(0, versatile_i2c_board_info,
 352                                        ARRAY_SIZE(versatile_i2c_board_info));
 353 }
 354 arch_initcall(versatile_i2c_init);
 355
 356 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 357
 358 unsigned int mmc_status(struct device *dev)
 359 {
 360         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 361         u32 mask;
 362
 363         if (adev->res.start == VERSATILE_MMCI0_BASE)
 364                 mask = 1;
 365         else
 366                 mask = 2;
 367
 368         return readl(VERSATILE_SYSMCI) & mask;
 369 }
 370
 371 static struct mmci_platform_data mmc0_plat_data = {
 372         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 373         .status         = mmc_status,
 374         .gpio_wp        = -1,
 375         .gpio_cd        = -1,
 376 };
 377
 378 /*
 379  * Clock handling
 380  */
 381 static const struct icst_params versatile_oscvco_params = {
 382         .ref            = 24000000,
 383         .vco_max        = ICST307_VCO_MAX,
 384         .vco_min        = ICST307_VCO_MIN,
 385         .vd_min         = 4 + 8,
 386         .vd_max         = 511 + 8,
 387         .rd_min         = 1 + 2,
 388         .rd_max         = 127 + 2,
 389         .s2div          = icst307_s2div,
 390         .idx2s          = icst307_idx2s,
 391 };
 392
 393 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 394 {
 395         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 396         void __iomem *sys_lock = sys + VERSATILE_SYS_LOCK_OFFSET;
 397         u32 val;
 398
 399         val = readl(sys + clk->oscoff) & ~0x7ffff;
 400         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 401
 402         writel(0xa05f, sys_lock);
 403         writel(val, sys + clk->oscoff);
 404         writel(0, sys_lock);
 405 }
 406
 407 static struct clk osc4_clk = {
 408         .params = &versatile_oscvco_params,
 409         .oscoff = VERSATILE_SYS_OSCCLCD_OFFSET,
 410         .setvco = versatile_oscvco_set,
 411 };
 412
 413 /*
 414  * These are fixed clocks.
 415  */
 416 static struct clk ref24_clk = {
 417         .rate   = 24000000,
 418 };
 419
 420 static struct clk_lookup lookups[] = {
 421         {       /* UART0 */
 422                 .dev_id         = "dev:f1",
 423                 .clk            = &ref24_clk,
 424         }, {    /* UART1 */
 425                 .dev_id         = "dev:f2",
 426                 .clk            = &ref24_clk,
 427         }, {    /* UART2 */
 428                 .dev_id         = "dev:f3",
 429                 .clk            = &ref24_clk,
 430         }, {    /* UART3 */
 431                 .dev_id         = "fpga:09",
 432                 .clk            = &ref24_clk,
 433         }, {    /* KMI0 */
 434                 .dev_id         = "fpga:06",
 435                 .clk            = &ref24_clk,
 436         }, {    /* KMI1 */
 437                 .dev_id         = "fpga:07",
 438                 .clk            = &ref24_clk,
 439         }, {    /* MMC0 */
 440                 .dev_id         = "fpga:05",
 441                 .clk            = &ref24_clk,
 442         }, {    /* MMC1 */
 443                 .dev_id         = "fpga:0b",
 444                 .clk            = &ref24_clk,
 445         }, {    /* CLCD */
 446                 .dev_id         = "dev:20",
 447                 .clk            = &osc4_clk,
 448         }
 449 };
 450
 451 /*
 452  * CLCD support.
 453  */
 454 #define SYS_CLCD_MODE_MASK      (3 << 0)
 455 #define SYS_CLCD_MODE_888       (0 << 0)
 456 #define SYS_CLCD_MODE_5551      (1 << 0)
 457 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 458 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 459 #define SYS_CLCD_NLCDIOON       (1 << 2)
 460 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 461 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 462 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 463 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 464 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 465 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 466 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 467 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 468
 469 static struct clcd_panel vga = {
 470         .mode           = {
 471                 .name           = "VGA",
 472                 .refresh        = 60,
 473                 .xres           = 640,
 474                 .yres           = 480,
 475                 .pixclock       = 39721,
 476                 .left_margin    = 40,
 477                 .right_margin   = 24,
 478                 .upper_margin   = 32,
 479                 .lower_margin   = 11,
 480                 .hsync_len      = 96,
 481                 .vsync_len      = 2,
 482                 .sync           = 0,
 483                 .vmode          = FB_VMODE_NONINTERLACED,
 484         },
 485         .width          = -1,
 486         .height         = -1,
 487         .tim2           = TIM2_BCD | TIM2_IPC,
 488         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 489         .bpp            = 16,
 490 };
 491
 492 static struct clcd_panel sanyo_3_8_in = {
 493         .mode           = {
 494                 .name           = "Sanyo QVGA",
 495                 .refresh        = 116,
 496                 .xres           = 320,
 497                 .yres           = 240,
 498                 .pixclock       = 100000,
 499                 .left_margin    = 6,
 500                 .right_margin   = 6,
 501                 .upper_margin   = 5,
 502                 .lower_margin   = 5,
 503                 .hsync_len      = 6,
 504                 .vsync_len      = 6,
 505                 .sync           = 0,
 506                 .vmode          = FB_VMODE_NONINTERLACED,
 507         },
 508         .width          = -1,
 509         .height         = -1,
 510         .tim2           = TIM2_BCD,
 511         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 512         .bpp            = 16,
 513 };
 514
 515 static struct clcd_panel sanyo_2_5_in = {
 516         .mode           = {
 517                 .name           = "Sanyo QVGA Portrait",
 518                 .refresh        = 116,
 519                 .xres           = 240,
 520                 .yres           = 320,
 521                 .pixclock       = 100000,
 522                 .left_margin    = 20,
 523                 .right_margin   = 10,
 524                 .upper_margin   = 2,
 525                 .lower_margin   = 2,
 526                 .hsync_len      = 10,
 527                 .vsync_len      = 2,
 528                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 529                 .vmode          = FB_VMODE_NONINTERLACED,
 530         },
 531         .width          = -1,
 532         .height         = -1,
 533         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 534         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 535         .bpp            = 16,
 536 };
 537
 538 static struct clcd_panel epson_2_2_in = {
 539         .mode           = {
 540                 .name           = "Epson QCIF",
 541                 .refresh        = 390,
 542                 .xres           = 176,
 543                 .yres           = 220,
 544                 .pixclock       = 62500,
 545                 .left_margin    = 3,
 546                 .right_margin   = 2,
 547                 .upper_margin   = 1,
 548                 .lower_margin   = 0,
 549                 .hsync_len      = 3,
 550                 .vsync_len      = 2,
 551                 .sync           = 0,
 552                 .vmode          = FB_VMODE_NONINTERLACED,
 553         },
 554         .width          = -1,
 555         .height         = -1,
 556         .tim2           = TIM2_BCD | TIM2_IPC,
 557         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 558         .bpp            = 16,
 559 };
 560
 561 /*
 562  * Detect which LCD panel is connected, and return the appropriate
 563  * clcd_panel structure.  Note: we do not have any information on
 564  * the required timings for the 8.4in panel, so we presently assume
 565  * VGA timings.
 566  */
 567 static struct clcd_panel *versatile_clcd_panel(void)
 568 {
 569         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 570         struct clcd_panel *panel = &vga;
 571         u32 val;
 572
 573         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 574         if (val == SYS_CLCD_ID_SANYO_3_8)
 575                 panel = &sanyo_3_8_in;
 576         else if (val == SYS_CLCD_ID_SANYO_2_5)
 577                 panel = &sanyo_2_5_in;
 578         else if (val == SYS_CLCD_ID_EPSON_2_2)
 579                 panel = &epson_2_2_in;
 580         else if (val == SYS_CLCD_ID_VGA)
 581                 panel = &vga;
 582         else {
 583                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 584                         val);
 585                 panel = &vga;
 586         }
 587
 588         return panel;
 589 }
 590
 591 /*
 592  * Disable all display connectors on the interface module.
 593  */
 594 static void versatile_clcd_disable(struct clcd_fb *fb)
 595 {
 596         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 597         u32 val;
 598
 599         val = readl(sys_clcd);
 600         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 601         writel(val, sys_clcd);
 602
 603 #ifdef CONFIG_MACH_VERSATILE_AB
 604         /*
 605          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 606          */
 607         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 608                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 609                 unsigned long ctrl;
 610
 611                 ctrl = readl(versatile_ib2_ctrl);
 612                 ctrl &= ~0x01;
 613                 writel(ctrl, versatile_ib2_ctrl);
 614         }
 615 #endif
 616 }
 617
 618 /*
 619  * Enable the relevant connector on the interface module.
 620  */
 621 static void versatile_clcd_enable(struct clcd_fb *fb)
 622 {
 623         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 624         u32 val;
 625
 626         val = readl(sys_clcd);
 627         val &= ~SYS_CLCD_MODE_MASK;
 628
 629         switch (fb->fb.var.green.length) {
 630         case 5:
 631                 val |= SYS_CLCD_MODE_5551;
 632                 break;
 633         case 6:
 634                 val |= SYS_CLCD_MODE_565_RLSB;
 635                 break;
 636         case 8:
 637                 val |= SYS_CLCD_MODE_888;
 638                 break;
 639         }
 640
 641         /*
 642          * Set the MUX
 643          */
 644         writel(val, sys_clcd);
 645
 646         /*
 647          * And now enable the PSUs
 648          */
 649         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 650         writel(val, sys_clcd);
 651
 652 #ifdef CONFIG_MACH_VERSATILE_AB
 653         /*
 654          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 655          */
 656         if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
 657                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 658                 unsigned long ctrl;
 659
 660                 ctrl = readl(versatile_ib2_ctrl);
 661                 ctrl |= 0x01;
 662                 writel(ctrl, versatile_ib2_ctrl);
 663         }
 664 #endif
 665 }
 666
 667 static unsigned long framesize = SZ_1M;
 668
 669 static int versatile_clcd_setup(struct clcd_fb *fb)
 670 {
 671         dma_addr_t dma;
 672
 673         fb->panel               = versatile_clcd_panel();
 674
 675         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 676                                                     &dma, GFP_KERNEL);
 677         if (!fb->fb.screen_base) {
 678                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 679                 return -ENOMEM;
 680         }
 681
 682         fb->fb.fix.smem_start   = dma;
 683         fb->fb.fix.smem_len     = framesize;
 684
 685         return 0;
 686 }
 687
 688 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 689 {
 690         return dma_mmap_writecombine(&fb->dev->dev, vma,
 691                                      fb->fb.screen_base,
 692                                      fb->fb.fix.smem_start,
 693                                      fb->fb.fix.smem_len);
 694 }
 695
 696 static void versatile_clcd_remove(struct clcd_fb *fb)
 697 {
 698         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 699                               fb->fb.screen_base, fb->fb.fix.smem_start);
 700 }
 701
 702 static struct clcd_board clcd_plat_data = {
 703         .name           = "Versatile",
 704         .check          = clcdfb_check,
 705         .decode         = clcdfb_decode,
 706         .disable        = versatile_clcd_disable,
 707         .enable         = versatile_clcd_enable,
 708         .setup          = versatile_clcd_setup,
 709         .mmap           = versatile_clcd_mmap,
 710         .remove         = versatile_clcd_remove,
 711 };
 712
 713 static struct pl061_platform_data gpio0_plat_data = {
 714         .gpio_base      = 0,
 715         .irq_base       = IRQ_GPIO0_START,
 716 };
 717
 718 static struct pl061_platform_data gpio1_plat_data = {
 719         .gpio_base      = 8,
 720         .irq_base       = IRQ_GPIO1_START,
 721 };
 722
 723 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 724 #define AACI_DMA        { 0x80, 0x81 }
 725 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 726 #define MMCI0_DMA       { 0x84, 0 }
 727 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 728 #define KMI0_DMA        { 0, 0 }
 729 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 730 #define KMI1_DMA        { 0, 0 }
 731
 732 /*
 733  * These devices are connected directly to the multi-layer AHB switch
 734  */
 735 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 736 #define SMC_DMA         { 0, 0 }
 737 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 738 #define MPMC_DMA        { 0, 0 }
 739 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 740 #define CLCD_DMA        { 0, 0 }
 741 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 742 #define DMAC_DMA        { 0, 0 }
 743
 744 /*
 745  * These devices are connected via the core APB bridge
 746  */
 747 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 748 #define SCTL_DMA        { 0, 0 }
 749 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 750 #define WATCHDOG_DMA    { 0, 0 }
 751 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 752 #define GPIO0_DMA       { 0, 0 }
 753 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 754 #define GPIO1_DMA       { 0, 0 }
 755 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 756 #define RTC_DMA         { 0, 0 }
 757
 758 /*
 759  * These devices are connected via the DMA APB bridge
 760  */
 761 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 762 #define SCI_DMA         { 7, 6 }
 763 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 764 #define UART0_DMA       { 15, 14 }
 765 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 766 #define UART1_DMA       { 13, 12 }
 767 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 768 #define UART2_DMA       { 11, 10 }
 769 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 770 #define SSP_DMA         { 9, 8 }
 771
 772 /* FPGA Primecells */
 773 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 774 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 775 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 776 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 777
 778 /* DevChip Primecells */
 779 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 780 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 781 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 782 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 783 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 784 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 785 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 786 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 787 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 788 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 789 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 790 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 791 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 792 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 793
 794 static struct amba_device *amba_devs[] __initdata = {
 795         &dmac_device,
 796         &uart0_device,
 797         &uart1_device,
 798         &uart2_device,
 799         &smc_device,
 800         &mpmc_device,
 801         &clcd_device,
 802         &sctl_device,
 803         &wdog_device,
 804         &gpio0_device,
 805         &gpio1_device,
 806         &rtc_device,
 807         &sci0_device,
 808         &ssp0_device,
 809         &aaci_device,
 810         &mmc0_device,
 811         &kmi0_device,
 812         &kmi1_device,
 813 };
 814
 815 #ifdef CONFIG_LEDS
 816 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 817
 818 static void versatile_leds_event(led_event_t ledevt)
 819 {
 820         unsigned long flags;
 821         u32 val;
 822
 823         local_irq_save(flags);
 824         val = readl(VA_LEDS_BASE);
 825
 826         switch (ledevt) {
 827         case led_idle_start:
 828                 val = val & ~VERSATILE_SYS_LED0;
 829                 break;
 830
 831         case led_idle_end:
 832                 val = val | VERSATILE_SYS_LED0;
 833                 break;
 834
 835         case led_timer:
 836                 val = val ^ VERSATILE_SYS_LED1;
 837                 break;
 838
 839         case led_halted:
 840                 val = 0;
 841                 break;
 842
 843         default:
 844                 break;
 845         }
 846
 847         writel(val, VA_LEDS_BASE);
 848         local_irq_restore(flags);
 849 }
 850 #endif  /* CONFIG_LEDS */
 851
 852 void __init versatile_init(void)
 853 {
 854         int i;
 855
 856         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 857
 858         platform_device_register(&versatile_flash_device);
 859         platform_device_register(&versatile_i2c_device);
 860         platform_device_register(&smc91x_device);
 861
 862         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 863                 struct amba_device *d = amba_devs[i];
 864                 amba_device_register(d, &iomem_resource);
 865         }
 866
 867 #ifdef CONFIG_LEDS
 868         leds_event = versatile_leds_event;
 869 #endif
 870 }
 871
 872 /*
 873  * Where is the timer (VA)?
 874  */
 875 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 876 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 877 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 878 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 879
 880 /*
 881  * Set up timer interrupt, and return the current time in seconds.
 882  */
 883 static void __init versatile_timer_init(void)
 884 {
 885         u32 val;
 886
 887         /*
 888          * set clock frequency:
 889          *      VERSATILE_REFCLK is 32KHz
 890          *      VERSATILE_TIMCLK is 1MHz
 891          */
 892         val = readl(__io_address(VERSATILE_SCTL_BASE));
 893         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 894                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 895                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 896                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 897                __io_address(VERSATILE_SCTL_BASE));
 898
 899         /*
 900          * Initialise to a known state (all timers off)
 901          */
 902         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 903         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 904         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 905         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 906
 907         sp804_clocksource_init(TIMER3_VA_BASE);
 908         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 909 }
 910
 911 struct sys_timer versatile_timer = {
 912         .init           = versatile_timer_init,
 913 };
 914