SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74                 .id             = -1,
  75         },
  76         .sources        = &clkset_armclk,
  77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  79 };
  80
  81 static struct clksrc_clk clk_hclk_msys = {
  82         .clk    = {
  83                 .name           = "hclk_msys",
  84                 .id             = -1,
  85                 .parent         = &clk_armclk.clk,
  86         },
  87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  88 };
  89
  90 static struct clksrc_clk clk_pclk_msys = {
  91         .clk    = {
  92                 .name           = "pclk_msys",
  93                 .id             = -1,
  94                 .parent         = &clk_hclk_msys.clk,
  95         },
  96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  97 };
  98
  99 static struct clksrc_clk clk_sclk_a2m = {
 100         .clk    = {
 101                 .name           = "sclk_a2m",
 102                 .id             = -1,
 103                 .parent         = &clk_mout_apll.clk,
 104         },
 105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 106 };
 107
 108 static struct clk *clkset_hclk_sys_list[] = {
 109         [0] = &clk_mout_mpll.clk,
 110         [1] = &clk_sclk_a2m.clk,
 111 };
 112
 113 static struct clksrc_sources clkset_hclk_sys = {
 114         .sources        = clkset_hclk_sys_list,
 115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 116 };
 117
 118 static struct clksrc_clk clk_hclk_dsys = {
 119         .clk    = {
 120                 .name   = "hclk_dsys",
 121                 .id     = -1,
 122         },
 123         .sources        = &clkset_hclk_sys,
 124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 126 };
 127
 128 static struct clksrc_clk clk_pclk_dsys = {
 129         .clk    = {
 130                 .name   = "pclk_dsys",
 131                 .id     = -1,
 132                 .parent = &clk_hclk_dsys.clk,
 133         },
 134         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 135 };
 136
 137 static struct clksrc_clk clk_hclk_psys = {
 138         .clk    = {
 139                 .name   = "hclk_psys",
 140                 .id     = -1,
 141         },
 142         .sources        = &clkset_hclk_sys,
 143         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 145 };
 146
 147 static struct clksrc_clk clk_pclk_psys = {
 148         .clk    = {
 149                 .name   = "pclk_psys",
 150                 .id     = -1,
 151                 .parent = &clk_hclk_psys.clk,
 152         },
 153         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 154 };
 155
 156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 159 }
 160
 161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 164 }
 165
 166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 169 }
 170
 171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 174 }
 175
 176 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 179 }
 180
 181 static struct clk clk_sclk_hdmi27m = {
 182         .name           = "sclk_hdmi27m",
 183         .id             = -1,
 184         .rate           = 27000000,
 185 };
 186
 187 static struct clk *clkset_vpllsrc_list[] = {
 188         [0] = &clk_fin_vpll,
 189         [1] = &clk_sclk_hdmi27m,
 190 };
 191
 192 static struct clksrc_sources clkset_vpllsrc = {
 193         .sources        = clkset_vpllsrc_list,
 194         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 195 };
 196
 197 static struct clksrc_clk clk_vpllsrc = {
 198         .clk    = {
 199                 .name           = "vpll_src",
 200                 .id             = -1,
 201                 .enable         = s5pv210_clk_mask0_ctrl,
 202                 .ctrlbit        = (1 << 7),
 203         },
 204         .sources        = &clkset_vpllsrc,
 205         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 206 };
 207
 208 static struct clk *clkset_sclk_vpll_list[] = {
 209         [0] = &clk_vpllsrc.clk,
 210         [1] = &clk_fout_vpll,
 211 };
 212
 213 static struct clksrc_sources clkset_sclk_vpll = {
 214         .sources        = clkset_sclk_vpll_list,
 215         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 216 };
 217
 218 static struct clksrc_clk clk_sclk_vpll = {
 219         .clk    = {
 220                 .name           = "sclk_vpll",
 221                 .id             = -1,
 222         },
 223         .sources        = &clkset_sclk_vpll,
 224         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 225 };
 226
 227 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 228 {
 229         return clk_get_rate(clk->parent) / 2;
 230 }
 231
 232 static struct clk_ops clk_hclk_imem_ops = {
 233         .get_rate       = s5pv210_clk_imem_get_rate,
 234 };
 235
 236 static struct clk init_clocks_disable[] = {
 237         {
 238                 .name           = "rot",
 239                 .id             = -1,
 240                 .parent         = &clk_hclk_dsys.clk,
 241                 .enable         = s5pv210_clk_ip0_ctrl,
 242                 .ctrlbit        = (1<<29),
 243         }, {
 244                 .name           = "otg",
 245                 .id             = -1,
 246                 .parent         = &clk_hclk_psys.clk,
 247                 .enable         = s5pv210_clk_ip1_ctrl,
 248                 .ctrlbit        = (1<<16),
 249         }, {
 250                 .name           = "usb-host",
 251                 .id             = -1,
 252                 .parent         = &clk_hclk_psys.clk,
 253                 .enable         = s5pv210_clk_ip1_ctrl,
 254                 .ctrlbit        = (1<<17),
 255         }, {
 256                 .name           = "lcd",
 257                 .id             = -1,
 258                 .parent         = &clk_hclk_dsys.clk,
 259                 .enable         = s5pv210_clk_ip1_ctrl,
 260                 .ctrlbit        = (1<<0),
 261         }, {
 262                 .name           = "cfcon",
 263                 .id             = 0,
 264                 .parent         = &clk_hclk_psys.clk,
 265                 .enable         = s5pv210_clk_ip1_ctrl,
 266                 .ctrlbit        = (1<<25),
 267         }, {
 268                 .name           = "hsmmc",
 269                 .id             = 0,
 270                 .parent         = &clk_hclk_psys.clk,
 271                 .enable         = s5pv210_clk_ip2_ctrl,
 272                 .ctrlbit        = (1<<16),
 273         }, {
 274                 .name           = "hsmmc",
 275                 .id             = 1,
 276                 .parent         = &clk_hclk_psys.clk,
 277                 .enable         = s5pv210_clk_ip2_ctrl,
 278                 .ctrlbit        = (1<<17),
 279         }, {
 280                 .name           = "hsmmc",
 281                 .id             = 2,
 282                 .parent         = &clk_hclk_psys.clk,
 283                 .enable         = s5pv210_clk_ip2_ctrl,
 284                 .ctrlbit        = (1<<18),
 285         }, {
 286                 .name           = "hsmmc",
 287                 .id             = 3,
 288                 .parent         = &clk_hclk_psys.clk,
 289                 .enable         = s5pv210_clk_ip2_ctrl,
 290                 .ctrlbit        = (1<<19),
 291         }, {
 292                 .name           = "systimer",
 293                 .id             = -1,
 294                 .parent         = &clk_pclk_psys.clk,
 295                 .enable         = s5pv210_clk_ip3_ctrl,
 296                 .ctrlbit        = (1<<16),
 297         }, {
 298                 .name           = "watchdog",
 299                 .id             = -1,
 300                 .parent         = &clk_pclk_psys.clk,
 301                 .enable         = s5pv210_clk_ip3_ctrl,
 302                 .ctrlbit        = (1<<22),
 303         }, {
 304                 .name           = "rtc",
 305                 .id             = -1,
 306                 .parent         = &clk_pclk_psys.clk,
 307                 .enable         = s5pv210_clk_ip3_ctrl,
 308                 .ctrlbit        = (1<<15),
 309         }, {
 310                 .name           = "i2c",
 311                 .id             = 0,
 312                 .parent         = &clk_pclk_psys.clk,
 313                 .enable         = s5pv210_clk_ip3_ctrl,
 314                 .ctrlbit        = (1<<7),
 315         }, {
 316                 .name           = "i2c",
 317                 .id             = 1,
 318                 .parent         = &clk_pclk_psys.clk,
 319                 .enable         = s5pv210_clk_ip3_ctrl,
 320                 .ctrlbit        = (1<<8),
 321         }, {
 322                 .name           = "i2c",
 323                 .id             = 2,
 324                 .parent         = &clk_pclk_psys.clk,
 325                 .enable         = s5pv210_clk_ip3_ctrl,
 326                 .ctrlbit        = (1<<9),
 327         }, {
 328                 .name           = "spi",
 329                 .id             = 0,
 330                 .parent         = &clk_pclk_psys.clk,
 331                 .enable         = s5pv210_clk_ip3_ctrl,
 332                 .ctrlbit        = (1<<12),
 333         }, {
 334                 .name           = "spi",
 335                 .id             = 1,
 336                 .parent         = &clk_pclk_psys.clk,
 337                 .enable         = s5pv210_clk_ip3_ctrl,
 338                 .ctrlbit        = (1<<13),
 339         }, {
 340                 .name           = "spi",
 341                 .id             = 2,
 342                 .parent         = &clk_pclk_psys.clk,
 343                 .enable         = s5pv210_clk_ip3_ctrl,
 344                 .ctrlbit        = (1<<14),
 345         }, {
 346                 .name           = "timers",
 347                 .id             = -1,
 348                 .parent         = &clk_pclk_psys.clk,
 349                 .enable         = s5pv210_clk_ip3_ctrl,
 350                 .ctrlbit        = (1<<23),
 351         }, {
 352                 .name           = "adc",
 353                 .id             = -1,
 354                 .parent         = &clk_pclk_psys.clk,
 355                 .enable         = s5pv210_clk_ip3_ctrl,
 356                 .ctrlbit        = (1<<24),
 357         }, {
 358                 .name           = "keypad",
 359                 .id             = -1,
 360                 .parent         = &clk_pclk_psys.clk,
 361                 .enable         = s5pv210_clk_ip3_ctrl,
 362                 .ctrlbit        = (1<<21),
 363         }, {
 364                 .name           = "i2s_v50",
 365                 .id             = 0,
 366                 .parent         = &clk_p,
 367                 .enable         = s5pv210_clk_ip3_ctrl,
 368                 .ctrlbit        = (1<<4),
 369         }, {
 370                 .name           = "i2s_v32",
 371                 .id             = 0,
 372                 .parent         = &clk_p,
 373                 .enable         = s5pv210_clk_ip3_ctrl,
 374                 .ctrlbit        = (1<<4),
 375         }, {
 376                 .name           = "i2s_v32",
 377                 .id             = 1,
 378                 .parent         = &clk_p,
 379                 .enable         = s5pv210_clk_ip3_ctrl,
 380                 .ctrlbit        = (1<<4),
 381         }
 382 };
 383
 384 static struct clk init_clocks[] = {
 385         {
 386                 .name           = "hclk_imem",
 387                 .id             = -1,
 388                 .parent         = &clk_hclk_msys.clk,
 389                 .ctrlbit        = (1 << 5),
 390                 .enable         = s5pv210_clk_ip0_ctrl,
 391                 .ops            = &clk_hclk_imem_ops,
 392         }, {
 393                 .name           = "uart",
 394                 .id             = 0,
 395                 .parent         = &clk_pclk_psys.clk,
 396                 .enable         = s5pv210_clk_ip3_ctrl,
 397                 .ctrlbit        = (1<<7),
 398         }, {
 399                 .name           = "uart",
 400                 .id             = 1,
 401                 .parent         = &clk_pclk_psys.clk,
 402                 .enable         = s5pv210_clk_ip3_ctrl,
 403                 .ctrlbit        = (1<<8),
 404         }, {
 405                 .name           = "uart",
 406                 .id             = 2,
 407                 .parent         = &clk_pclk_psys.clk,
 408                 .enable         = s5pv210_clk_ip3_ctrl,
 409                 .ctrlbit        = (1<<9),
 410         }, {
 411                 .name           = "uart",
 412                 .id             = 3,
 413                 .parent         = &clk_pclk_psys.clk,
 414                 .enable         = s5pv210_clk_ip3_ctrl,
 415                 .ctrlbit        = (1<<10),
 416         },
 417 };
 418
 419 static struct clk *clkset_uart_list[] = {
 420         [6] = &clk_mout_mpll.clk,
 421         [7] = &clk_mout_epll.clk,
 422 };
 423
 424 static struct clksrc_sources clkset_uart = {
 425         .sources        = clkset_uart_list,
 426         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 427 };
 428
 429 static struct clksrc_clk clksrcs[] = {
 430         {
 431                 .clk    = {
 432                         .name           = "uclk1",
 433                         .id             = -1,
 434                         .ctrlbit        = (1<<17),
 435                         .enable         = s5pv210_clk_ip3_ctrl,
 436                 },
 437                 .sources = &clkset_uart,
 438                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 439                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 440         }
 441 };
 442
 443 /* Clock initialisation code */
 444 static struct clksrc_clk *sysclks[] = {
 445         &clk_mout_apll,
 446         &clk_mout_epll,
 447         &clk_mout_mpll,
 448         &clk_armclk,
 449         &clk_hclk_msys,
 450         &clk_sclk_a2m,
 451         &clk_hclk_dsys,
 452         &clk_hclk_psys,
 453         &clk_pclk_msys,
 454         &clk_pclk_dsys,
 455         &clk_pclk_psys,
 456         &clk_vpllsrc,
 457         &clk_sclk_vpll,
 458 };
 459
 460 void __init_or_cpufreq s5pv210_setup_clocks(void)
 461 {
 462         struct clk *xtal_clk;
 463         unsigned long xtal;
 464         unsigned long vpllsrc;
 465         unsigned long armclk;
 466         unsigned long hclk_msys;
 467         unsigned long hclk_dsys;
 468         unsigned long hclk_psys;
 469         unsigned long pclk_msys;
 470         unsigned long pclk_dsys;
 471         unsigned long pclk_psys;
 472         unsigned long apll;
 473         unsigned long mpll;
 474         unsigned long epll;
 475         unsigned long vpll;
 476         unsigned int ptr;
 477         u32 clkdiv0, clkdiv1;
 478
 479         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 480
 481         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 482         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 483
 484         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 485                                 __func__, clkdiv0, clkdiv1);
 486
 487         xtal_clk = clk_get(NULL, "xtal");
 488         BUG_ON(IS_ERR(xtal_clk));
 489
 490         xtal = clk_get_rate(xtal_clk);
 491         clk_put(xtal_clk);
 492
 493         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 494
 495         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 496         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 497         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 498         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
 499         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
 500
 501         clk_fout_apll.rate = apll;
 502         clk_fout_mpll.rate = mpll;
 503         clk_fout_epll.rate = epll;
 504         clk_fout_vpll.rate = vpll;
 505
 506         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
 507                         apll, mpll, epll, vpll);
 508
 509         armclk = clk_get_rate(&clk_armclk.clk);
 510         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
 511         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
 512         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
 513         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
 514         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
 515         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
 516
 517         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
 518                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 519                         armclk, hclk_msys, hclk_dsys, hclk_psys,
 520                         pclk_msys, pclk_dsys, pclk_psys);
 521
 522         clk_f.rate = armclk;
 523         clk_h.rate = hclk_psys;
 524         clk_p.rate = pclk_psys;
 525
 526         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 527                 s3c_set_clksrc(&clksrcs[ptr], true);
 528 }
 529
 530 static struct clk *clks[] __initdata = {
 531         &clk_sclk_hdmi27m,
 532 };
 533
 534 void __init s5pv210_register_clocks(void)
 535 {
 536         struct clk *clkp;
 537         int ret;
 538         int ptr;
 539
 540         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 541         if (ret > 0)
 542                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 543
 544         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 545                 s3c_register_clksrc(sysclks[ptr], 1);
 546
 547         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 548         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 549
 550         clkp = init_clocks_disable;
 551         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 552                 ret = s3c24xx_register_clock(clkp);
 553                 if (ret < 0) {
 554                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 555                                clkp->name, ret);
 556                 }
 557                 (clkp->enable)(clkp, 0);
 558         }
 559
 560         s3c_pwmclk_init();
 561 }