1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static struct clksrc_clk clk_mout_apll = {
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61 static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
66 static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71 static struct clksrc_clk clk_armclk = {
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81 static struct clksrc_clk clk_hclk_msys = {
85 .parent = &clk_armclk.clk,
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90 static struct clksrc_clk clk_pclk_msys = {
94 .parent = &clk_hclk_msys.clk,
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
99 static struct clksrc_clk clk_sclk_a2m = {
103 .parent = &clk_mout_apll.clk,
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
108 static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
113 static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
118 static struct clksrc_clk clk_hclk_dsys = {
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 static struct clksrc_clk clk_pclk_dsys = {
132 .parent = &clk_hclk_dsys.clk,
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
137 static struct clksrc_clk clk_hclk_psys = {
142 .sources = &clkset_hclk_sys,
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
147 static struct clksrc_clk clk_pclk_psys = {
151 .parent = &clk_hclk_psys.clk,
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
158 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
163 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
176 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
178 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
181 static struct clk clk_sclk_hdmi27m = {
182 .name = "sclk_hdmi27m",
187 static struct clk clk_sclk_hdmiphy = {
188 .name = "sclk_hdmiphy",
192 static struct clk clk_sclk_usbphy0 = {
193 .name = "sclk_usbphy0",
197 static struct clk clk_sclk_usbphy1 = {
198 .name = "sclk_usbphy1",
202 static struct clk *clkset_vpllsrc_list[] = {
204 [1] = &clk_sclk_hdmi27m,
207 static struct clksrc_sources clkset_vpllsrc = {
208 .sources = clkset_vpllsrc_list,
209 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
212 static struct clksrc_clk clk_vpllsrc = {
216 .enable = s5pv210_clk_mask0_ctrl,
219 .sources = &clkset_vpllsrc,
220 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
223 static struct clk *clkset_sclk_vpll_list[] = {
224 [0] = &clk_vpllsrc.clk,
225 [1] = &clk_fout_vpll,
228 static struct clksrc_sources clkset_sclk_vpll = {
229 .sources = clkset_sclk_vpll_list,
230 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
233 static struct clksrc_clk clk_sclk_vpll = {
238 .sources = &clkset_sclk_vpll,
239 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
242 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
244 return clk_get_rate(clk->parent) / 2;
247 static struct clk_ops clk_hclk_imem_ops = {
248 .get_rate = s5pv210_clk_imem_get_rate,
251 static struct clk init_clocks_disable[] = {
255 .parent = &clk_hclk_dsys.clk,
256 .enable = s5pv210_clk_ip0_ctrl,
261 .parent = &clk_hclk_psys.clk,
262 .enable = s5pv210_clk_ip1_ctrl,
267 .parent = &clk_hclk_psys.clk,
268 .enable = s5pv210_clk_ip1_ctrl,
273 .parent = &clk_hclk_dsys.clk,
274 .enable = s5pv210_clk_ip1_ctrl,
279 .parent = &clk_hclk_psys.clk,
280 .enable = s5pv210_clk_ip1_ctrl,
285 .parent = &clk_hclk_psys.clk,
286 .enable = s5pv210_clk_ip2_ctrl,
291 .parent = &clk_hclk_psys.clk,
292 .enable = s5pv210_clk_ip2_ctrl,
297 .parent = &clk_hclk_psys.clk,
298 .enable = s5pv210_clk_ip2_ctrl,
303 .parent = &clk_hclk_psys.clk,
304 .enable = s5pv210_clk_ip2_ctrl,
309 .parent = &clk_pclk_psys.clk,
310 .enable = s5pv210_clk_ip3_ctrl,
315 .parent = &clk_pclk_psys.clk,
316 .enable = s5pv210_clk_ip3_ctrl,
321 .parent = &clk_pclk_psys.clk,
322 .enable = s5pv210_clk_ip3_ctrl,
327 .parent = &clk_pclk_psys.clk,
328 .enable = s5pv210_clk_ip3_ctrl,
333 .parent = &clk_pclk_psys.clk,
334 .enable = s5pv210_clk_ip3_ctrl,
339 .parent = &clk_pclk_psys.clk,
340 .enable = s5pv210_clk_ip3_ctrl,
345 .parent = &clk_pclk_psys.clk,
346 .enable = s5pv210_clk_ip3_ctrl,
351 .parent = &clk_pclk_psys.clk,
352 .enable = s5pv210_clk_ip3_ctrl,
357 .parent = &clk_pclk_psys.clk,
358 .enable = s5pv210_clk_ip3_ctrl,
363 .parent = &clk_pclk_psys.clk,
364 .enable = s5pv210_clk_ip3_ctrl,
369 .parent = &clk_pclk_psys.clk,
370 .enable = s5pv210_clk_ip3_ctrl,
375 .parent = &clk_pclk_psys.clk,
376 .enable = s5pv210_clk_ip3_ctrl,
382 .enable = s5pv210_clk_ip3_ctrl,
388 .enable = s5pv210_clk_ip3_ctrl,
394 .enable = s5pv210_clk_ip3_ctrl,
399 static struct clk init_clocks[] = {
403 .parent = &clk_hclk_msys.clk,
405 .enable = s5pv210_clk_ip0_ctrl,
406 .ops = &clk_hclk_imem_ops,
410 .parent = &clk_pclk_psys.clk,
411 .enable = s5pv210_clk_ip3_ctrl,
416 .parent = &clk_pclk_psys.clk,
417 .enable = s5pv210_clk_ip3_ctrl,
422 .parent = &clk_pclk_psys.clk,
423 .enable = s5pv210_clk_ip3_ctrl,
428 .parent = &clk_pclk_psys.clk,
429 .enable = s5pv210_clk_ip3_ctrl,
434 static struct clk *clkset_uart_list[] = {
435 [6] = &clk_mout_mpll.clk,
436 [7] = &clk_mout_epll.clk,
439 static struct clksrc_sources clkset_uart = {
440 .sources = clkset_uart_list,
441 .nr_sources = ARRAY_SIZE(clkset_uart_list),
444 static struct clk *clkset_group1_list[] = {
445 [0] = &clk_sclk_a2m.clk,
446 [1] = &clk_mout_mpll.clk,
447 [2] = &clk_mout_epll.clk,
448 [3] = &clk_sclk_vpll.clk,
451 static struct clksrc_sources clkset_group1 = {
452 .sources = clkset_group1_list,
453 .nr_sources = ARRAY_SIZE(clkset_group1_list),
456 static struct clk *clkset_sclk_onenand_list[] = {
457 [0] = &clk_hclk_psys.clk,
458 [1] = &clk_hclk_dsys.clk,
461 static struct clksrc_sources clkset_sclk_onenand = {
462 .sources = clkset_sclk_onenand_list,
463 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
466 static struct clk *clkset_sclk_dac_list[] = {
467 [0] = &clk_sclk_vpll.clk,
468 [1] = &clk_sclk_hdmiphy,
471 static struct clksrc_sources clkset_sclk_dac = {
472 .sources = clkset_sclk_dac_list,
473 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
476 static struct clksrc_clk clk_sclk_dac = {
480 .ctrlbit = (1 << 10),
481 .enable = s5pv210_clk_ip1_ctrl,
483 .sources = &clkset_sclk_dac,
484 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
487 static struct clksrc_clk clk_sclk_pixel = {
489 .name = "sclk_pixel",
491 .parent = &clk_sclk_vpll.clk,
493 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
496 static struct clk *clkset_sclk_hdmi_list[] = {
497 [0] = &clk_sclk_pixel.clk,
498 [1] = &clk_sclk_hdmiphy,
501 static struct clksrc_sources clkset_sclk_hdmi = {
502 .sources = clkset_sclk_hdmi_list,
503 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
506 static struct clksrc_clk clk_sclk_hdmi = {
510 .enable = s5pv210_clk_ip1_ctrl,
511 .ctrlbit = (1 << 11),
513 .sources = &clkset_sclk_hdmi,
514 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
517 static struct clk *clkset_sclk_mixer_list[] = {
518 [0] = &clk_sclk_dac.clk,
519 [1] = &clk_sclk_hdmi.clk,
522 static struct clksrc_sources clkset_sclk_mixer = {
523 .sources = clkset_sclk_mixer_list,
524 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
527 static struct clksrc_clk clksrcs[] = {
533 .sources = &clkset_group1,
534 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
535 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
538 .name = "sclk_onenand",
541 .sources = &clkset_sclk_onenand,
542 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
543 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
549 .enable = s5pv210_clk_ip3_ctrl,
551 .sources = &clkset_uart,
552 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
553 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
556 .name = "sclk_mixer",
558 .enable = s5pv210_clk_ip1_ctrl,
561 .sources = &clkset_sclk_mixer,
562 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
566 /* Clock initialisation code */
567 static struct clksrc_clk *sysclks[] = {
586 void __init_or_cpufreq s5pv210_setup_clocks(void)
588 struct clk *xtal_clk;
590 unsigned long vpllsrc;
591 unsigned long armclk;
592 unsigned long hclk_msys;
593 unsigned long hclk_dsys;
594 unsigned long hclk_psys;
595 unsigned long pclk_msys;
596 unsigned long pclk_dsys;
597 unsigned long pclk_psys;
603 u32 clkdiv0, clkdiv1;
605 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
607 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
608 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
610 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
611 __func__, clkdiv0, clkdiv1);
613 xtal_clk = clk_get(NULL, "xtal");
614 BUG_ON(IS_ERR(xtal_clk));
616 xtal = clk_get_rate(xtal_clk);
619 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
621 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
622 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
623 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
624 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
625 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
627 clk_fout_apll.rate = apll;
628 clk_fout_mpll.rate = mpll;
629 clk_fout_epll.rate = epll;
630 clk_fout_vpll.rate = vpll;
632 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
633 apll, mpll, epll, vpll);
635 armclk = clk_get_rate(&clk_armclk.clk);
636 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
637 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
638 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
639 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
640 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
641 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
643 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
644 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
645 armclk, hclk_msys, hclk_dsys, hclk_psys,
646 pclk_msys, pclk_dsys, pclk_psys);
649 clk_h.rate = hclk_psys;
650 clk_p.rate = pclk_psys;
652 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
653 s3c_set_clksrc(&clksrcs[ptr], true);
656 static struct clk *clks[] __initdata = {
663 void __init s5pv210_register_clocks(void)
669 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
671 printk(KERN_ERR "Failed to register %u clocks\n", ret);
673 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
674 s3c_register_clksrc(sysclks[ptr], 1);
676 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
677 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
679 clkp = init_clocks_disable;
680 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
681 ret = s3c24xx_register_clock(clkp);
683 printk(KERN_ERR "Failed to register clock %s (%d)\n",
686 (clkp->enable)(clkp, 0);