SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74                 .id             = -1,
  75         },
  76         .sources        = &clkset_armclk,
  77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  79 };
  80
  81 static struct clksrc_clk clk_hclk_msys = {
  82         .clk    = {
  83                 .name           = "hclk_msys",
  84                 .id             = -1,
  85                 .parent         = &clk_armclk.clk,
  86         },
  87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  88 };
  89
  90 static struct clksrc_clk clk_pclk_msys = {
  91         .clk    = {
  92                 .name           = "pclk_msys",
  93                 .id             = -1,
  94                 .parent         = &clk_hclk_msys.clk,
  95         },
  96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  97 };
  98
  99 static struct clksrc_clk clk_sclk_a2m = {
 100         .clk    = {
 101                 .name           = "sclk_a2m",
 102                 .id             = -1,
 103                 .parent         = &clk_mout_apll.clk,
 104         },
 105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 106 };
 107
 108 static struct clk *clkset_hclk_sys_list[] = {
 109         [0] = &clk_mout_mpll.clk,
 110         [1] = &clk_sclk_a2m.clk,
 111 };
 112
 113 static struct clksrc_sources clkset_hclk_sys = {
 114         .sources        = clkset_hclk_sys_list,
 115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 116 };
 117
 118 static struct clksrc_clk clk_hclk_dsys = {
 119         .clk    = {
 120                 .name   = "hclk_dsys",
 121                 .id     = -1,
 122         },
 123         .sources        = &clkset_hclk_sys,
 124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 126 };
 127
 128 static struct clksrc_clk clk_hclk_psys = {
 129         .clk    = {
 130                 .name   = "hclk_psys",
 131                 .id     = -1,
 132         },
 133         .sources        = &clkset_hclk_sys,
 134         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 135         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 136 };
 137
 138 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 139 {
 140         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 141 }
 142
 143 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 144 {
 145         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 146 }
 147
 148 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 149 {
 150         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 151 }
 152
 153 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 154 {
 155         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 156 }
 157
 158 static struct clk clk_p83 = {
 159         .name           = "pclk83",
 160         .id             = -1,
 161 };
 162
 163 static struct clk clk_p66 = {
 164         .name           = "pclk66",
 165         .id             = -1,
 166 };
 167
 168 static struct clk *sys_clks[] = {
 169         &clk_p83,
 170         &clk_p66
 171 };
 172
 173 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 174 {
 175         return clk_get_rate(clk->parent) / 2;
 176 }
 177
 178 static struct clk_ops clk_hclk_imem_ops = {
 179         .get_rate       = s5pv210_clk_imem_get_rate,
 180 };
 181
 182 static struct clk init_clocks_disable[] = {
 183         {
 184                 .name           = "rot",
 185                 .id             = -1,
 186                 .parent         = &clk_hclk_dsys.clk,
 187                 .enable         = s5pv210_clk_ip0_ctrl,
 188                 .ctrlbit        = (1<<29),
 189         }, {
 190                 .name           = "otg",
 191                 .id             = -1,
 192                 .parent         = &clk_hclk_psys.clk,
 193                 .enable         = s5pv210_clk_ip1_ctrl,
 194                 .ctrlbit        = (1<<16),
 195         }, {
 196                 .name           = "usb-host",
 197                 .id             = -1,
 198                 .parent         = &clk_hclk_psys.clk,
 199                 .enable         = s5pv210_clk_ip1_ctrl,
 200                 .ctrlbit        = (1<<17),
 201         }, {
 202                 .name           = "lcd",
 203                 .id             = -1,
 204                 .parent         = &clk_hclk_dsys.clk,
 205                 .enable         = s5pv210_clk_ip1_ctrl,
 206                 .ctrlbit        = (1<<0),
 207         }, {
 208                 .name           = "cfcon",
 209                 .id             = 0,
 210                 .parent         = &clk_hclk_psys.clk,
 211                 .enable         = s5pv210_clk_ip1_ctrl,
 212                 .ctrlbit        = (1<<25),
 213         }, {
 214                 .name           = "hsmmc",
 215                 .id             = 0,
 216                 .parent         = &clk_hclk_psys.clk,
 217                 .enable         = s5pv210_clk_ip2_ctrl,
 218                 .ctrlbit        = (1<<16),
 219         }, {
 220                 .name           = "hsmmc",
 221                 .id             = 1,
 222                 .parent         = &clk_hclk_psys.clk,
 223                 .enable         = s5pv210_clk_ip2_ctrl,
 224                 .ctrlbit        = (1<<17),
 225         }, {
 226                 .name           = "hsmmc",
 227                 .id             = 2,
 228                 .parent         = &clk_hclk_psys.clk,
 229                 .enable         = s5pv210_clk_ip2_ctrl,
 230                 .ctrlbit        = (1<<18),
 231         }, {
 232                 .name           = "hsmmc",
 233                 .id             = 3,
 234                 .parent         = &clk_hclk_psys.clk,
 235                 .enable         = s5pv210_clk_ip2_ctrl,
 236                 .ctrlbit        = (1<<19),
 237         }, {
 238                 .name           = "systimer",
 239                 .id             = -1,
 240                 .parent         = &clk_p66,
 241                 .enable         = s5pv210_clk_ip3_ctrl,
 242                 .ctrlbit        = (1<<16),
 243         }, {
 244                 .name           = "watchdog",
 245                 .id             = -1,
 246                 .parent         = &clk_p66,
 247                 .enable         = s5pv210_clk_ip3_ctrl,
 248                 .ctrlbit        = (1<<22),
 249         }, {
 250                 .name           = "rtc",
 251                 .id             = -1,
 252                 .parent         = &clk_p66,
 253                 .enable         = s5pv210_clk_ip3_ctrl,
 254                 .ctrlbit        = (1<<15),
 255         }, {
 256                 .name           = "i2c",
 257                 .id             = 0,
 258                 .parent         = &clk_p66,
 259                 .enable         = s5pv210_clk_ip3_ctrl,
 260                 .ctrlbit        = (1<<7),
 261         }, {
 262                 .name           = "i2c",
 263                 .id             = 1,
 264                 .parent         = &clk_p66,
 265                 .enable         = s5pv210_clk_ip3_ctrl,
 266                 .ctrlbit        = (1<<8),
 267         }, {
 268                 .name           = "i2c",
 269                 .id             = 2,
 270                 .parent         = &clk_p66,
 271                 .enable         = s5pv210_clk_ip3_ctrl,
 272                 .ctrlbit        = (1<<9),
 273         }, {
 274                 .name           = "spi",
 275                 .id             = 0,
 276                 .parent         = &clk_p66,
 277                 .enable         = s5pv210_clk_ip3_ctrl,
 278                 .ctrlbit        = (1<<12),
 279         }, {
 280                 .name           = "spi",
 281                 .id             = 1,
 282                 .parent         = &clk_p66,
 283                 .enable         = s5pv210_clk_ip3_ctrl,
 284                 .ctrlbit        = (1<<13),
 285         }, {
 286                 .name           = "spi",
 287                 .id             = 2,
 288                 .parent         = &clk_p66,
 289                 .enable         = s5pv210_clk_ip3_ctrl,
 290                 .ctrlbit        = (1<<14),
 291         }, {
 292                 .name           = "timers",
 293                 .id             = -1,
 294                 .parent         = &clk_p66,
 295                 .enable         = s5pv210_clk_ip3_ctrl,
 296                 .ctrlbit        = (1<<23),
 297         }, {
 298                 .name           = "adc",
 299                 .id             = -1,
 300                 .parent         = &clk_p66,
 301                 .enable         = s5pv210_clk_ip3_ctrl,
 302                 .ctrlbit        = (1<<24),
 303         }, {
 304                 .name           = "keypad",
 305                 .id             = -1,
 306                 .parent         = &clk_p66,
 307                 .enable         = s5pv210_clk_ip3_ctrl,
 308                 .ctrlbit        = (1<<21),
 309         }, {
 310                 .name           = "i2s_v50",
 311                 .id             = 0,
 312                 .parent         = &clk_p,
 313                 .enable         = s5pv210_clk_ip3_ctrl,
 314                 .ctrlbit        = (1<<4),
 315         }, {
 316                 .name           = "i2s_v32",
 317                 .id             = 0,
 318                 .parent         = &clk_p,
 319                 .enable         = s5pv210_clk_ip3_ctrl,
 320                 .ctrlbit        = (1<<4),
 321         }, {
 322                 .name           = "i2s_v32",
 323                 .id             = 1,
 324                 .parent         = &clk_p,
 325                 .enable         = s5pv210_clk_ip3_ctrl,
 326                 .ctrlbit        = (1<<4),
 327         }
 328 };
 329
 330 static struct clk init_clocks[] = {
 331         {
 332                 .name           = "hclk_imem",
 333                 .id             = -1,
 334                 .parent         = &clk_hclk_msys.clk,
 335                 .ctrlbit        = (1 << 5),
 336                 .enable         = s5pv210_clk_ip0_ctrl,
 337                 .ops            = &clk_hclk_imem_ops,
 338         }, {
 339                 .name           = "uart",
 340                 .id             = 0,
 341                 .parent         = &clk_p66,
 342                 .enable         = s5pv210_clk_ip3_ctrl,
 343                 .ctrlbit        = (1<<7),
 344         }, {
 345                 .name           = "uart",
 346                 .id             = 1,
 347                 .parent         = &clk_p66,
 348                 .enable         = s5pv210_clk_ip3_ctrl,
 349                 .ctrlbit        = (1<<8),
 350         }, {
 351                 .name           = "uart",
 352                 .id             = 2,
 353                 .parent         = &clk_p66,
 354                 .enable         = s5pv210_clk_ip3_ctrl,
 355                 .ctrlbit        = (1<<9),
 356         }, {
 357                 .name           = "uart",
 358                 .id             = 3,
 359                 .parent         = &clk_p66,
 360                 .enable         = s5pv210_clk_ip3_ctrl,
 361                 .ctrlbit        = (1<<10),
 362         },
 363 };
 364
 365 static struct clk *clkset_uart_list[] = {
 366         [6] = &clk_mout_mpll.clk,
 367         [7] = &clk_mout_epll.clk,
 368 };
 369
 370 static struct clksrc_sources clkset_uart = {
 371         .sources        = clkset_uart_list,
 372         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 373 };
 374
 375 static struct clksrc_clk clksrcs[] = {
 376         {
 377                 .clk    = {
 378                         .name           = "uclk1",
 379                         .id             = -1,
 380                         .ctrlbit        = (1<<17),
 381                         .enable         = s5pv210_clk_ip3_ctrl,
 382                 },
 383                 .sources = &clkset_uart,
 384                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 385                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 386         }
 387 };
 388
 389 /* Clock initialisation code */
 390 static struct clksrc_clk *sysclks[] = {
 391         &clk_mout_apll,
 392         &clk_mout_epll,
 393         &clk_mout_mpll,
 394         &clk_armclk,
 395         &clk_hclk_msys,
 396         &clk_sclk_a2m,
 397         &clk_hclk_dsys,
 398         &clk_hclk_psys,
 399         &clk_pclk_msys,
 400 };
 401
 402 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 403
 404 void __init_or_cpufreq s5pv210_setup_clocks(void)
 405 {
 406         struct clk *xtal_clk;
 407         unsigned long xtal;
 408         unsigned long armclk;
 409         unsigned long hclk_msys;
 410         unsigned long hclk_dsys;
 411         unsigned long hclk_psys;
 412         unsigned long pclk_msys;
 413         unsigned long pclk83;
 414         unsigned long pclk66;
 415         unsigned long apll;
 416         unsigned long mpll;
 417         unsigned long epll;
 418         unsigned int ptr;
 419         u32 clkdiv0, clkdiv1;
 420
 421         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 422
 423         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 424         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 425
 426         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 427                                 __func__, clkdiv0, clkdiv1);
 428
 429         xtal_clk = clk_get(NULL, "xtal");
 430         BUG_ON(IS_ERR(xtal_clk));
 431
 432         xtal = clk_get_rate(xtal_clk);
 433         clk_put(xtal_clk);
 434
 435         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 436
 437         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 438         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 439         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 440
 441         clk_fout_apll.rate = apll;
 442         clk_fout_mpll.rate = mpll;
 443         clk_fout_epll.rate = epll;
 444
 445         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
 446                         apll, mpll, epll);
 447
 448         armclk = clk_get_rate(&clk_armclk.clk);
 449         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
 450         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
 451         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
 452         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
 453         pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
 454         pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
 455
 456         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
 457                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 458                         armclk, hclk_msys, hclk_dsys, hclk_psys,
 459                         pclk_msys, pclk83, pclk66);
 460
 461         clk_f.rate = armclk;
 462         clk_h.rate = hclk_psys;
 463         clk_p.rate = pclk66;
 464         clk_p66.rate = pclk66;
 465         clk_p83.rate = pclk83;
 466
 467         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 468                 s3c_set_clksrc(&clksrcs[ptr], true);
 469 }
 470
 471 static struct clk *clks[] __initdata = {
 472 };
 473
 474 void __init s5pv210_register_clocks(void)
 475 {
 476         struct clk *clkp;
 477         int ret;
 478         int ptr;
 479
 480         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 481         if (ret > 0)
 482                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 483
 484         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 485                 s3c_register_clksrc(sysclks[ptr], 1);
 486
 487         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 488         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 489
 490         ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
 491         if (ret > 0)
 492                 printk(KERN_ERR "Failed to register system clocks\n");
 493
 494         clkp = init_clocks_disable;
 495         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 496                 ret = s3c24xx_register_clock(clkp);
 497                 if (ret < 0) {
 498                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 499                                clkp->name, ret);
 500                 }
 501                 (clkp->enable)(clkp, 0);
 502         }
 503
 504         s3c_pwmclk_init();
 505 }