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   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74                 .id             = -1,
  75         },
  76         .sources        = &clkset_armclk,
  77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  79 };
  80
  81 static struct clksrc_clk clk_hclk_msys = {
  82         .clk    = {
  83                 .name           = "hclk_msys",
  84                 .id             = -1,
  85                 .parent         = &clk_armclk.clk,
  86         },
  87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  88 };
  89
  90 static struct clksrc_clk clk_pclk_msys = {
  91         .clk    = {
  92                 .name           = "pclk_msys",
  93                 .id             = -1,
  94                 .parent         = &clk_hclk_msys.clk,
  95         },
  96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  97 };
  98
  99 static struct clksrc_clk clk_sclk_a2m = {
 100         .clk    = {
 101                 .name           = "sclk_a2m",
 102                 .id             = -1,
 103                 .parent         = &clk_mout_apll.clk,
 104         },
 105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 106 };
 107
 108 static struct clk *clkset_hclk_sys_list[] = {
 109         [0] = &clk_mout_mpll.clk,
 110         [1] = &clk_sclk_a2m.clk,
 111 };
 112
 113 static struct clksrc_sources clkset_hclk_sys = {
 114         .sources        = clkset_hclk_sys_list,
 115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 116 };
 117
 118 static struct clksrc_clk clk_hclk_dsys = {
 119         .clk    = {
 120                 .name   = "hclk_dsys",
 121                 .id     = -1,
 122         },
 123         .sources        = &clkset_hclk_sys,
 124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 126 };
 127
 128 static struct clksrc_clk clk_hclk_psys = {
 129         .clk    = {
 130                 .name   = "hclk_psys",
 131                 .id     = -1,
 132         },
 133         .sources        = &clkset_hclk_sys,
 134         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 135         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 136 };
 137
 138 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 139 {
 140         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 141 }
 142
 143 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 144 {
 145         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 146 }
 147
 148 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 149 {
 150         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 151 }
 152
 153 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 154 {
 155         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 156 }
 157
 158 static struct clk clk_h100 = {
 159         .name           = "hclk100",
 160         .id             = -1,
 161 };
 162
 163 static struct clk clk_p83 = {
 164         .name           = "pclk83",
 165         .id             = -1,
 166 };
 167
 168 static struct clk clk_p66 = {
 169         .name           = "pclk66",
 170         .id             = -1,
 171 };
 172
 173 static struct clk *sys_clks[] = {
 174         &clk_h100,
 175         &clk_p83,
 176         &clk_p66
 177 };
 178
 179 static struct clk init_clocks_disable[] = {
 180         {
 181                 .name           = "rot",
 182                 .id             = -1,
 183                 .parent         = &clk_hclk_dsys.clk,
 184                 .enable         = s5pv210_clk_ip0_ctrl,
 185                 .ctrlbit        = (1<<29),
 186         }, {
 187                 .name           = "otg",
 188                 .id             = -1,
 189                 .parent         = &clk_hclk_psys.clk,
 190                 .enable         = s5pv210_clk_ip1_ctrl,
 191                 .ctrlbit        = (1<<16),
 192         }, {
 193                 .name           = "usb-host",
 194                 .id             = -1,
 195                 .parent         = &clk_hclk_psys.clk,
 196                 .enable         = s5pv210_clk_ip1_ctrl,
 197                 .ctrlbit        = (1<<17),
 198         }, {
 199                 .name           = "lcd",
 200                 .id             = -1,
 201                 .parent         = &clk_hclk_dsys.clk,
 202                 .enable         = s5pv210_clk_ip1_ctrl,
 203                 .ctrlbit        = (1<<0),
 204         }, {
 205                 .name           = "cfcon",
 206                 .id             = 0,
 207                 .parent         = &clk_hclk_psys.clk,
 208                 .enable         = s5pv210_clk_ip1_ctrl,
 209                 .ctrlbit        = (1<<25),
 210         }, {
 211                 .name           = "hsmmc",
 212                 .id             = 0,
 213                 .parent         = &clk_hclk_psys.clk,
 214                 .enable         = s5pv210_clk_ip2_ctrl,
 215                 .ctrlbit        = (1<<16),
 216         }, {
 217                 .name           = "hsmmc",
 218                 .id             = 1,
 219                 .parent         = &clk_hclk_psys.clk,
 220                 .enable         = s5pv210_clk_ip2_ctrl,
 221                 .ctrlbit        = (1<<17),
 222         }, {
 223                 .name           = "hsmmc",
 224                 .id             = 2,
 225                 .parent         = &clk_hclk_psys.clk,
 226                 .enable         = s5pv210_clk_ip2_ctrl,
 227                 .ctrlbit        = (1<<18),
 228         }, {
 229                 .name           = "hsmmc",
 230                 .id             = 3,
 231                 .parent         = &clk_hclk_psys.clk,
 232                 .enable         = s5pv210_clk_ip2_ctrl,
 233                 .ctrlbit        = (1<<19),
 234         }, {
 235                 .name           = "systimer",
 236                 .id             = -1,
 237                 .parent         = &clk_p66,
 238                 .enable         = s5pv210_clk_ip3_ctrl,
 239                 .ctrlbit        = (1<<16),
 240         }, {
 241                 .name           = "watchdog",
 242                 .id             = -1,
 243                 .parent         = &clk_p66,
 244                 .enable         = s5pv210_clk_ip3_ctrl,
 245                 .ctrlbit        = (1<<22),
 246         }, {
 247                 .name           = "rtc",
 248                 .id             = -1,
 249                 .parent         = &clk_p66,
 250                 .enable         = s5pv210_clk_ip3_ctrl,
 251                 .ctrlbit        = (1<<15),
 252         }, {
 253                 .name           = "i2c",
 254                 .id             = 0,
 255                 .parent         = &clk_p66,
 256                 .enable         = s5pv210_clk_ip3_ctrl,
 257                 .ctrlbit        = (1<<7),
 258         }, {
 259                 .name           = "i2c",
 260                 .id             = 1,
 261                 .parent         = &clk_p66,
 262                 .enable         = s5pv210_clk_ip3_ctrl,
 263                 .ctrlbit        = (1<<8),
 264         }, {
 265                 .name           = "i2c",
 266                 .id             = 2,
 267                 .parent         = &clk_p66,
 268                 .enable         = s5pv210_clk_ip3_ctrl,
 269                 .ctrlbit        = (1<<9),
 270         }, {
 271                 .name           = "spi",
 272                 .id             = 0,
 273                 .parent         = &clk_p66,
 274                 .enable         = s5pv210_clk_ip3_ctrl,
 275                 .ctrlbit        = (1<<12),
 276         }, {
 277                 .name           = "spi",
 278                 .id             = 1,
 279                 .parent         = &clk_p66,
 280                 .enable         = s5pv210_clk_ip3_ctrl,
 281                 .ctrlbit        = (1<<13),
 282         }, {
 283                 .name           = "spi",
 284                 .id             = 2,
 285                 .parent         = &clk_p66,
 286                 .enable         = s5pv210_clk_ip3_ctrl,
 287                 .ctrlbit        = (1<<14),
 288         }, {
 289                 .name           = "timers",
 290                 .id             = -1,
 291                 .parent         = &clk_p66,
 292                 .enable         = s5pv210_clk_ip3_ctrl,
 293                 .ctrlbit        = (1<<23),
 294         }, {
 295                 .name           = "adc",
 296                 .id             = -1,
 297                 .parent         = &clk_p66,
 298                 .enable         = s5pv210_clk_ip3_ctrl,
 299                 .ctrlbit        = (1<<24),
 300         }, {
 301                 .name           = "keypad",
 302                 .id             = -1,
 303                 .parent         = &clk_p66,
 304                 .enable         = s5pv210_clk_ip3_ctrl,
 305                 .ctrlbit        = (1<<21),
 306         }, {
 307                 .name           = "i2s_v50",
 308                 .id             = 0,
 309                 .parent         = &clk_p,
 310                 .enable         = s5pv210_clk_ip3_ctrl,
 311                 .ctrlbit        = (1<<4),
 312         }, {
 313                 .name           = "i2s_v32",
 314                 .id             = 0,
 315                 .parent         = &clk_p,
 316                 .enable         = s5pv210_clk_ip3_ctrl,
 317                 .ctrlbit        = (1<<4),
 318         }, {
 319                 .name           = "i2s_v32",
 320                 .id             = 1,
 321                 .parent         = &clk_p,
 322                 .enable         = s5pv210_clk_ip3_ctrl,
 323                 .ctrlbit        = (1<<4),
 324         }
 325 };
 326
 327 static struct clk init_clocks[] = {
 328         {
 329                 .name           = "uart",
 330                 .id             = 0,
 331                 .parent         = &clk_p66,
 332                 .enable         = s5pv210_clk_ip3_ctrl,
 333                 .ctrlbit        = (1<<7),
 334         }, {
 335                 .name           = "uart",
 336                 .id             = 1,
 337                 .parent         = &clk_p66,
 338                 .enable         = s5pv210_clk_ip3_ctrl,
 339                 .ctrlbit        = (1<<8),
 340         }, {
 341                 .name           = "uart",
 342                 .id             = 2,
 343                 .parent         = &clk_p66,
 344                 .enable         = s5pv210_clk_ip3_ctrl,
 345                 .ctrlbit        = (1<<9),
 346         }, {
 347                 .name           = "uart",
 348                 .id             = 3,
 349                 .parent         = &clk_p66,
 350                 .enable         = s5pv210_clk_ip3_ctrl,
 351                 .ctrlbit        = (1<<10),
 352         },
 353 };
 354
 355 static struct clk *clkset_uart_list[] = {
 356         [6] = &clk_mout_mpll.clk,
 357         [7] = &clk_mout_epll.clk,
 358 };
 359
 360 static struct clksrc_sources clkset_uart = {
 361         .sources        = clkset_uart_list,
 362         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 363 };
 364
 365 static struct clksrc_clk clksrcs[] = {
 366         {
 367                 .clk    = {
 368                         .name           = "uclk1",
 369                         .id             = -1,
 370                         .ctrlbit        = (1<<17),
 371                         .enable         = s5pv210_clk_ip3_ctrl,
 372                 },
 373                 .sources = &clkset_uart,
 374                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 375                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 376         }
 377 };
 378
 379 /* Clock initialisation code */
 380 static struct clksrc_clk *sysclks[] = {
 381         &clk_mout_apll,
 382         &clk_mout_epll,
 383         &clk_mout_mpll,
 384         &clk_armclk,
 385         &clk_hclk_msys,
 386         &clk_sclk_a2m,
 387         &clk_hclk_dsys,
 388         &clk_hclk_psys,
 389         &clk_pclk_msys,
 390 };
 391
 392 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
 393
 394 void __init_or_cpufreq s5pv210_setup_clocks(void)
 395 {
 396         struct clk *xtal_clk;
 397         unsigned long xtal;
 398         unsigned long armclk;
 399         unsigned long hclk_msys;
 400         unsigned long hclk_dsys;
 401         unsigned long hclk_psys;
 402         unsigned long pclk_msys;
 403         unsigned long pclk83;
 404         unsigned long pclk66;
 405         unsigned long apll;
 406         unsigned long mpll;
 407         unsigned long epll;
 408         unsigned int ptr;
 409         u32 clkdiv0, clkdiv1;
 410
 411         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 412
 413         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 414         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 415
 416         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 417                                 __func__, clkdiv0, clkdiv1);
 418
 419         xtal_clk = clk_get(NULL, "xtal");
 420         BUG_ON(IS_ERR(xtal_clk));
 421
 422         xtal = clk_get_rate(xtal_clk);
 423         clk_put(xtal_clk);
 424
 425         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 426
 427         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 428         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 429         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 430
 431         clk_fout_apll.rate = apll;
 432         clk_fout_mpll.rate = mpll;
 433         clk_fout_epll.rate = epll;
 434
 435         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
 436                         apll, mpll, epll);
 437
 438         armclk = clk_get_rate(&clk_armclk.clk);
 439         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
 440         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
 441         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
 442         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
 443         pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
 444         pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
 445
 446         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
 447                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 448                         armclk, hclk_msys, hclk_dsys, hclk_psys,
 449                         pclk_msys, pclk83, pclk66);
 450
 451         clk_f.rate = armclk;
 452         clk_h.rate = hclk_psys;
 453         clk_p.rate = pclk66;
 454         clk_p66.rate = pclk66;
 455         clk_p83.rate = pclk83;
 456
 457         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 458                 s3c_set_clksrc(&clksrcs[ptr], true);
 459 }
 460
 461 static struct clk *clks[] __initdata = {
 462 };
 463
 464 void __init s5pv210_register_clocks(void)
 465 {
 466         struct clk *clkp;
 467         int ret;
 468         int ptr;
 469
 470         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 471         if (ret > 0)
 472                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 473
 474         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 475                 s3c_register_clksrc(sysclks[ptr], 1);
 476
 477         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 478         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 479
 480         ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
 481         if (ret > 0)
 482                 printk(KERN_ERR "Failed to register system clocks\n");
 483
 484         clkp = init_clocks_disable;
 485         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 486                 ret = s3c24xx_register_clock(clkp);
 487                 if (ret < 0) {
 488                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 489                                clkp->name, ret);
 490                 }
 491                 (clkp->enable)(clkp, 0);
 492         }
 493
 494         s3c_pwmclk_init();
 495 }