1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static struct clksrc_clk clk_mout_apll = {
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
61 static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
66 static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
71 static struct clksrc_clk clk_armclk = {
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
81 static struct clksrc_clk clk_hclk_msys = {
85 .parent = &clk_armclk.clk,
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
90 static struct clksrc_clk clk_pclk_msys = {
94 .parent = &clk_hclk_msys.clk,
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
99 static struct clksrc_clk clk_sclk_a2m = {
103 .parent = &clk_mout_apll.clk,
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
108 static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
113 static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
118 static struct clksrc_clk clk_hclk_dsys = {
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
128 static struct clksrc_clk clk_hclk_psys = {
133 .sources = &clkset_hclk_sys,
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
135 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
138 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
140 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
143 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
145 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
148 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
150 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
153 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
155 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
158 static struct clk clk_h100 = {
163 static struct clk clk_p83 = {
168 static struct clk clk_p66 = {
173 static struct clk *sys_clks[] = {
179 static struct clk init_clocks_disable[] = {
183 .parent = &clk_hclk_dsys.clk,
184 .enable = s5pv210_clk_ip0_ctrl,
189 .parent = &clk_hclk_psys.clk,
190 .enable = s5pv210_clk_ip1_ctrl,
195 .parent = &clk_hclk_psys.clk,
196 .enable = s5pv210_clk_ip1_ctrl,
201 .parent = &clk_hclk_dsys.clk,
202 .enable = s5pv210_clk_ip1_ctrl,
207 .parent = &clk_hclk_psys.clk,
208 .enable = s5pv210_clk_ip1_ctrl,
213 .parent = &clk_hclk_psys.clk,
214 .enable = s5pv210_clk_ip2_ctrl,
219 .parent = &clk_hclk_psys.clk,
220 .enable = s5pv210_clk_ip2_ctrl,
225 .parent = &clk_hclk_psys.clk,
226 .enable = s5pv210_clk_ip2_ctrl,
231 .parent = &clk_hclk_psys.clk,
232 .enable = s5pv210_clk_ip2_ctrl,
238 .enable = s5pv210_clk_ip3_ctrl,
244 .enable = s5pv210_clk_ip3_ctrl,
250 .enable = s5pv210_clk_ip3_ctrl,
256 .enable = s5pv210_clk_ip3_ctrl,
262 .enable = s5pv210_clk_ip3_ctrl,
268 .enable = s5pv210_clk_ip3_ctrl,
274 .enable = s5pv210_clk_ip3_ctrl,
280 .enable = s5pv210_clk_ip3_ctrl,
286 .enable = s5pv210_clk_ip3_ctrl,
292 .enable = s5pv210_clk_ip3_ctrl,
298 .enable = s5pv210_clk_ip3_ctrl,
304 .enable = s5pv210_clk_ip3_ctrl,
310 .enable = s5pv210_clk_ip3_ctrl,
316 .enable = s5pv210_clk_ip3_ctrl,
322 .enable = s5pv210_clk_ip3_ctrl,
327 static struct clk init_clocks[] = {
332 .enable = s5pv210_clk_ip3_ctrl,
338 .enable = s5pv210_clk_ip3_ctrl,
344 .enable = s5pv210_clk_ip3_ctrl,
350 .enable = s5pv210_clk_ip3_ctrl,
355 static struct clk *clkset_uart_list[] = {
356 [6] = &clk_mout_mpll.clk,
357 [7] = &clk_mout_epll.clk,
360 static struct clksrc_sources clkset_uart = {
361 .sources = clkset_uart_list,
362 .nr_sources = ARRAY_SIZE(clkset_uart_list),
365 static struct clksrc_clk clksrcs[] = {
371 .enable = s5pv210_clk_ip3_ctrl,
373 .sources = &clkset_uart,
374 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
375 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
379 /* Clock initialisation code */
380 static struct clksrc_clk *sysclks[] = {
392 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
394 void __init_or_cpufreq s5pv210_setup_clocks(void)
396 struct clk *xtal_clk;
398 unsigned long armclk;
399 unsigned long hclk_msys;
400 unsigned long hclk_dsys;
401 unsigned long hclk_psys;
402 unsigned long pclk_msys;
403 unsigned long pclk83;
404 unsigned long pclk66;
409 u32 clkdiv0, clkdiv1;
411 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
413 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
414 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
416 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
417 __func__, clkdiv0, clkdiv1);
419 xtal_clk = clk_get(NULL, "xtal");
420 BUG_ON(IS_ERR(xtal_clk));
422 xtal = clk_get_rate(xtal_clk);
425 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
427 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
428 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
429 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
431 clk_fout_apll.rate = apll;
432 clk_fout_mpll.rate = mpll;
433 clk_fout_epll.rate = epll;
435 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
438 armclk = clk_get_rate(&clk_armclk.clk);
439 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
440 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
441 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
442 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
443 pclk83 = hclk_dsys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
444 pclk66 = hclk_psys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
446 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
447 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
448 armclk, hclk_msys, hclk_dsys, hclk_psys,
449 pclk_msys, pclk83, pclk66);
452 clk_h.rate = hclk_psys;
454 clk_p66.rate = pclk66;
455 clk_p83.rate = pclk83;
457 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
458 s3c_set_clksrc(&clksrcs[ptr], true);
461 static struct clk *clks[] __initdata = {
464 void __init s5pv210_register_clocks(void)
470 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
472 printk(KERN_ERR "Failed to register %u clocks\n", ret);
474 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
475 s3c_register_clksrc(sysclks[ptr], 1);
477 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
478 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
480 ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
482 printk(KERN_ERR "Failed to register system clocks\n");
484 clkp = init_clocks_disable;
485 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
486 ret = s3c24xx_register_clock(clkp);
488 printk(KERN_ERR "Failed to register clock %s (%d)\n",
491 (clkp->enable)(clkp, 0);