SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74                 .id             = -1,
  75         },
  76         .sources        = &clkset_armclk,
  77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  79 };
  80
  81 static struct clksrc_clk clk_hclk_msys = {
  82         .clk    = {
  83                 .name           = "hclk_msys",
  84                 .id             = -1,
  85                 .parent         = &clk_armclk.clk,
  86         },
  87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  88 };
  89
  90 static struct clksrc_clk clk_pclk_msys = {
  91         .clk    = {
  92                 .name           = "pclk_msys",
  93                 .id             = -1,
  94                 .parent         = &clk_hclk_msys.clk,
  95         },
  96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  97 };
  98
  99 static struct clksrc_clk clk_sclk_a2m = {
 100         .clk    = {
 101                 .name           = "sclk_a2m",
 102                 .id             = -1,
 103                 .parent         = &clk_mout_apll.clk,
 104         },
 105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 106 };
 107
 108 static struct clk *clkset_hclk_sys_list[] = {
 109         [0] = &clk_mout_mpll.clk,
 110         [1] = &clk_sclk_a2m.clk,
 111 };
 112
 113 static struct clksrc_sources clkset_hclk_sys = {
 114         .sources        = clkset_hclk_sys_list,
 115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 116 };
 117
 118 static struct clksrc_clk clk_hclk_dsys = {
 119         .clk    = {
 120                 .name   = "hclk_dsys",
 121                 .id     = -1,
 122         },
 123         .sources        = &clkset_hclk_sys,
 124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 126 };
 127
 128 static struct clksrc_clk clk_pclk_dsys = {
 129         .clk    = {
 130                 .name   = "pclk_dsys",
 131                 .id     = -1,
 132                 .parent = &clk_hclk_dsys.clk,
 133         },
 134         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 135 };
 136
 137 static struct clksrc_clk clk_hclk_psys = {
 138         .clk    = {
 139                 .name   = "hclk_psys",
 140                 .id     = -1,
 141         },
 142         .sources        = &clkset_hclk_sys,
 143         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 145 };
 146
 147 static struct clksrc_clk clk_pclk_psys = {
 148         .clk    = {
 149                 .name   = "pclk_psys",
 150                 .id     = -1,
 151                 .parent = &clk_hclk_psys.clk,
 152         },
 153         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 154 };
 155
 156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 159 }
 160
 161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 164 }
 165
 166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 169 }
 170
 171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 174 }
 175
 176 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 179 }
 180
 181 static struct clk clk_sclk_hdmi27m = {
 182         .name           = "sclk_hdmi27m",
 183         .id             = -1,
 184         .rate           = 27000000,
 185 };
 186
 187 static struct clk clk_sclk_hdmiphy = {
 188         .name           = "sclk_hdmiphy",
 189         .id             = -1,
 190 };
 191
 192 static struct clk clk_sclk_usbphy0 = {
 193         .name           = "sclk_usbphy0",
 194         .id             = -1,
 195 };
 196
 197 static struct clk clk_sclk_usbphy1 = {
 198         .name           = "sclk_usbphy1",
 199         .id             = -1,
 200 };
 201
 202 static struct clk *clkset_vpllsrc_list[] = {
 203         [0] = &clk_fin_vpll,
 204         [1] = &clk_sclk_hdmi27m,
 205 };
 206
 207 static struct clksrc_sources clkset_vpllsrc = {
 208         .sources        = clkset_vpllsrc_list,
 209         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 210 };
 211
 212 static struct clksrc_clk clk_vpllsrc = {
 213         .clk    = {
 214                 .name           = "vpll_src",
 215                 .id             = -1,
 216                 .enable         = s5pv210_clk_mask0_ctrl,
 217                 .ctrlbit        = (1 << 7),
 218         },
 219         .sources        = &clkset_vpllsrc,
 220         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 221 };
 222
 223 static struct clk *clkset_sclk_vpll_list[] = {
 224         [0] = &clk_vpllsrc.clk,
 225         [1] = &clk_fout_vpll,
 226 };
 227
 228 static struct clksrc_sources clkset_sclk_vpll = {
 229         .sources        = clkset_sclk_vpll_list,
 230         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 231 };
 232
 233 static struct clksrc_clk clk_sclk_vpll = {
 234         .clk    = {
 235                 .name           = "sclk_vpll",
 236                 .id             = -1,
 237         },
 238         .sources        = &clkset_sclk_vpll,
 239         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 240 };
 241
 242 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 243 {
 244         return clk_get_rate(clk->parent) / 2;
 245 }
 246
 247 static struct clk_ops clk_hclk_imem_ops = {
 248         .get_rate       = s5pv210_clk_imem_get_rate,
 249 };
 250
 251 static struct clk init_clocks_disable[] = {
 252         {
 253                 .name           = "rot",
 254                 .id             = -1,
 255                 .parent         = &clk_hclk_dsys.clk,
 256                 .enable         = s5pv210_clk_ip0_ctrl,
 257                 .ctrlbit        = (1<<29),
 258         }, {
 259                 .name           = "otg",
 260                 .id             = -1,
 261                 .parent         = &clk_hclk_psys.clk,
 262                 .enable         = s5pv210_clk_ip1_ctrl,
 263                 .ctrlbit        = (1<<16),
 264         }, {
 265                 .name           = "usb-host",
 266                 .id             = -1,
 267                 .parent         = &clk_hclk_psys.clk,
 268                 .enable         = s5pv210_clk_ip1_ctrl,
 269                 .ctrlbit        = (1<<17),
 270         }, {
 271                 .name           = "lcd",
 272                 .id             = -1,
 273                 .parent         = &clk_hclk_dsys.clk,
 274                 .enable         = s5pv210_clk_ip1_ctrl,
 275                 .ctrlbit        = (1<<0),
 276         }, {
 277                 .name           = "cfcon",
 278                 .id             = 0,
 279                 .parent         = &clk_hclk_psys.clk,
 280                 .enable         = s5pv210_clk_ip1_ctrl,
 281                 .ctrlbit        = (1<<25),
 282         }, {
 283                 .name           = "hsmmc",
 284                 .id             = 0,
 285                 .parent         = &clk_hclk_psys.clk,
 286                 .enable         = s5pv210_clk_ip2_ctrl,
 287                 .ctrlbit        = (1<<16),
 288         }, {
 289                 .name           = "hsmmc",
 290                 .id             = 1,
 291                 .parent         = &clk_hclk_psys.clk,
 292                 .enable         = s5pv210_clk_ip2_ctrl,
 293                 .ctrlbit        = (1<<17),
 294         }, {
 295                 .name           = "hsmmc",
 296                 .id             = 2,
 297                 .parent         = &clk_hclk_psys.clk,
 298                 .enable         = s5pv210_clk_ip2_ctrl,
 299                 .ctrlbit        = (1<<18),
 300         }, {
 301                 .name           = "hsmmc",
 302                 .id             = 3,
 303                 .parent         = &clk_hclk_psys.clk,
 304                 .enable         = s5pv210_clk_ip2_ctrl,
 305                 .ctrlbit        = (1<<19),
 306         }, {
 307                 .name           = "systimer",
 308                 .id             = -1,
 309                 .parent         = &clk_pclk_psys.clk,
 310                 .enable         = s5pv210_clk_ip3_ctrl,
 311                 .ctrlbit        = (1<<16),
 312         }, {
 313                 .name           = "watchdog",
 314                 .id             = -1,
 315                 .parent         = &clk_pclk_psys.clk,
 316                 .enable         = s5pv210_clk_ip3_ctrl,
 317                 .ctrlbit        = (1<<22),
 318         }, {
 319                 .name           = "rtc",
 320                 .id             = -1,
 321                 .parent         = &clk_pclk_psys.clk,
 322                 .enable         = s5pv210_clk_ip3_ctrl,
 323                 .ctrlbit        = (1<<15),
 324         }, {
 325                 .name           = "i2c",
 326                 .id             = 0,
 327                 .parent         = &clk_pclk_psys.clk,
 328                 .enable         = s5pv210_clk_ip3_ctrl,
 329                 .ctrlbit        = (1<<7),
 330         }, {
 331                 .name           = "i2c",
 332                 .id             = 1,
 333                 .parent         = &clk_pclk_psys.clk,
 334                 .enable         = s5pv210_clk_ip3_ctrl,
 335                 .ctrlbit        = (1<<8),
 336         }, {
 337                 .name           = "i2c",
 338                 .id             = 2,
 339                 .parent         = &clk_pclk_psys.clk,
 340                 .enable         = s5pv210_clk_ip3_ctrl,
 341                 .ctrlbit        = (1<<9),
 342         }, {
 343                 .name           = "spi",
 344                 .id             = 0,
 345                 .parent         = &clk_pclk_psys.clk,
 346                 .enable         = s5pv210_clk_ip3_ctrl,
 347                 .ctrlbit        = (1<<12),
 348         }, {
 349                 .name           = "spi",
 350                 .id             = 1,
 351                 .parent         = &clk_pclk_psys.clk,
 352                 .enable         = s5pv210_clk_ip3_ctrl,
 353                 .ctrlbit        = (1<<13),
 354         }, {
 355                 .name           = "spi",
 356                 .id             = 2,
 357                 .parent         = &clk_pclk_psys.clk,
 358                 .enable         = s5pv210_clk_ip3_ctrl,
 359                 .ctrlbit        = (1<<14),
 360         }, {
 361                 .name           = "timers",
 362                 .id             = -1,
 363                 .parent         = &clk_pclk_psys.clk,
 364                 .enable         = s5pv210_clk_ip3_ctrl,
 365                 .ctrlbit        = (1<<23),
 366         }, {
 367                 .name           = "adc",
 368                 .id             = -1,
 369                 .parent         = &clk_pclk_psys.clk,
 370                 .enable         = s5pv210_clk_ip3_ctrl,
 371                 .ctrlbit        = (1<<24),
 372         }, {
 373                 .name           = "keypad",
 374                 .id             = -1,
 375                 .parent         = &clk_pclk_psys.clk,
 376                 .enable         = s5pv210_clk_ip3_ctrl,
 377                 .ctrlbit        = (1<<21),
 378         }, {
 379                 .name           = "i2s_v50",
 380                 .id             = 0,
 381                 .parent         = &clk_p,
 382                 .enable         = s5pv210_clk_ip3_ctrl,
 383                 .ctrlbit        = (1<<4),
 384         }, {
 385                 .name           = "i2s_v32",
 386                 .id             = 0,
 387                 .parent         = &clk_p,
 388                 .enable         = s5pv210_clk_ip3_ctrl,
 389                 .ctrlbit        = (1<<4),
 390         }, {
 391                 .name           = "i2s_v32",
 392                 .id             = 1,
 393                 .parent         = &clk_p,
 394                 .enable         = s5pv210_clk_ip3_ctrl,
 395                 .ctrlbit        = (1<<4),
 396         }
 397 };
 398
 399 static struct clk init_clocks[] = {
 400         {
 401                 .name           = "hclk_imem",
 402                 .id             = -1,
 403                 .parent         = &clk_hclk_msys.clk,
 404                 .ctrlbit        = (1 << 5),
 405                 .enable         = s5pv210_clk_ip0_ctrl,
 406                 .ops            = &clk_hclk_imem_ops,
 407         }, {
 408                 .name           = "uart",
 409                 .id             = 0,
 410                 .parent         = &clk_pclk_psys.clk,
 411                 .enable         = s5pv210_clk_ip3_ctrl,
 412                 .ctrlbit        = (1<<7),
 413         }, {
 414                 .name           = "uart",
 415                 .id             = 1,
 416                 .parent         = &clk_pclk_psys.clk,
 417                 .enable         = s5pv210_clk_ip3_ctrl,
 418                 .ctrlbit        = (1<<8),
 419         }, {
 420                 .name           = "uart",
 421                 .id             = 2,
 422                 .parent         = &clk_pclk_psys.clk,
 423                 .enable         = s5pv210_clk_ip3_ctrl,
 424                 .ctrlbit        = (1<<9),
 425         }, {
 426                 .name           = "uart",
 427                 .id             = 3,
 428                 .parent         = &clk_pclk_psys.clk,
 429                 .enable         = s5pv210_clk_ip3_ctrl,
 430                 .ctrlbit        = (1<<10),
 431         },
 432 };
 433
 434 static struct clk *clkset_uart_list[] = {
 435         [6] = &clk_mout_mpll.clk,
 436         [7] = &clk_mout_epll.clk,
 437 };
 438
 439 static struct clksrc_sources clkset_uart = {
 440         .sources        = clkset_uart_list,
 441         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 442 };
 443
 444 static struct clk *clkset_group1_list[] = {
 445         [0] = &clk_sclk_a2m.clk,
 446         [1] = &clk_mout_mpll.clk,
 447         [2] = &clk_mout_epll.clk,
 448         [3] = &clk_sclk_vpll.clk,
 449 };
 450
 451 static struct clksrc_sources clkset_group1 = {
 452         .sources        = clkset_group1_list,
 453         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 454 };
 455
 456 static struct clk *clkset_sclk_onenand_list[] = {
 457         [0] = &clk_hclk_psys.clk,
 458         [1] = &clk_hclk_dsys.clk,
 459 };
 460
 461 static struct clksrc_sources clkset_sclk_onenand = {
 462         .sources        = clkset_sclk_onenand_list,
 463         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 464 };
 465
 466 static struct clksrc_clk clksrcs[] = {
 467         {
 468                 .clk    = {
 469                         .name           = "sclk_dmc",
 470                         .id             = -1,
 471                 },
 472                 .sources = &clkset_group1,
 473                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 474                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 475         }, {
 476                 .clk    = {
 477                         .name           = "sclk_onenand",
 478                         .id             = -1,
 479                 },
 480                 .sources = &clkset_sclk_onenand,
 481                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 482                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 483         }, {
 484                 .clk    = {
 485                         .name           = "uclk1",
 486                         .id             = -1,
 487                         .ctrlbit        = (1<<17),
 488                         .enable         = s5pv210_clk_ip3_ctrl,
 489                 },
 490                 .sources = &clkset_uart,
 491                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 492                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 493         }
 494 };
 495
 496 /* Clock initialisation code */
 497 static struct clksrc_clk *sysclks[] = {
 498         &clk_mout_apll,
 499         &clk_mout_epll,
 500         &clk_mout_mpll,
 501         &clk_armclk,
 502         &clk_hclk_msys,
 503         &clk_sclk_a2m,
 504         &clk_hclk_dsys,
 505         &clk_hclk_psys,
 506         &clk_pclk_msys,
 507         &clk_pclk_dsys,
 508         &clk_pclk_psys,
 509         &clk_vpllsrc,
 510         &clk_sclk_vpll,
 511 };
 512
 513 void __init_or_cpufreq s5pv210_setup_clocks(void)
 514 {
 515         struct clk *xtal_clk;
 516         unsigned long xtal;
 517         unsigned long vpllsrc;
 518         unsigned long armclk;
 519         unsigned long hclk_msys;
 520         unsigned long hclk_dsys;
 521         unsigned long hclk_psys;
 522         unsigned long pclk_msys;
 523         unsigned long pclk_dsys;
 524         unsigned long pclk_psys;
 525         unsigned long apll;
 526         unsigned long mpll;
 527         unsigned long epll;
 528         unsigned long vpll;
 529         unsigned int ptr;
 530         u32 clkdiv0, clkdiv1;
 531
 532         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 533
 534         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 535         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 536
 537         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 538                                 __func__, clkdiv0, clkdiv1);
 539
 540         xtal_clk = clk_get(NULL, "xtal");
 541         BUG_ON(IS_ERR(xtal_clk));
 542
 543         xtal = clk_get_rate(xtal_clk);
 544         clk_put(xtal_clk);
 545
 546         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 547
 548         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 549         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 550         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 551         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
 552         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
 553
 554         clk_fout_apll.rate = apll;
 555         clk_fout_mpll.rate = mpll;
 556         clk_fout_epll.rate = epll;
 557         clk_fout_vpll.rate = vpll;
 558
 559         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
 560                         apll, mpll, epll, vpll);
 561
 562         armclk = clk_get_rate(&clk_armclk.clk);
 563         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
 564         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
 565         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
 566         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
 567         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
 568         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
 569
 570         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
 571                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 572                         armclk, hclk_msys, hclk_dsys, hclk_psys,
 573                         pclk_msys, pclk_dsys, pclk_psys);
 574
 575         clk_f.rate = armclk;
 576         clk_h.rate = hclk_psys;
 577         clk_p.rate = pclk_psys;
 578
 579         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 580                 s3c_set_clksrc(&clksrcs[ptr], true);
 581 }
 582
 583 static struct clk *clks[] __initdata = {
 584         &clk_sclk_hdmi27m,
 585         &clk_sclk_hdmiphy,
 586         &clk_sclk_usbphy0,
 587         &clk_sclk_usbphy1,
 588 };
 589
 590 void __init s5pv210_register_clocks(void)
 591 {
 592         struct clk *clkp;
 593         int ret;
 594         int ptr;
 595
 596         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 597         if (ret > 0)
 598                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 599
 600         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 601                 s3c_register_clksrc(sysclks[ptr], 1);
 602
 603         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 604         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 605
 606         clkp = init_clocks_disable;
 607         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 608                 ret = s3c24xx_register_clock(clkp);
 609                 if (ret < 0) {
 610                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 611                                clkp->name, ret);
 612                 }
 613                 (clkp->enable)(clkp, 0);
 614         }
 615
 616         s3c_pwmclk_init();
 617 }