SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74                 .id             = -1,
  75         },
  76         .sources        = &clkset_armclk,
  77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  79 };
  80
  81 static struct clksrc_clk clk_hclk_msys = {
  82         .clk    = {
  83                 .name           = "hclk_msys",
  84                 .id             = -1,
  85                 .parent         = &clk_armclk.clk,
  86         },
  87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  88 };
  89
  90 static struct clksrc_clk clk_pclk_msys = {
  91         .clk    = {
  92                 .name           = "pclk_msys",
  93                 .id             = -1,
  94                 .parent         = &clk_hclk_msys.clk,
  95         },
  96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  97 };
  98
  99 static struct clksrc_clk clk_sclk_a2m = {
 100         .clk    = {
 101                 .name           = "sclk_a2m",
 102                 .id             = -1,
 103                 .parent         = &clk_mout_apll.clk,
 104         },
 105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 106 };
 107
 108 static struct clk *clkset_hclk_sys_list[] = {
 109         [0] = &clk_mout_mpll.clk,
 110         [1] = &clk_sclk_a2m.clk,
 111 };
 112
 113 static struct clksrc_sources clkset_hclk_sys = {
 114         .sources        = clkset_hclk_sys_list,
 115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 116 };
 117
 118 static struct clksrc_clk clk_hclk_dsys = {
 119         .clk    = {
 120                 .name   = "hclk_dsys",
 121                 .id     = -1,
 122         },
 123         .sources        = &clkset_hclk_sys,
 124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 126 };
 127
 128 static struct clksrc_clk clk_pclk_dsys = {
 129         .clk    = {
 130                 .name   = "pclk_dsys",
 131                 .id     = -1,
 132                 .parent = &clk_hclk_dsys.clk,
 133         },
 134         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 135 };
 136
 137 static struct clksrc_clk clk_hclk_psys = {
 138         .clk    = {
 139                 .name   = "hclk_psys",
 140                 .id     = -1,
 141         },
 142         .sources        = &clkset_hclk_sys,
 143         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 145 };
 146
 147 static struct clksrc_clk clk_pclk_psys = {
 148         .clk    = {
 149                 .name   = "pclk_psys",
 150                 .id     = -1,
 151                 .parent = &clk_hclk_psys.clk,
 152         },
 153         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 154 };
 155
 156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 159 }
 160
 161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 164 }
 165
 166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 169 }
 170
 171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 174 }
 175
 176 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 179 }
 180
 181 static struct clk clk_sclk_hdmi27m = {
 182         .name           = "sclk_hdmi27m",
 183         .id             = -1,
 184         .rate           = 27000000,
 185 };
 186
 187 static struct clk clk_sclk_hdmiphy = {
 188         .name           = "sclk_hdmiphy",
 189         .id             = -1,
 190 };
 191
 192 static struct clk clk_sclk_usbphy0 = {
 193         .name           = "sclk_usbphy0",
 194         .id             = -1,
 195 };
 196
 197 static struct clk clk_sclk_usbphy1 = {
 198         .name           = "sclk_usbphy1",
 199         .id             = -1,
 200 };
 201
 202 static struct clk clk_pcmcdclk0 = {
 203         .name           = "pcmcdclk",
 204         .id             = -1,
 205 };
 206
 207 static struct clk clk_pcmcdclk1 = {
 208         .name           = "pcmcdclk",
 209         .id             = -1,
 210 };
 211
 212 static struct clk clk_pcmcdclk2 = {
 213         .name           = "pcmcdclk",
 214         .id             = -1,
 215 };
 216
 217 static struct clk *clkset_vpllsrc_list[] = {
 218         [0] = &clk_fin_vpll,
 219         [1] = &clk_sclk_hdmi27m,
 220 };
 221
 222 static struct clksrc_sources clkset_vpllsrc = {
 223         .sources        = clkset_vpllsrc_list,
 224         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 225 };
 226
 227 static struct clksrc_clk clk_vpllsrc = {
 228         .clk    = {
 229                 .name           = "vpll_src",
 230                 .id             = -1,
 231                 .enable         = s5pv210_clk_mask0_ctrl,
 232                 .ctrlbit        = (1 << 7),
 233         },
 234         .sources        = &clkset_vpllsrc,
 235         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 236 };
 237
 238 static struct clk *clkset_sclk_vpll_list[] = {
 239         [0] = &clk_vpllsrc.clk,
 240         [1] = &clk_fout_vpll,
 241 };
 242
 243 static struct clksrc_sources clkset_sclk_vpll = {
 244         .sources        = clkset_sclk_vpll_list,
 245         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 246 };
 247
 248 static struct clksrc_clk clk_sclk_vpll = {
 249         .clk    = {
 250                 .name           = "sclk_vpll",
 251                 .id             = -1,
 252         },
 253         .sources        = &clkset_sclk_vpll,
 254         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 255 };
 256
 257 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 258 {
 259         return clk_get_rate(clk->parent) / 2;
 260 }
 261
 262 static struct clk_ops clk_hclk_imem_ops = {
 263         .get_rate       = s5pv210_clk_imem_get_rate,
 264 };
 265
 266 static struct clk init_clocks_disable[] = {
 267         {
 268                 .name           = "rot",
 269                 .id             = -1,
 270                 .parent         = &clk_hclk_dsys.clk,
 271                 .enable         = s5pv210_clk_ip0_ctrl,
 272                 .ctrlbit        = (1<<29),
 273         }, {
 274                 .name           = "otg",
 275                 .id             = -1,
 276                 .parent         = &clk_hclk_psys.clk,
 277                 .enable         = s5pv210_clk_ip1_ctrl,
 278                 .ctrlbit        = (1<<16),
 279         }, {
 280                 .name           = "usb-host",
 281                 .id             = -1,
 282                 .parent         = &clk_hclk_psys.clk,
 283                 .enable         = s5pv210_clk_ip1_ctrl,
 284                 .ctrlbit        = (1<<17),
 285         }, {
 286                 .name           = "lcd",
 287                 .id             = -1,
 288                 .parent         = &clk_hclk_dsys.clk,
 289                 .enable         = s5pv210_clk_ip1_ctrl,
 290                 .ctrlbit        = (1<<0),
 291         }, {
 292                 .name           = "cfcon",
 293                 .id             = 0,
 294                 .parent         = &clk_hclk_psys.clk,
 295                 .enable         = s5pv210_clk_ip1_ctrl,
 296                 .ctrlbit        = (1<<25),
 297         }, {
 298                 .name           = "hsmmc",
 299                 .id             = 0,
 300                 .parent         = &clk_hclk_psys.clk,
 301                 .enable         = s5pv210_clk_ip2_ctrl,
 302                 .ctrlbit        = (1<<16),
 303         }, {
 304                 .name           = "hsmmc",
 305                 .id             = 1,
 306                 .parent         = &clk_hclk_psys.clk,
 307                 .enable         = s5pv210_clk_ip2_ctrl,
 308                 .ctrlbit        = (1<<17),
 309         }, {
 310                 .name           = "hsmmc",
 311                 .id             = 2,
 312                 .parent         = &clk_hclk_psys.clk,
 313                 .enable         = s5pv210_clk_ip2_ctrl,
 314                 .ctrlbit        = (1<<18),
 315         }, {
 316                 .name           = "hsmmc",
 317                 .id             = 3,
 318                 .parent         = &clk_hclk_psys.clk,
 319                 .enable         = s5pv210_clk_ip2_ctrl,
 320                 .ctrlbit        = (1<<19),
 321         }, {
 322                 .name           = "systimer",
 323                 .id             = -1,
 324                 .parent         = &clk_pclk_psys.clk,
 325                 .enable         = s5pv210_clk_ip3_ctrl,
 326                 .ctrlbit        = (1<<16),
 327         }, {
 328                 .name           = "watchdog",
 329                 .id             = -1,
 330                 .parent         = &clk_pclk_psys.clk,
 331                 .enable         = s5pv210_clk_ip3_ctrl,
 332                 .ctrlbit        = (1<<22),
 333         }, {
 334                 .name           = "rtc",
 335                 .id             = -1,
 336                 .parent         = &clk_pclk_psys.clk,
 337                 .enable         = s5pv210_clk_ip3_ctrl,
 338                 .ctrlbit        = (1<<15),
 339         }, {
 340                 .name           = "i2c",
 341                 .id             = 0,
 342                 .parent         = &clk_pclk_psys.clk,
 343                 .enable         = s5pv210_clk_ip3_ctrl,
 344                 .ctrlbit        = (1<<7),
 345         }, {
 346                 .name           = "i2c",
 347                 .id             = 1,
 348                 .parent         = &clk_pclk_psys.clk,
 349                 .enable         = s5pv210_clk_ip3_ctrl,
 350                 .ctrlbit        = (1<<8),
 351         }, {
 352                 .name           = "i2c",
 353                 .id             = 2,
 354                 .parent         = &clk_pclk_psys.clk,
 355                 .enable         = s5pv210_clk_ip3_ctrl,
 356                 .ctrlbit        = (1<<9),
 357         }, {
 358                 .name           = "spi",
 359                 .id             = 0,
 360                 .parent         = &clk_pclk_psys.clk,
 361                 .enable         = s5pv210_clk_ip3_ctrl,
 362                 .ctrlbit        = (1<<12),
 363         }, {
 364                 .name           = "spi",
 365                 .id             = 1,
 366                 .parent         = &clk_pclk_psys.clk,
 367                 .enable         = s5pv210_clk_ip3_ctrl,
 368                 .ctrlbit        = (1<<13),
 369         }, {
 370                 .name           = "spi",
 371                 .id             = 2,
 372                 .parent         = &clk_pclk_psys.clk,
 373                 .enable         = s5pv210_clk_ip3_ctrl,
 374                 .ctrlbit        = (1<<14),
 375         }, {
 376                 .name           = "timers",
 377                 .id             = -1,
 378                 .parent         = &clk_pclk_psys.clk,
 379                 .enable         = s5pv210_clk_ip3_ctrl,
 380                 .ctrlbit        = (1<<23),
 381         }, {
 382                 .name           = "adc",
 383                 .id             = -1,
 384                 .parent         = &clk_pclk_psys.clk,
 385                 .enable         = s5pv210_clk_ip3_ctrl,
 386                 .ctrlbit        = (1<<24),
 387         }, {
 388                 .name           = "keypad",
 389                 .id             = -1,
 390                 .parent         = &clk_pclk_psys.clk,
 391                 .enable         = s5pv210_clk_ip3_ctrl,
 392                 .ctrlbit        = (1<<21),
 393         }, {
 394                 .name           = "i2s_v50",
 395                 .id             = 0,
 396                 .parent         = &clk_p,
 397                 .enable         = s5pv210_clk_ip3_ctrl,
 398                 .ctrlbit        = (1<<4),
 399         }, {
 400                 .name           = "i2s_v32",
 401                 .id             = 0,
 402                 .parent         = &clk_p,
 403                 .enable         = s5pv210_clk_ip3_ctrl,
 404                 .ctrlbit        = (1<<4),
 405         }, {
 406                 .name           = "i2s_v32",
 407                 .id             = 1,
 408                 .parent         = &clk_p,
 409                 .enable         = s5pv210_clk_ip3_ctrl,
 410                 .ctrlbit        = (1<<4),
 411         }
 412 };
 413
 414 static struct clk init_clocks[] = {
 415         {
 416                 .name           = "hclk_imem",
 417                 .id             = -1,
 418                 .parent         = &clk_hclk_msys.clk,
 419                 .ctrlbit        = (1 << 5),
 420                 .enable         = s5pv210_clk_ip0_ctrl,
 421                 .ops            = &clk_hclk_imem_ops,
 422         }, {
 423                 .name           = "uart",
 424                 .id             = 0,
 425                 .parent         = &clk_pclk_psys.clk,
 426                 .enable         = s5pv210_clk_ip3_ctrl,
 427                 .ctrlbit        = (1<<7),
 428         }, {
 429                 .name           = "uart",
 430                 .id             = 1,
 431                 .parent         = &clk_pclk_psys.clk,
 432                 .enable         = s5pv210_clk_ip3_ctrl,
 433                 .ctrlbit        = (1<<8),
 434         }, {
 435                 .name           = "uart",
 436                 .id             = 2,
 437                 .parent         = &clk_pclk_psys.clk,
 438                 .enable         = s5pv210_clk_ip3_ctrl,
 439                 .ctrlbit        = (1<<9),
 440         }, {
 441                 .name           = "uart",
 442                 .id             = 3,
 443                 .parent         = &clk_pclk_psys.clk,
 444                 .enable         = s5pv210_clk_ip3_ctrl,
 445                 .ctrlbit        = (1<<10),
 446         },
 447 };
 448
 449 static struct clk *clkset_uart_list[] = {
 450         [6] = &clk_mout_mpll.clk,
 451         [7] = &clk_mout_epll.clk,
 452 };
 453
 454 static struct clksrc_sources clkset_uart = {
 455         .sources        = clkset_uart_list,
 456         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 457 };
 458
 459 static struct clk *clkset_group1_list[] = {
 460         [0] = &clk_sclk_a2m.clk,
 461         [1] = &clk_mout_mpll.clk,
 462         [2] = &clk_mout_epll.clk,
 463         [3] = &clk_sclk_vpll.clk,
 464 };
 465
 466 static struct clksrc_sources clkset_group1 = {
 467         .sources        = clkset_group1_list,
 468         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 469 };
 470
 471 static struct clk *clkset_sclk_onenand_list[] = {
 472         [0] = &clk_hclk_psys.clk,
 473         [1] = &clk_hclk_dsys.clk,
 474 };
 475
 476 static struct clksrc_sources clkset_sclk_onenand = {
 477         .sources        = clkset_sclk_onenand_list,
 478         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 479 };
 480
 481 static struct clk *clkset_sclk_dac_list[] = {
 482         [0] = &clk_sclk_vpll.clk,
 483         [1] = &clk_sclk_hdmiphy,
 484 };
 485
 486 static struct clksrc_sources clkset_sclk_dac = {
 487         .sources        = clkset_sclk_dac_list,
 488         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 489 };
 490
 491 static struct clksrc_clk clk_sclk_dac = {
 492         .clk            = {
 493                 .name           = "sclk_dac",
 494                 .id             = -1,
 495                 .ctrlbit        = (1 << 10),
 496                 .enable         = s5pv210_clk_ip1_ctrl,
 497         },
 498         .sources        = &clkset_sclk_dac,
 499         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 500 };
 501
 502 static struct clksrc_clk clk_sclk_pixel = {
 503         .clk            = {
 504                 .name           = "sclk_pixel",
 505                 .id             = -1,
 506                 .parent         = &clk_sclk_vpll.clk,
 507         },
 508         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 509 };
 510
 511 static struct clk *clkset_sclk_hdmi_list[] = {
 512         [0] = &clk_sclk_pixel.clk,
 513         [1] = &clk_sclk_hdmiphy,
 514 };
 515
 516 static struct clksrc_sources clkset_sclk_hdmi = {
 517         .sources        = clkset_sclk_hdmi_list,
 518         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 519 };
 520
 521 static struct clksrc_clk clk_sclk_hdmi = {
 522         .clk            = {
 523                 .name           = "sclk_hdmi",
 524                 .id             = -1,
 525                 .enable         = s5pv210_clk_ip1_ctrl,
 526                 .ctrlbit        = (1 << 11),
 527         },
 528         .sources        = &clkset_sclk_hdmi,
 529         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 530 };
 531
 532 static struct clk *clkset_sclk_mixer_list[] = {
 533         [0] = &clk_sclk_dac.clk,
 534         [1] = &clk_sclk_hdmi.clk,
 535 };
 536
 537 static struct clksrc_sources clkset_sclk_mixer = {
 538         .sources        = clkset_sclk_mixer_list,
 539         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 540 };
 541
 542 static struct clk *clkset_sclk_audio0_list[] = {
 543         [0] = &clk_ext_xtal_mux,
 544         [1] = &clk_pcmcdclk0,
 545         [2] = &clk_sclk_hdmi27m,
 546         [3] = &clk_sclk_usbphy0,
 547         [4] = &clk_sclk_usbphy1,
 548         [5] = &clk_sclk_hdmiphy,
 549         [6] = &clk_mout_mpll.clk,
 550         [7] = &clk_mout_epll.clk,
 551         [8] = &clk_sclk_vpll.clk,
 552 };
 553
 554 static struct clksrc_sources clkset_sclk_audio0 = {
 555         .sources        = clkset_sclk_audio0_list,
 556         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 557 };
 558
 559 static struct clksrc_clk clk_sclk_audio0 = {
 560         .clk            = {
 561                 .name           = "sclk_audio",
 562                 .id             = 0,
 563                 .enable         = s5pv210_clk_ip3_ctrl,
 564                 .ctrlbit        = (1 << 4),
 565         },
 566         .sources = &clkset_sclk_audio0,
 567         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 568         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 569 };
 570
 571 static struct clk *clkset_sclk_audio1_list[] = {
 572         [0] = &clk_ext_xtal_mux,
 573         [1] = &clk_pcmcdclk1,
 574         [2] = &clk_sclk_hdmi27m,
 575         [3] = &clk_sclk_usbphy0,
 576         [4] = &clk_sclk_usbphy1,
 577         [5] = &clk_sclk_hdmiphy,
 578         [6] = &clk_mout_mpll.clk,
 579         [7] = &clk_mout_epll.clk,
 580         [8] = &clk_sclk_vpll.clk,
 581 };
 582
 583 static struct clksrc_sources clkset_sclk_audio1 = {
 584         .sources        = clkset_sclk_audio1_list,
 585         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 586 };
 587
 588 static struct clksrc_clk clk_sclk_audio1 = {
 589         .clk            = {
 590                 .name           = "sclk_audio",
 591                 .id             = 1,
 592                 .enable         = s5pv210_clk_ip3_ctrl,
 593                 .ctrlbit        = (1 << 5),
 594         },
 595         .sources = &clkset_sclk_audio1,
 596         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 597         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 598 };
 599
 600 static struct clk *clkset_sclk_audio2_list[] = {
 601         [0] = &clk_ext_xtal_mux,
 602         [1] = &clk_pcmcdclk0,
 603         [2] = &clk_sclk_hdmi27m,
 604         [3] = &clk_sclk_usbphy0,
 605         [4] = &clk_sclk_usbphy1,
 606         [5] = &clk_sclk_hdmiphy,
 607         [6] = &clk_mout_mpll.clk,
 608         [7] = &clk_mout_epll.clk,
 609         [8] = &clk_sclk_vpll.clk,
 610 };
 611
 612 static struct clksrc_sources clkset_sclk_audio2 = {
 613         .sources        = clkset_sclk_audio2_list,
 614         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 615 };
 616
 617 static struct clksrc_clk clk_sclk_audio2 = {
 618         .clk            = {
 619                 .name           = "sclk_audio",
 620                 .id             = 2,
 621                 .enable         = s5pv210_clk_ip3_ctrl,
 622                 .ctrlbit        = (1 << 6),
 623         },
 624         .sources = &clkset_sclk_audio2,
 625         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 626         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 627 };
 628
 629 static struct clk *clkset_sclk_spdif_list[] = {
 630         [0] = &clk_sclk_audio0.clk,
 631         [1] = &clk_sclk_audio1.clk,
 632         [2] = &clk_sclk_audio2.clk,
 633 };
 634
 635 static struct clksrc_sources clkset_sclk_spdif = {
 636         .sources        = clkset_sclk_spdif_list,
 637         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 638 };
 639
 640 static struct clksrc_clk clksrcs[] = {
 641         {
 642                 .clk    = {
 643                         .name           = "sclk_dmc",
 644                         .id             = -1,
 645                 },
 646                 .sources = &clkset_group1,
 647                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 648                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 649         }, {
 650                 .clk    = {
 651                         .name           = "sclk_onenand",
 652                         .id             = -1,
 653                 },
 654                 .sources = &clkset_sclk_onenand,
 655                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 656                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 657         }, {
 658                 .clk    = {
 659                         .name           = "uclk1",
 660                         .id             = -1,
 661                         .ctrlbit        = (1<<17),
 662                         .enable         = s5pv210_clk_ip3_ctrl,
 663                 },
 664                 .sources = &clkset_uart,
 665                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 666                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 667         }, {
 668                 .clk    = {
 669                         .name           = "sclk_mixer",
 670                         .id             = -1,
 671                         .enable         = s5pv210_clk_ip1_ctrl,
 672                         .ctrlbit        = (1 << 9),
 673                 },
 674                 .sources = &clkset_sclk_mixer,
 675                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 676         }, {
 677                 .clk            = {
 678                         .name           = "sclk_spdif",
 679                         .id             = -1,
 680                         .enable         = s5pv210_clk_mask0_ctrl,
 681                         .ctrlbit        = (1 << 27),
 682                 },
 683                 .sources = &clkset_sclk_spdif,
 684                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 685         },
 686 };
 687
 688 /* Clock initialisation code */
 689 static struct clksrc_clk *sysclks[] = {
 690         &clk_mout_apll,
 691         &clk_mout_epll,
 692         &clk_mout_mpll,
 693         &clk_armclk,
 694         &clk_hclk_msys,
 695         &clk_sclk_a2m,
 696         &clk_hclk_dsys,
 697         &clk_hclk_psys,
 698         &clk_pclk_msys,
 699         &clk_pclk_dsys,
 700         &clk_pclk_psys,
 701         &clk_vpllsrc,
 702         &clk_sclk_vpll,
 703         &clk_sclk_dac,
 704         &clk_sclk_pixel,
 705         &clk_sclk_hdmi,
 706 };
 707
 708 void __init_or_cpufreq s5pv210_setup_clocks(void)
 709 {
 710         struct clk *xtal_clk;
 711         unsigned long xtal;
 712         unsigned long vpllsrc;
 713         unsigned long armclk;
 714         unsigned long hclk_msys;
 715         unsigned long hclk_dsys;
 716         unsigned long hclk_psys;
 717         unsigned long pclk_msys;
 718         unsigned long pclk_dsys;
 719         unsigned long pclk_psys;
 720         unsigned long apll;
 721         unsigned long mpll;
 722         unsigned long epll;
 723         unsigned long vpll;
 724         unsigned int ptr;
 725         u32 clkdiv0, clkdiv1;
 726
 727         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 728
 729         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 730         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 731
 732         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 733                                 __func__, clkdiv0, clkdiv1);
 734
 735         xtal_clk = clk_get(NULL, "xtal");
 736         BUG_ON(IS_ERR(xtal_clk));
 737
 738         xtal = clk_get_rate(xtal_clk);
 739         clk_put(xtal_clk);
 740
 741         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 742
 743         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 744         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 745         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 746         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
 747         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
 748
 749         clk_fout_apll.rate = apll;
 750         clk_fout_mpll.rate = mpll;
 751         clk_fout_epll.rate = epll;
 752         clk_fout_vpll.rate = vpll;
 753
 754         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
 755                         apll, mpll, epll, vpll);
 756
 757         armclk = clk_get_rate(&clk_armclk.clk);
 758         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
 759         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
 760         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
 761         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
 762         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
 763         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
 764
 765         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
 766                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
 767                         armclk, hclk_msys, hclk_dsys, hclk_psys,
 768                         pclk_msys, pclk_dsys, pclk_psys);
 769
 770         clk_f.rate = armclk;
 771         clk_h.rate = hclk_psys;
 772         clk_p.rate = pclk_psys;
 773
 774         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 775                 s3c_set_clksrc(&clksrcs[ptr], true);
 776 }
 777
 778 static struct clk *clks[] __initdata = {
 779         &clk_sclk_hdmi27m,
 780         &clk_sclk_hdmiphy,
 781         &clk_sclk_usbphy0,
 782         &clk_sclk_usbphy1,
 783         &clk_pcmcdclk0,
 784         &clk_pcmcdclk1,
 785         &clk_pcmcdclk2,
 786 };
 787
 788 void __init s5pv210_register_clocks(void)
 789 {
 790         struct clk *clkp;
 791         int ret;
 792         int ptr;
 793
 794         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 795         if (ret > 0)
 796                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 797
 798         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 799                 s3c_register_clksrc(sysclks[ptr], 1);
 800
 801         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 802         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 803
 804         clkp = init_clocks_disable;
 805         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 806                 ret = s3c24xx_register_clock(clkp);
 807                 if (ret < 0) {
 808                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 809                                clkp->name, ret);
 810                 }
 811                 (clkp->enable)(clkp, 0);
 812         }
 813
 814         s3c_pwmclk_init();
 815 }