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   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/io.h>
  29 #include <linux/smsc911x.h>
  30 #include <linux/ata_platform.h>
  31 #include <linux/amba/mmci.h>
  32
  33 #include <asm/clkdev.h>
  34 #include <asm/system.h>
  35 #include <mach/hardware.h>
  36 #include <asm/irq.h>
  37 #include <asm/leds.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41
  42 #include <asm/mach/arch.h>
  43 #include <asm/mach/flash.h>
  44 #include <asm/mach/irq.h>
  45 #include <asm/mach/map.h>
  46
  47 #include <asm/hardware/gic.h>
  48
  49 #include <mach/clkdev.h>
  50 #include <mach/platform.h>
  51 #include <mach/irqs.h>
  52 #include <plat/timer-sp.h>
  53
  54 #include "core.h"
  55
  56 #define REALVIEW_REFCOUNTER     (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
  57
  58 /* used by entry-macro.S and platsmp.c */
  59 void __iomem *gic_cpu_base_addr;
  60
  61 #ifdef CONFIG_ZONE_DMA
  62 /*
  63  * Adjust the zones if there are restrictions for DMA access.
  64  */
  65 void __init realview_adjust_zones(int node, unsigned long *size,
  66                                   unsigned long *hole)
  67 {
  68         unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
  69
  70         if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
  71                 return;
  72
  73         size[ZONE_NORMAL] = size[0] - dma_size;
  74         size[ZONE_DMA] = dma_size;
  75         hole[ZONE_NORMAL] = hole[0];
  76         hole[ZONE_DMA] = 0;
  77 }
  78 #endif
  79
  80 /*
  81  * This is the RealView sched_clock implementation.  This has
  82  * a resolution of 41.7ns, and a maximum value of about 179s.
  83  */
  84 unsigned long long sched_clock(void)
  85 {
  86         unsigned long long v;
  87
  88         v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
  89         do_div(v, 3);
  90
  91         return v;
  92 }
  93
  94
  95 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  96
  97 static int realview_flash_init(void)
  98 {
  99         u32 val;
 100
 101         val = __raw_readl(REALVIEW_FLASHCTRL);
 102         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 103         __raw_writel(val, REALVIEW_FLASHCTRL);
 104
 105         return 0;
 106 }
 107
 108 static void realview_flash_exit(void)
 109 {
 110         u32 val;
 111
 112         val = __raw_readl(REALVIEW_FLASHCTRL);
 113         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 114         __raw_writel(val, REALVIEW_FLASHCTRL);
 115 }
 116
 117 static void realview_flash_set_vpp(int on)
 118 {
 119         u32 val;
 120
 121         val = __raw_readl(REALVIEW_FLASHCTRL);
 122         if (on)
 123                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 124         else
 125                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 126         __raw_writel(val, REALVIEW_FLASHCTRL);
 127 }
 128
 129 static struct flash_platform_data realview_flash_data = {
 130         .map_name               = "cfi_probe",
 131         .width                  = 4,
 132         .init                   = realview_flash_init,
 133         .exit                   = realview_flash_exit,
 134         .set_vpp                = realview_flash_set_vpp,
 135 };
 136
 137 struct platform_device realview_flash_device = {
 138         .name                   = "armflash",
 139         .id                     = 0,
 140         .dev                    = {
 141                 .platform_data  = &realview_flash_data,
 142         },
 143 };
 144
 145 int realview_flash_register(struct resource *res, u32 num)
 146 {
 147         realview_flash_device.resource = res;
 148         realview_flash_device.num_resources = num;
 149         return platform_device_register(&realview_flash_device);
 150 }
 151
 152 static struct smsc911x_platform_config smsc911x_config = {
 153         .flags          = SMSC911X_USE_32BIT,
 154         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 155         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 156         .phy_interface  = PHY_INTERFACE_MODE_MII,
 157 };
 158
 159 static struct platform_device realview_eth_device = {
 160         .name           = "smsc911x",
 161         .id             = 0,
 162         .num_resources  = 2,
 163 };
 164
 165 int realview_eth_register(const char *name, struct resource *res)
 166 {
 167         if (name)
 168                 realview_eth_device.name = name;
 169         realview_eth_device.resource = res;
 170         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 171                 realview_eth_device.dev.platform_data = &smsc911x_config;
 172
 173         return platform_device_register(&realview_eth_device);
 174 }
 175
 176 struct platform_device realview_usb_device = {
 177         .name                   = "isp1760",
 178         .num_resources          = 2,
 179 };
 180
 181 int realview_usb_register(struct resource *res)
 182 {
 183         realview_usb_device.resource = res;
 184         return platform_device_register(&realview_usb_device);
 185 }
 186
 187 static struct pata_platform_info pata_platform_data = {
 188         .ioport_shift           = 1,
 189 };
 190
 191 static struct resource pata_resources[] = {
 192         [0] = {
 193                 .start          = REALVIEW_CF_BASE,
 194                 .end            = REALVIEW_CF_BASE + 0xff,
 195                 .flags          = IORESOURCE_MEM,
 196         },
 197         [1] = {
 198                 .start          = REALVIEW_CF_BASE + 0x100,
 199                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
 200                 .flags          = IORESOURCE_MEM,
 201         },
 202 };
 203
 204 struct platform_device realview_cf_device = {
 205         .name                   = "pata_platform",
 206         .id                     = -1,
 207         .num_resources          = ARRAY_SIZE(pata_resources),
 208         .resource               = pata_resources,
 209         .dev                    = {
 210                 .platform_data  = &pata_platform_data,
 211         },
 212 };
 213
 214 static struct resource realview_i2c_resource = {
 215         .start          = REALVIEW_I2C_BASE,
 216         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 217         .flags          = IORESOURCE_MEM,
 218 };
 219
 220 struct platform_device realview_i2c_device = {
 221         .name           = "versatile-i2c",
 222         .id             = 0,
 223         .num_resources  = 1,
 224         .resource       = &realview_i2c_resource,
 225 };
 226
 227 static struct i2c_board_info realview_i2c_board_info[] = {
 228         {
 229                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 230         },
 231 };
 232
 233 static int __init realview_i2c_init(void)
 234 {
 235         return i2c_register_board_info(0, realview_i2c_board_info,
 236                                        ARRAY_SIZE(realview_i2c_board_info));
 237 }
 238 arch_initcall(realview_i2c_init);
 239
 240 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 241
 242 /*
 243  * This is only used if GPIOLIB support is disabled
 244  */
 245 static unsigned int realview_mmc_status(struct device *dev)
 246 {
 247         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 248         u32 mask;
 249
 250         if (adev->res.start == REALVIEW_MMCI0_BASE)
 251                 mask = 1;
 252         else
 253                 mask = 2;
 254
 255         return readl(REALVIEW_SYSMCI) & mask;
 256 }
 257
 258 struct mmci_platform_data realview_mmc0_plat_data = {
 259         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 260         .status         = realview_mmc_status,
 261         .gpio_wp        = 17,
 262         .gpio_cd        = 16,
 263 };
 264
 265 struct mmci_platform_data realview_mmc1_plat_data = {
 266         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 267         .status         = realview_mmc_status,
 268         .gpio_wp        = 19,
 269         .gpio_cd        = 18,
 270 };
 271
 272 /*
 273  * Clock handling
 274  */
 275 static const struct icst_params realview_oscvco_params = {
 276         .ref            = 24000000,
 277         .vco_max        = ICST307_VCO_MAX,
 278         .vco_min        = ICST307_VCO_MIN,
 279         .vd_min         = 4 + 8,
 280         .vd_max         = 511 + 8,
 281         .rd_min         = 1 + 2,
 282         .rd_max         = 127 + 2,
 283         .s2div          = icst307_s2div,
 284         .idx2s          = icst307_idx2s,
 285 };
 286
 287 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
 288 {
 289         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 290         void __iomem *sys_osc;
 291         u32 val;
 292
 293         if (machine_is_realview_pb1176())
 294                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 295         else
 296                 sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 297
 298         val = readl(sys_osc) & ~0x7ffff;
 299         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 300
 301         writel(0xa05f, sys_lock);
 302         writel(val, sys_osc);
 303         writel(0, sys_lock);
 304 }
 305
 306 static struct clk oscvco_clk = {
 307         .params = &realview_oscvco_params,
 308         .setvco = realview_oscvco_set,
 309 };
 310
 311 /*
 312  * These are fixed clocks.
 313  */
 314 static struct clk ref24_clk = {
 315         .rate   = 24000000,
 316 };
 317
 318 static struct clk_lookup lookups[] = {
 319         {       /* UART0 */
 320                 .dev_id         = "dev:uart0",
 321                 .clk            = &ref24_clk,
 322         }, {    /* UART1 */
 323                 .dev_id         = "dev:uart1",
 324                 .clk            = &ref24_clk,
 325         }, {    /* UART2 */
 326                 .dev_id         = "dev:uart2",
 327                 .clk            = &ref24_clk,
 328         }, {    /* UART3 */
 329                 .dev_id         = "fpga:uart3",
 330                 .clk            = &ref24_clk,
 331         }, {    /* KMI0 */
 332                 .dev_id         = "fpga:kmi0",
 333                 .clk            = &ref24_clk,
 334         }, {    /* KMI1 */
 335                 .dev_id         = "fpga:kmi1",
 336                 .clk            = &ref24_clk,
 337         }, {    /* MMC0 */
 338                 .dev_id         = "fpga:mmc0",
 339                 .clk            = &ref24_clk,
 340         }, {    /* EB:CLCD */
 341                 .dev_id         = "dev:clcd",
 342                 .clk            = &oscvco_clk,
 343         }, {    /* PB:CLCD */
 344                 .dev_id         = "issp:clcd",
 345                 .clk            = &oscvco_clk,
 346         }
 347 };
 348
 349 static int __init clk_init(void)
 350 {
 351         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 352         return 0;
 353 }
 354 arch_initcall(clk_init);
 355
 356 /*
 357  * CLCD support.
 358  */
 359 #define SYS_CLCD_NLCDIOON       (1 << 2)
 360 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 361 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 362 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 363 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 364 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 365 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 366 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 367 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 368
 369 static struct clcd_panel vga = {
 370         .mode           = {
 371                 .name           = "VGA",
 372                 .refresh        = 60,
 373                 .xres           = 640,
 374                 .yres           = 480,
 375                 .pixclock       = 39721,
 376                 .left_margin    = 40,
 377                 .right_margin   = 24,
 378                 .upper_margin   = 32,
 379                 .lower_margin   = 11,
 380                 .hsync_len      = 96,
 381                 .vsync_len      = 2,
 382                 .sync           = 0,
 383                 .vmode          = FB_VMODE_NONINTERLACED,
 384         },
 385         .width          = -1,
 386         .height         = -1,
 387         .tim2           = TIM2_BCD | TIM2_IPC,
 388         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 389         .bpp            = 16,
 390 };
 391
 392 static struct clcd_panel xvga = {
 393         .mode           = {
 394                 .name           = "XVGA",
 395                 .refresh        = 60,
 396                 .xres           = 1024,
 397                 .yres           = 768,
 398                 .pixclock       = 15748,
 399                 .left_margin    = 152,
 400                 .right_margin   = 48,
 401                 .upper_margin   = 23,
 402                 .lower_margin   = 3,
 403                 .hsync_len      = 104,
 404                 .vsync_len      = 4,
 405                 .sync           = 0,
 406                 .vmode          = FB_VMODE_NONINTERLACED,
 407         },
 408         .width          = -1,
 409         .height         = -1,
 410         .tim2           = TIM2_BCD | TIM2_IPC,
 411         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 412         .bpp            = 16,
 413 };
 414
 415 static struct clcd_panel sanyo_3_8_in = {
 416         .mode           = {
 417                 .name           = "Sanyo QVGA",
 418                 .refresh        = 116,
 419                 .xres           = 320,
 420                 .yres           = 240,
 421                 .pixclock       = 100000,
 422                 .left_margin    = 6,
 423                 .right_margin   = 6,
 424                 .upper_margin   = 5,
 425                 .lower_margin   = 5,
 426                 .hsync_len      = 6,
 427                 .vsync_len      = 6,
 428                 .sync           = 0,
 429                 .vmode          = FB_VMODE_NONINTERLACED,
 430         },
 431         .width          = -1,
 432         .height         = -1,
 433         .tim2           = TIM2_BCD,
 434         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 435         .bpp            = 16,
 436 };
 437
 438 static struct clcd_panel sanyo_2_5_in = {
 439         .mode           = {
 440                 .name           = "Sanyo QVGA Portrait",
 441                 .refresh        = 116,
 442                 .xres           = 240,
 443                 .yres           = 320,
 444                 .pixclock       = 100000,
 445                 .left_margin    = 20,
 446                 .right_margin   = 10,
 447                 .upper_margin   = 2,
 448                 .lower_margin   = 2,
 449                 .hsync_len      = 10,
 450                 .vsync_len      = 2,
 451                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 452                 .vmode          = FB_VMODE_NONINTERLACED,
 453         },
 454         .width          = -1,
 455         .height         = -1,
 456         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 457         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 458         .bpp            = 16,
 459 };
 460
 461 static struct clcd_panel epson_2_2_in = {
 462         .mode           = {
 463                 .name           = "Epson QCIF",
 464                 .refresh        = 390,
 465                 .xres           = 176,
 466                 .yres           = 220,
 467                 .pixclock       = 62500,
 468                 .left_margin    = 3,
 469                 .right_margin   = 2,
 470                 .upper_margin   = 1,
 471                 .lower_margin   = 0,
 472                 .hsync_len      = 3,
 473                 .vsync_len      = 2,
 474                 .sync           = 0,
 475                 .vmode          = FB_VMODE_NONINTERLACED,
 476         },
 477         .width          = -1,
 478         .height         = -1,
 479         .tim2           = TIM2_BCD | TIM2_IPC,
 480         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 481         .bpp            = 16,
 482 };
 483
 484 /*
 485  * Detect which LCD panel is connected, and return the appropriate
 486  * clcd_panel structure.  Note: we do not have any information on
 487  * the required timings for the 8.4in panel, so we presently assume
 488  * VGA timings.
 489  */
 490 static struct clcd_panel *realview_clcd_panel(void)
 491 {
 492         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 493         struct clcd_panel *vga_panel;
 494         struct clcd_panel *panel;
 495         u32 val;
 496
 497         if (machine_is_realview_eb())
 498                 vga_panel = &vga;
 499         else
 500                 vga_panel = &xvga;
 501
 502         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 503         if (val == SYS_CLCD_ID_SANYO_3_8)
 504                 panel = &sanyo_3_8_in;
 505         else if (val == SYS_CLCD_ID_SANYO_2_5)
 506                 panel = &sanyo_2_5_in;
 507         else if (val == SYS_CLCD_ID_EPSON_2_2)
 508                 panel = &epson_2_2_in;
 509         else if (val == SYS_CLCD_ID_VGA)
 510                 panel = vga_panel;
 511         else {
 512                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 513                         val);
 514                 panel = vga_panel;
 515         }
 516
 517         return panel;
 518 }
 519
 520 /*
 521  * Disable all display connectors on the interface module.
 522  */
 523 static void realview_clcd_disable(struct clcd_fb *fb)
 524 {
 525         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 526         u32 val;
 527
 528         val = readl(sys_clcd);
 529         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 530         writel(val, sys_clcd);
 531 }
 532
 533 /*
 534  * Enable the relevant connector on the interface module.
 535  */
 536 static void realview_clcd_enable(struct clcd_fb *fb)
 537 {
 538         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 539         u32 val;
 540
 541         /*
 542          * Enable the PSUs
 543          */
 544         val = readl(sys_clcd);
 545         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 546         writel(val, sys_clcd);
 547 }
 548
 549 static int realview_clcd_setup(struct clcd_fb *fb)
 550 {
 551         unsigned long framesize;
 552         dma_addr_t dma;
 553
 554         if (machine_is_realview_eb())
 555                 /* VGA, 16bpp */
 556                 framesize = 640 * 480 * 2;
 557         else
 558                 /* XVGA, 16bpp */
 559                 framesize = 1024 * 768 * 2;
 560
 561         fb->panel               = realview_clcd_panel();
 562
 563         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 564                                                     &dma, GFP_KERNEL | GFP_DMA);
 565         if (!fb->fb.screen_base) {
 566                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 567                 return -ENOMEM;
 568         }
 569
 570         fb->fb.fix.smem_start   = dma;
 571         fb->fb.fix.smem_len     = framesize;
 572
 573         return 0;
 574 }
 575
 576 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 577 {
 578         return dma_mmap_writecombine(&fb->dev->dev, vma,
 579                                      fb->fb.screen_base,
 580                                      fb->fb.fix.smem_start,
 581                                      fb->fb.fix.smem_len);
 582 }
 583
 584 static void realview_clcd_remove(struct clcd_fb *fb)
 585 {
 586         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 587                               fb->fb.screen_base, fb->fb.fix.smem_start);
 588 }
 589
 590 struct clcd_board clcd_plat_data = {
 591         .name           = "RealView",
 592         .check          = clcdfb_check,
 593         .decode         = clcdfb_decode,
 594         .disable        = realview_clcd_disable,
 595         .enable         = realview_clcd_enable,
 596         .setup          = realview_clcd_setup,
 597         .mmap           = realview_clcd_mmap,
 598         .remove         = realview_clcd_remove,
 599 };
 600
 601 #ifdef CONFIG_LEDS
 602 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 603
 604 void realview_leds_event(led_event_t ledevt)
 605 {
 606         unsigned long flags;
 607         u32 val;
 608         u32 led = 1 << smp_processor_id();
 609
 610         local_irq_save(flags);
 611         val = readl(VA_LEDS_BASE);
 612
 613         switch (ledevt) {
 614         case led_idle_start:
 615                 val = val & ~led;
 616                 break;
 617
 618         case led_idle_end:
 619                 val = val | led;
 620                 break;
 621
 622         case led_timer:
 623                 val = val ^ REALVIEW_SYS_LED7;
 624                 break;
 625
 626         case led_halted:
 627                 val = 0;
 628                 break;
 629
 630         default:
 631                 break;
 632         }
 633
 634         writel(val, VA_LEDS_BASE);
 635         local_irq_restore(flags);
 636 }
 637 #endif  /* CONFIG_LEDS */
 638
 639 /*
 640  * Where is the timer (VA)?
 641  */
 642 void __iomem *timer0_va_base;
 643 void __iomem *timer1_va_base;
 644 void __iomem *timer2_va_base;
 645 void __iomem *timer3_va_base;
 646
 647 /*
 648  * Set up the clock source and clock events devices
 649  */
 650 void __init realview_timer_init(unsigned int timer_irq)
 651 {
 652         u32 val;
 653
 654         /*
 655          * set clock frequency:
 656          *      REALVIEW_REFCLK is 32KHz
 657          *      REALVIEW_TIMCLK is 1MHz
 658          */
 659         val = readl(__io_address(REALVIEW_SCTL_BASE));
 660         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 661                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 662                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 663                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 664                __io_address(REALVIEW_SCTL_BASE));
 665
 666         /*
 667          * Initialise to a known state (all timers off)
 668          */
 669         writel(0, timer0_va_base + TIMER_CTRL);
 670         writel(0, timer1_va_base + TIMER_CTRL);
 671         writel(0, timer2_va_base + TIMER_CTRL);
 672         writel(0, timer3_va_base + TIMER_CTRL);
 673
 674         sp804_clocksource_init(timer3_va_base);
 675         sp804_clockevents_init(timer0_va_base, timer_irq);
 676 }
 677
 678 /*
 679  * Setup the memory banks.
 680  */
 681 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 682                     struct meminfo *meminfo)
 683 {
 684         /*
 685          * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
 686          * Half of this is mirrored at 0.
 687          */
 688 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
 689         meminfo->bank[0].start = 0x70000000;
 690         meminfo->bank[0].size = SZ_512M;
 691         meminfo->nr_banks = 1;
 692 #else
 693         meminfo->bank[0].start = 0;
 694         meminfo->bank[0].size = SZ_256M;
 695         meminfo->nr_banks = 1;
 696 #endif
 697 }