2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
26 #include <linux/delay.h>
28 #include <plat/common.h>
29 #include <plat/board.h>
30 #include <plat/clock.h>
31 #include <plat/control.h>
35 #include "prm-regbits-34xx.h"
37 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
38 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
41 * NOTE: By default the serial timeout is disabled as it causes lost characters
42 * over the serial ports. This means that the UART clocks will stay on until
43 * disabled via sysfs. This also causes that any deeper omap sleep states are
46 #define DEFAULT_TIMEOUT 0
48 struct omap_uart_state {
51 struct timer_list timer;
63 struct plat_serial8250_port *p;
64 struct list_head node;
65 struct platform_device pdev;
67 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
70 /* Registers to be saved/restored for OFF-mode */
80 static LIST_HEAD(uart_list);
82 static struct plat_serial8250_port serial_platform_data0[] = {
85 .flags = UPF_BOOT_AUTOCONF,
88 .uartclk = OMAP24XX_BASE_BAUD * 16,
94 static struct plat_serial8250_port serial_platform_data1[] = {
97 .flags = UPF_BOOT_AUTOCONF,
100 .uartclk = OMAP24XX_BASE_BAUD * 16,
106 static struct plat_serial8250_port serial_platform_data2[] = {
109 .flags = UPF_BOOT_AUTOCONF,
112 .uartclk = OMAP24XX_BASE_BAUD * 16,
118 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
119 static struct plat_serial8250_port serial_platform_data3[] = {
122 .flags = UPF_BOOT_AUTOCONF,
125 .uartclk = OMAP24XX_BASE_BAUD * 16,
131 static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
133 serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
136 static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
141 void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
143 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
144 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
145 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
146 if (cpu_is_omap3630() || cpu_is_omap44xx())
147 omap2_set_globals_uart4(omap2_globals);
150 static inline unsigned int __serial_read_reg(struct uart_port *up,
153 offset <<= up->regshift;
154 return (unsigned int)__raw_readb(up->membase + offset);
157 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
160 offset <<= up->regshift;
161 return (unsigned int)__raw_readb(up->membase + offset);
164 static inline void __serial_write_reg(struct uart_port *up, int offset,
167 offset <<= up->regshift;
168 __raw_writeb(value, up->membase + offset);
171 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
174 offset <<= p->regshift;
175 __raw_writeb(value, p->membase + offset);
179 * Internal UARTs need to be initialized for the 8250 autoconfig to work
180 * properly. Note that the TX watermark initialization may not be needed
181 * once the 8250.c watermark handling code is merged.
183 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
185 struct plat_serial8250_port *p = uart->p;
187 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
188 serial_write_reg(p, UART_OMAP_SCR, 0x08);
189 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
190 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
193 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
195 static void omap_uart_save_context(struct omap_uart_state *uart)
198 struct plat_serial8250_port *p = uart->p;
200 if (!enable_off_mode)
203 lcr = serial_read_reg(p, UART_LCR);
204 serial_write_reg(p, UART_LCR, 0xBF);
205 uart->dll = serial_read_reg(p, UART_DLL);
206 uart->dlh = serial_read_reg(p, UART_DLM);
207 serial_write_reg(p, UART_LCR, lcr);
208 uart->ier = serial_read_reg(p, UART_IER);
209 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
210 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
211 uart->wer = serial_read_reg(p, UART_OMAP_WER);
213 uart->context_valid = 1;
216 static void omap_uart_restore_context(struct omap_uart_state *uart)
219 struct plat_serial8250_port *p = uart->p;
221 if (!enable_off_mode)
224 if (!uart->context_valid)
227 uart->context_valid = 0;
229 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
230 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
231 efr = serial_read_reg(p, UART_EFR);
232 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
233 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
234 serial_write_reg(p, UART_IER, 0x0);
235 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
236 serial_write_reg(p, UART_DLL, uart->dll);
237 serial_write_reg(p, UART_DLM, uart->dlh);
238 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
239 serial_write_reg(p, UART_IER, uart->ier);
240 serial_write_reg(p, UART_FCR, 0xA1);
241 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
242 serial_write_reg(p, UART_EFR, efr);
243 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
244 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
245 serial_write_reg(p, UART_OMAP_WER, uart->wer);
246 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
247 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
250 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
251 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
252 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
254 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
259 clk_enable(uart->ick);
260 clk_enable(uart->fck);
262 omap_uart_restore_context(uart);
267 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
272 omap_uart_save_context(uart);
274 clk_disable(uart->ick);
275 clk_disable(uart->fck);
278 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
280 /* Set wake-enable bit */
281 if (uart->wk_en && uart->wk_mask) {
282 u32 v = __raw_readl(uart->wk_en);
284 __raw_writel(v, uart->wk_en);
287 /* Ensure IOPAD wake-enables are set */
288 if (cpu_is_omap34xx() && uart->padconf) {
289 u16 v = omap_ctrl_readw(uart->padconf);
290 v |= OMAP3_PADCONF_WAKEUPENABLE0;
291 omap_ctrl_writew(v, uart->padconf);
295 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
297 /* Clear wake-enable bit */
298 if (uart->wk_en && uart->wk_mask) {
299 u32 v = __raw_readl(uart->wk_en);
301 __raw_writel(v, uart->wk_en);
304 /* Ensure IOPAD wake-enables are cleared */
305 if (cpu_is_omap34xx() && uart->padconf) {
306 u16 v = omap_ctrl_readw(uart->padconf);
307 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
308 omap_ctrl_writew(v, uart->padconf);
312 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
315 struct plat_serial8250_port *p = uart->p;
318 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
324 serial_write_reg(p, UART_OMAP_SYSC, sysc);
327 static void omap_uart_block_sleep(struct omap_uart_state *uart)
329 omap_uart_enable_clocks(uart);
331 omap_uart_smart_idle_enable(uart, 0);
334 mod_timer(&uart->timer, jiffies + uart->timeout);
336 del_timer(&uart->timer);
339 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
341 if (device_may_wakeup(&uart->pdev.dev))
342 omap_uart_enable_wakeup(uart);
344 omap_uart_disable_wakeup(uart);
349 omap_uart_smart_idle_enable(uart, 1);
351 del_timer(&uart->timer);
354 static void omap_uart_idle_timer(unsigned long data)
356 struct omap_uart_state *uart = (struct omap_uart_state *)data;
358 omap_uart_allow_sleep(uart);
361 void omap_uart_prepare_idle(int num)
363 struct omap_uart_state *uart;
365 list_for_each_entry(uart, &uart_list, node) {
366 if (num == uart->num && uart->can_sleep) {
367 omap_uart_disable_clocks(uart);
373 void omap_uart_resume_idle(int num)
375 struct omap_uart_state *uart;
377 list_for_each_entry(uart, &uart_list, node) {
378 if (num == uart->num) {
379 omap_uart_enable_clocks(uart);
381 /* Check for IO pad wakeup */
382 if (cpu_is_omap34xx() && uart->padconf) {
383 u16 p = omap_ctrl_readw(uart->padconf);
385 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
386 omap_uart_block_sleep(uart);
389 /* Check for normal UART wakeup */
390 if (__raw_readl(uart->wk_st) & uart->wk_mask)
391 omap_uart_block_sleep(uart);
397 void omap_uart_prepare_suspend(void)
399 struct omap_uart_state *uart;
401 list_for_each_entry(uart, &uart_list, node) {
402 omap_uart_allow_sleep(uart);
406 int omap_uart_can_sleep(void)
408 struct omap_uart_state *uart;
411 list_for_each_entry(uart, &uart_list, node) {
415 if (!uart->can_sleep) {
420 /* This UART can now safely sleep. */
421 omap_uart_allow_sleep(uart);
428 * omap_uart_interrupt()
430 * This handler is used only to detect that *any* UART interrupt has
431 * occurred. It does _nothing_ to handle the interrupt. Rather,
432 * any UART interrupt will trigger the inactivity timer so the
433 * UART will not idle or sleep for its timeout period.
436 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
438 struct omap_uart_state *uart = dev_id;
440 omap_uart_block_sleep(uart);
445 static void omap_uart_idle_init(struct omap_uart_state *uart)
447 struct plat_serial8250_port *p = uart->p;
451 uart->timeout = DEFAULT_TIMEOUT;
452 setup_timer(&uart->timer, omap_uart_idle_timer,
453 (unsigned long) uart);
455 mod_timer(&uart->timer, jiffies + uart->timeout);
456 omap_uart_smart_idle_enable(uart, 0);
458 if (cpu_is_omap34xx()) {
459 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
463 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
464 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
467 wk_mask = OMAP3430_ST_UART1_MASK;
471 wk_mask = OMAP3430_ST_UART2_MASK;
475 wk_mask = OMAP3430_ST_UART3_MASK;
479 uart->wk_mask = wk_mask;
480 uart->padconf = padconf;
481 } else if (cpu_is_omap24xx()) {
484 if (cpu_is_omap2430()) {
485 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
486 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
487 } else if (cpu_is_omap2420()) {
488 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
489 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
493 wk_mask = OMAP24XX_ST_UART1_MASK;
496 wk_mask = OMAP24XX_ST_UART2_MASK;
499 wk_mask = OMAP24XX_ST_UART3_MASK;
502 uart->wk_mask = wk_mask;
510 p->irqflags |= IRQF_SHARED;
511 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
512 "serial idle", (void *)uart);
516 void omap_uart_enable_irqs(int enable)
519 struct omap_uart_state *uart;
521 list_for_each_entry(uart, &uart_list, node) {
523 ret = request_irq(uart->p->irq, omap_uart_interrupt,
524 IRQF_SHARED, "serial idle", (void *)uart);
526 free_irq(uart->p->irq, (void *)uart);
530 static ssize_t sleep_timeout_show(struct device *dev,
531 struct device_attribute *attr,
534 struct platform_device *pdev = container_of(dev,
535 struct platform_device, dev);
536 struct omap_uart_state *uart = container_of(pdev,
537 struct omap_uart_state, pdev);
539 return sprintf(buf, "%u\n", uart->timeout / HZ);
542 static ssize_t sleep_timeout_store(struct device *dev,
543 struct device_attribute *attr,
544 const char *buf, size_t n)
546 struct platform_device *pdev = container_of(dev,
547 struct platform_device, dev);
548 struct omap_uart_state *uart = container_of(pdev,
549 struct omap_uart_state, pdev);
552 if (sscanf(buf, "%u", &value) != 1) {
553 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
557 uart->timeout = value * HZ;
559 mod_timer(&uart->timer, jiffies + uart->timeout);
561 /* A zero value means disable timeout feature */
562 omap_uart_block_sleep(uart);
567 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
568 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
570 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
571 #define DEV_CREATE_FILE(dev, attr)
572 #endif /* CONFIG_PM */
574 static struct omap_uart_state omap_uart[] = {
577 .name = "serial8250",
578 .id = PLAT8250_DEV_PLATFORM,
580 .platform_data = serial_platform_data0,
585 .name = "serial8250",
586 .id = PLAT8250_DEV_PLATFORM1,
588 .platform_data = serial_platform_data1,
593 .name = "serial8250",
594 .id = PLAT8250_DEV_PLATFORM2,
596 .platform_data = serial_platform_data2,
600 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
603 .name = "serial8250",
606 .platform_data = serial_platform_data3,
614 * Override the default 8250 read handler: mem_serial_in()
615 * Empty RX fifo read causes an abort on omap3630 and omap4
616 * This function makes sure that an empty rx fifo is not read on these silicons
617 * (OMAP1/2/3430 are not affected)
619 static unsigned int serial_in_override(struct uart_port *up, int offset)
621 if (UART_RX == offset) {
623 lsr = __serial_read_reg(up, UART_LSR);
624 if (!(lsr & UART_LSR_DR))
628 return __serial_read_reg(up, offset);
631 static void serial_out_override(struct uart_port *up, int offset, int value)
633 unsigned int status, tmout = 10000;
635 status = __serial_read_reg(up, UART_LSR);
636 while (!(status & UART_LSR_THRE)) {
637 /* Wait up to 10ms for the character(s) to be sent. */
641 status = __serial_read_reg(up, UART_LSR);
643 __serial_write_reg(up, offset, value);
645 void __init omap_serial_early_init(void)
650 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
653 nr_ports = ARRAY_SIZE(omap_uart);
656 * Make sure the serial ports are muxed on at this point.
657 * You have to mux them off in device drivers later on
661 for (i = 0; i < nr_ports; i++) {
662 struct omap_uart_state *uart = &omap_uart[i];
663 struct platform_device *pdev = &uart->pdev;
664 struct device *dev = &pdev->dev;
665 struct plat_serial8250_port *p = dev->platform_data;
668 * Module 4KB + L4 interconnect 4KB
669 * Static mapping, never released
671 p->membase = ioremap(p->mapbase, SZ_8K);
673 printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
677 sprintf(name, "uart%d_ick", i + 1);
678 uart->ick = clk_get(NULL, name);
679 if (IS_ERR(uart->ick)) {
680 printk(KERN_ERR "Could not get uart%d_ick\n", i + 1);
684 sprintf(name, "uart%d_fck", i+1);
685 uart->fck = clk_get(NULL, name);
686 if (IS_ERR(uart->fck)) {
687 printk(KERN_ERR "Could not get uart%d_fck\n", i + 1);
691 /* FIXME: Remove this once the clkdev is ready */
692 if (!cpu_is_omap44xx()) {
693 if (!uart->ick || !uart->fck)
698 p->private_data = uart;
701 if (cpu_is_omap44xx())
707 * omap_serial_init_port() - initialize single serial port
708 * @port: serial port number (0-3)
710 * This function initialies serial driver for given @port only.
711 * Platforms can call this function instead of omap_serial_init()
712 * if they don't plan to use all available UARTs as serial ports.
714 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
715 * use only one of the two.
717 void __init omap_serial_init_port(int port)
719 struct omap_uart_state *uart;
720 struct platform_device *pdev;
724 BUG_ON(port >= ARRAY_SIZE(omap_uart));
726 uart = &omap_uart[port];
730 omap_uart_enable_clocks(uart);
732 omap_uart_reset(uart);
733 omap_uart_idle_init(uart);
735 list_add_tail(&uart->node, &uart_list);
737 if (WARN_ON(platform_device_register(pdev)))
740 if ((cpu_is_omap34xx() && uart->padconf) ||
741 (uart->wk_en && uart->wk_mask)) {
742 device_init_wakeup(dev, true);
743 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
747 * omap44xx: Never read empty UART fifo
748 * omap3xxx: Never read empty UART fifo on UARTs
751 if (cpu_is_omap44xx()) {
752 uart->p->serial_in = serial_in_override;
753 uart->p->serial_out = serial_out_override;
754 } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
755 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
756 uart->p->serial_in = serial_in_override;
757 uart->p->serial_out = serial_out_override;
762 * omap_serial_init() - intialize all supported serial ports
764 * Initializes all available UARTs as serial ports. Platforms
765 * can call this function when they want to have default behaviour
766 * for serial ports (e.g initialize them all as serial ports).
768 void __init omap_serial_init(void)
772 if (!(cpu_is_omap3630() || cpu_is_omap4430()))
775 nr_ports = ARRAY_SIZE(omap_uart);
777 for (i = 0; i < nr_ports; i++)
778 omap_serial_init_port(i);