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   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29
  30 #include <plat/sram.h>
  31 #include <plat/clockdomain.h>
  32 #include <plat/powerdomain.h>
  33 #include <plat/control.h>
  34 #include <plat/serial.h>
  35 #include <plat/sdrc.h>
  36 #include <plat/prcm.h>
  37 #include <plat/gpmc.h>
  38 #include <plat/dma.h>
  39 #include <plat/dmtimer.h>
  40
  41 #include <asm/tlbflush.h>
  42
  43 #include "cm.h"
  44 #include "cm-regbits-34xx.h"
  45 #include "prm-regbits-34xx.h"
  46
  47 #include "prm.h"
  48 #include "pm.h"
  49 #include "sdrc.h"
  50
  51 /* Scratchpad offsets */
  52 #define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
  53 #define OMAP343X_TABLE_VALUE_OFFSET        0x30
  54 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
  55
  56 u32 enable_off_mode;
  57 u32 sleep_while_idle;
  58 u32 wakeup_timer_seconds;
  59
  60 struct power_state {
  61         struct powerdomain *pwrdm;
  62         u32 next_state;
  63 #ifdef CONFIG_SUSPEND
  64         u32 saved_state;
  65 #endif
  66         struct list_head node;
  67 };
  68
  69 static LIST_HEAD(pwrst_list);
  70
  71 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  72
  73 static int (*_omap_save_secure_sram)(u32 *addr);
  74
  75 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  76 static struct powerdomain *core_pwrdm, *per_pwrdm;
  77 static struct powerdomain *cam_pwrdm;
  78
  79 static inline void omap3_per_save_context(void)
  80 {
  81         omap_gpio_save_context();
  82 }
  83
  84 static inline void omap3_per_restore_context(void)
  85 {
  86         omap_gpio_restore_context();
  87 }
  88
  89 static void omap3_enable_io_chain(void)
  90 {
  91         int timeout = 0;
  92
  93         if (omap_rev() >= OMAP3430_REV_ES3_1) {
  94                 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
  95                 /* Do a readback to assure write has been done */
  96                 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
  97
  98                 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
  99                          OMAP3430_ST_IO_CHAIN)) {
 100                         timeout++;
 101                         if (timeout > 1000) {
 102                                 printk(KERN_ERR "Wake up daisy chain "
 103                                        "activation failed.\n");
 104                                 return;
 105                         }
 106                         prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
 107                                              WKUP_MOD, PM_WKST);
 108                 }
 109         }
 110 }
 111
 112 static void omap3_disable_io_chain(void)
 113 {
 114         if (omap_rev() >= OMAP3430_REV_ES3_1)
 115                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
 116 }
 117
 118 static void omap3_core_save_context(void)
 119 {
 120         u32 control_padconf_off;
 121
 122         /* Save the padconf registers */
 123         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 124         control_padconf_off |= START_PADCONF_SAVE;
 125         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 126         /* wait for the save to complete */
 127         while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 128                         & PADCONF_SAVE_DONE)
 129                 ;
 130         /* Save the Interrupt controller context */
 131         omap_intc_save_context();
 132         /* Save the GPMC context */
 133         omap3_gpmc_save_context();
 134         /* Save the system control module context, padconf already save above*/
 135         omap3_control_save_context();
 136         omap_dma_global_context_save();
 137 }
 138
 139 static void omap3_core_restore_context(void)
 140 {
 141         /* Restore the control module context, padconf restored by h/w */
 142         omap3_control_restore_context();
 143         /* Restore the GPMC context */
 144         omap3_gpmc_restore_context();
 145         /* Restore the interrupt controller context */
 146         omap_intc_restore_context();
 147         omap_dma_global_context_restore();
 148 }
 149
 150 /*
 151  * FIXME: This function should be called before entering off-mode after
 152  * OMAP3 secure services have been accessed. Currently it is only called
 153  * once during boot sequence, but this works as we are not using secure
 154  * services.
 155  */
 156 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 157 {
 158         u32 ret;
 159
 160         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 161                 /*
 162                  * MPU next state must be set to POWER_ON temporarily,
 163                  * otherwise the WFI executed inside the ROM code
 164                  * will hang the system.
 165                  */
 166                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 167                 ret = _omap_save_secure_sram((u32 *)
 168                                 __pa(omap3_secure_ram_storage));
 169                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 170                 /* Following is for error tracking, it should not happen */
 171                 if (ret) {
 172                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 173                                 ret);
 174                         while (1)
 175                                 ;
 176                 }
 177         }
 178 }
 179
 180 /*
 181  * PRCM Interrupt Handler Helper Function
 182  *
 183  * The purpose of this function is to clear any wake-up events latched
 184  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 185  * may occur whilst attempting to clear a PM_WKST_x register and thus
 186  * set another bit in this register. A while loop is used to ensure
 187  * that any peripheral wake-up events occurring while attempting to
 188  * clear the PM_WKST_x are detected and cleared.
 189  */
 190 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 191 {
 192         u32 wkst, fclk, iclk, clken;
 193         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 194         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 195         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 196         u16 grpsel_off = (regs == 3) ?
 197                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 198         int c = 0;
 199
 200         wkst = prm_read_mod_reg(module, wkst_off);
 201         wkst &= prm_read_mod_reg(module, grpsel_off);
 202         if (wkst) {
 203                 iclk = cm_read_mod_reg(module, iclk_off);
 204                 fclk = cm_read_mod_reg(module, fclk_off);
 205                 while (wkst) {
 206                         clken = wkst;
 207                         cm_set_mod_reg_bits(clken, module, iclk_off);
 208                         /*
 209                          * For USBHOST, we don't know whether HOST1 or
 210                          * HOST2 woke us up, so enable both f-clocks
 211                          */
 212                         if (module == OMAP3430ES2_USBHOST_MOD)
 213                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 214                         cm_set_mod_reg_bits(clken, module, fclk_off);
 215                         prm_write_mod_reg(wkst, module, wkst_off);
 216                         wkst = prm_read_mod_reg(module, wkst_off);
 217                         c++;
 218                 }
 219                 cm_write_mod_reg(iclk, module, iclk_off);
 220                 cm_write_mod_reg(fclk, module, fclk_off);
 221         }
 222
 223         return c;
 224 }
 225
 226 static int _prcm_int_handle_wakeup(void)
 227 {
 228         int c;
 229
 230         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 231         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 232         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 233         if (omap_rev() > OMAP3430_REV_ES1_0) {
 234                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 235                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 236         }
 237
 238         return c;
 239 }
 240
 241 /*
 242  * PRCM Interrupt Handler
 243  *
 244  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 245  * interrupts from the PRCM for the MPU. These bits must be cleared in
 246  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 247  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 248  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 249  * register indicates that a wake-up event is pending for the MPU and
 250  * this bit can only be cleared if the all the wake-up events latched
 251  * in the various PM_WKST_x registers have been cleared. The interrupt
 252  * handler is implemented using a do-while loop so that if a wake-up
 253  * event occurred during the processing of the prcm interrupt handler
 254  * (setting a bit in the corresponding PM_WKST_x register and thus
 255  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 256  * this would be handled.
 257  */
 258 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 259 {
 260         u32 irqstatus_mpu;
 261         int c = 0;
 262
 263         do {
 264                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 265                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 266
 267                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 268                         c = _prcm_int_handle_wakeup();
 269
 270                         /*
 271                          * Is the MPU PRCM interrupt handler racing with the
 272                          * IVA2 PRCM interrupt handler ?
 273                          */
 274                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 275                              "but no wakeup sources are marked\n");
 276                 } else {
 277                         /* XXX we need to expand our PRCM interrupt handler */
 278                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 279                              "no code to handle it (%08x)\n", irqstatus_mpu);
 280                 }
 281
 282                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 283                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 284
 285         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 286
 287         return IRQ_HANDLED;
 288 }
 289
 290 static void restore_control_register(u32 val)
 291 {
 292         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 293 }
 294
 295 /* Function to restore the table entry that was modified for enabling MMU */
 296 static void restore_table_entry(void)
 297 {
 298         u32 *scratchpad_address;
 299         u32 previous_value, control_reg_value;
 300         u32 *address;
 301
 302         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 303
 304         /* Get address of entry that was modified */
 305         address = (u32 *)__raw_readl(scratchpad_address +
 306                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 307         /* Get the previous value which needs to be restored */
 308         previous_value = __raw_readl(scratchpad_address +
 309                                      OMAP343X_TABLE_VALUE_OFFSET);
 310         address = __va(address);
 311         *address = previous_value;
 312         flush_tlb_all();
 313         control_reg_value = __raw_readl(scratchpad_address
 314                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 315         /* This will enable caches and prediction */
 316         restore_control_register(control_reg_value);
 317 }
 318
 319 void omap_sram_idle(void)
 320 {
 321         /* Variable to tell what needs to be saved and restored
 322          * in omap_sram_idle*/
 323         /* save_state = 0 => Nothing to save and restored */
 324         /* save_state = 1 => Only L1 and logic lost */
 325         /* save_state = 2 => Only L2 lost */
 326         /* save_state = 3 => L1, L2 and logic lost */
 327         int save_state = 0;
 328         int mpu_next_state = PWRDM_POWER_ON;
 329         int per_next_state = PWRDM_POWER_ON;
 330         int core_next_state = PWRDM_POWER_ON;
 331         int core_prev_state, per_prev_state;
 332         u32 sdrc_pwr = 0;
 333         int per_state_modified = 0;
 334
 335         if (!_omap_sram_idle)
 336                 return;
 337
 338         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 339         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 340         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 341         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 342
 343         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 344         switch (mpu_next_state) {
 345         case PWRDM_POWER_ON:
 346         case PWRDM_POWER_RET:
 347                 /* No need to save context */
 348                 save_state = 0;
 349                 break;
 350         case PWRDM_POWER_OFF:
 351                 save_state = 3;
 352                 break;
 353         default:
 354                 /* Invalid state */
 355                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 356                 return;
 357         }
 358         pwrdm_pre_transition();
 359
 360         /* NEON control */
 361         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 362                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 363
 364         /* PER */
 365         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 366         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 367         if (per_next_state < PWRDM_POWER_ON) {
 368                 omap_uart_prepare_idle(2);
 369                 omap2_gpio_prepare_for_retention();
 370                 if (per_next_state == PWRDM_POWER_OFF) {
 371                         if (core_next_state == PWRDM_POWER_ON) {
 372                                 per_next_state = PWRDM_POWER_RET;
 373                                 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
 374                                 per_state_modified = 1;
 375                         } else
 376                                 omap3_per_save_context();
 377                 }
 378         }
 379
 380         if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
 381                 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 382
 383         /* CORE */
 384         if (core_next_state < PWRDM_POWER_ON) {
 385                 omap_uart_prepare_idle(0);
 386                 omap_uart_prepare_idle(1);
 387                 if (core_next_state == PWRDM_POWER_OFF) {
 388                         omap3_core_save_context();
 389                         omap3_prcm_save_context();
 390                 }
 391                 /* Enable IO-PAD and IO-CHAIN wakeups */
 392                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 393                 omap3_enable_io_chain();
 394         }
 395
 396         /*
 397         * On EMU/HS devices ROM code restores a SRDC value
 398         * from scratchpad which has automatic self refresh on timeout
 399         * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
 400         * Hence store/restore the SDRC_POWER register here.
 401         */
 402         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 403             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 404             core_next_state == PWRDM_POWER_OFF)
 405                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 406
 407         /*
 408          * omap3_arm_context is the location where ARM registers
 409          * get saved. The restore path then reads from this
 410          * location and restores them back.
 411          */
 412         _omap_sram_idle(omap3_arm_context, save_state);
 413         cpu_init();
 414
 415         /* Restore normal SDRC POWER settings */
 416         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 417             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 418             core_next_state == PWRDM_POWER_OFF)
 419                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 420
 421         /* Restore table entry modified during MMU restoration */
 422         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 423                 restore_table_entry();
 424
 425         /* CORE */
 426         if (core_next_state < PWRDM_POWER_ON) {
 427                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 428                 if (core_prev_state == PWRDM_POWER_OFF) {
 429                         omap3_core_restore_context();
 430                         omap3_prcm_restore_context();
 431                         omap3_sram_restore_context();
 432                         omap2_sms_restore_context();
 433                 }
 434                 omap_uart_resume_idle(0);
 435                 omap_uart_resume_idle(1);
 436                 if (core_next_state == PWRDM_POWER_OFF)
 437                         prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
 438                                                OMAP3430_GR_MOD,
 439                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 440         }
 441
 442         /* PER */
 443         if (per_next_state < PWRDM_POWER_ON) {
 444                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 445                 if (per_prev_state == PWRDM_POWER_OFF)
 446                         omap3_per_restore_context();
 447                 omap2_gpio_resume_after_retention();
 448                 omap_uart_resume_idle(2);
 449                 if (per_state_modified)
 450                         pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
 451         }
 452
 453         /* Disable IO-PAD and IO-CHAIN wakeup */
 454         if (core_next_state < PWRDM_POWER_ON) {
 455                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 456                 omap3_disable_io_chain();
 457         }
 458
 459         pwrdm_post_transition();
 460
 461         omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 462 }
 463
 464 /*
 465  * Check if functional clocks are enabled before entering
 466  * sleep. This function could be behind CONFIG_PM_DEBUG
 467  * when all drivers are configuring their sysconfig registers
 468  * properly and using their clocks properly.
 469  */
 470 static int omap3_fclks_active(void)
 471 {
 472         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 473                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 474
 475         fck_core1 = cm_read_mod_reg(CORE_MOD,
 476                                     CM_FCLKEN1);
 477         if (omap_rev() > OMAP3430_REV_ES1_0) {
 478                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 479                                             OMAP3430ES2_CM_FCLKEN3);
 480                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 481                                           CM_FCLKEN);
 482                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 483                                               CM_FCLKEN);
 484         } else
 485                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 486                                           OMAP3430ES2_CM_FCLKEN3);
 487         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 488                                   CM_FCLKEN);
 489         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 490                                   CM_FCLKEN);
 491         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 492                                   CM_FCLKEN);
 493
 494         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 495         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 496         fck_per &= ~OMAP3430_EN_UART3;
 497
 498         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 499             fck_cam | fck_per | fck_usbhost)
 500                 return 1;
 501         return 0;
 502 }
 503
 504 int omap3_can_sleep(void)
 505 {
 506         if (!sleep_while_idle)
 507                 return 0;
 508         if (!omap_uart_can_sleep())
 509                 return 0;
 510         if (omap3_fclks_active())
 511                 return 0;
 512         return 1;
 513 }
 514
 515 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 516  * RET are supported. Function is assuming that clkdm doesn't have
 517  * hw_sup mode enabled. */
 518 int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 519 {
 520         u32 cur_state;
 521         int sleep_switch = 0;
 522         int ret = 0;
 523
 524         if (pwrdm == NULL || IS_ERR(pwrdm))
 525                 return -EINVAL;
 526
 527         while (!(pwrdm->pwrsts & (1 << state))) {
 528                 if (state == PWRDM_POWER_OFF)
 529                         return ret;
 530                 state--;
 531         }
 532
 533         cur_state = pwrdm_read_next_pwrst(pwrdm);
 534         if (cur_state == state)
 535                 return ret;
 536
 537         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 538                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 539                 sleep_switch = 1;
 540                 pwrdm_wait_transition(pwrdm);
 541         }
 542
 543         ret = pwrdm_set_next_pwrst(pwrdm, state);
 544         if (ret) {
 545                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 546                        pwrdm->name);
 547                 goto err;
 548         }
 549
 550         if (sleep_switch) {
 551                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 552                 pwrdm_wait_transition(pwrdm);
 553                 pwrdm_state_switch(pwrdm);
 554         }
 555
 556 err:
 557         return ret;
 558 }
 559
 560 static void omap3_pm_idle(void)
 561 {
 562         local_irq_disable();
 563         local_fiq_disable();
 564
 565         if (!omap3_can_sleep())
 566                 goto out;
 567
 568         if (omap_irq_pending())
 569                 goto out;
 570
 571         omap_sram_idle();
 572
 573 out:
 574         local_fiq_enable();
 575         local_irq_enable();
 576 }
 577
 578 #ifdef CONFIG_SUSPEND
 579 static suspend_state_t suspend_state;
 580
 581 static void omap2_pm_wakeup_on_timer(u32 seconds)
 582 {
 583         u32 tick_rate, cycles;
 584
 585         if (!seconds)
 586                 return;
 587
 588         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
 589         cycles = tick_rate * seconds;
 590         omap_dm_timer_stop(gptimer_wakeup);
 591         omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
 592
 593         pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
 594                 seconds, cycles, tick_rate);
 595 }
 596
 597 static int omap3_pm_prepare(void)
 598 {
 599         disable_hlt();
 600         return 0;
 601 }
 602
 603 static int omap3_pm_suspend(void)
 604 {
 605         struct power_state *pwrst;
 606         int state, ret = 0;
 607
 608         if (wakeup_timer_seconds)
 609                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
 610
 611         /* Read current next_pwrsts */
 612         list_for_each_entry(pwrst, &pwrst_list, node)
 613                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 614         /* Set ones wanted by suspend */
 615         list_for_each_entry(pwrst, &pwrst_list, node) {
 616                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 617                         goto restore;
 618                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 619                         goto restore;
 620         }
 621
 622         omap_uart_prepare_suspend();
 623         omap_sram_idle();
 624
 625 restore:
 626         /* Restore next_pwrsts */
 627         list_for_each_entry(pwrst, &pwrst_list, node) {
 628                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 629                 if (state > pwrst->next_state) {
 630                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 631                                "target state %d\n",
 632                                pwrst->pwrdm->name, pwrst->next_state);
 633                         ret = -1;
 634                 }
 635                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 636         }
 637         if (ret)
 638                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 639         else
 640                 printk(KERN_INFO "Successfully put all powerdomains "
 641                        "to target state\n");
 642
 643         return ret;
 644 }
 645
 646 static int omap3_pm_enter(suspend_state_t unused)
 647 {
 648         int ret = 0;
 649
 650         switch (suspend_state) {
 651         case PM_SUSPEND_STANDBY:
 652         case PM_SUSPEND_MEM:
 653                 ret = omap3_pm_suspend();
 654                 break;
 655         default:
 656                 ret = -EINVAL;
 657         }
 658
 659         return ret;
 660 }
 661
 662 static void omap3_pm_finish(void)
 663 {
 664         enable_hlt();
 665 }
 666
 667 /* Hooks to enable / disable UART interrupts during suspend */
 668 static int omap3_pm_begin(suspend_state_t state)
 669 {
 670         suspend_state = state;
 671         omap_uart_enable_irqs(0);
 672         return 0;
 673 }
 674
 675 static void omap3_pm_end(void)
 676 {
 677         suspend_state = PM_SUSPEND_ON;
 678         omap_uart_enable_irqs(1);
 679         return;
 680 }
 681
 682 static struct platform_suspend_ops omap_pm_ops = {
 683         .begin          = omap3_pm_begin,
 684         .end            = omap3_pm_end,
 685         .prepare        = omap3_pm_prepare,
 686         .enter          = omap3_pm_enter,
 687         .finish         = omap3_pm_finish,
 688         .valid          = suspend_valid_only_mem,
 689 };
 690 #endif /* CONFIG_SUSPEND */
 691
 692
 693 /**
 694  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 695  *                   retention
 696  *
 697  * In cases where IVA2 is activated by bootcode, it may prevent
 698  * full-chip retention or off-mode because it is not idle.  This
 699  * function forces the IVA2 into idle state so it can go
 700  * into retention/off and thus allow full-chip retention/off.
 701  *
 702  **/
 703 static void __init omap3_iva_idle(void)
 704 {
 705         /* ensure IVA2 clock is disabled */
 706         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 707
 708         /* if no clock activity, nothing else to do */
 709         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 710               OMAP3430_CLKACTIVITY_IVA2_MASK))
 711                 return;
 712
 713         /* Reset IVA2 */
 714         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 715                           OMAP3430_RST2_IVA2 |
 716                           OMAP3430_RST3_IVA2,
 717                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 718
 719         /* Enable IVA2 clock */
 720         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 721                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 722
 723         /* Set IVA2 boot mode to 'idle' */
 724         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 725                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 726
 727         /* Un-reset IVA2 */
 728         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 729
 730         /* Disable IVA2 clock */
 731         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 732
 733         /* Reset IVA2 */
 734         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 735                           OMAP3430_RST2_IVA2 |
 736                           OMAP3430_RST3_IVA2,
 737                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 738 }
 739
 740 static void __init omap3_d2d_idle(void)
 741 {
 742         u16 mask, padconf;
 743
 744         /* In a stand alone OMAP3430 where there is not a stacked
 745          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 746          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 747          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 748         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 749         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 750         padconf |= mask;
 751         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 752
 753         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 754         padconf |= mask;
 755         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 756
 757         /* reset modem */
 758         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 759                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 760                           CORE_MOD, RM_RSTCTRL);
 761         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 762 }
 763
 764 static void __init prcm_setup_regs(void)
 765 {
 766         /* XXX Reset all wkdeps. This should be done when initializing
 767          * powerdomains */
 768         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 769         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 770         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 771         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 772         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 773         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 774         if (omap_rev() > OMAP3430_REV_ES1_0) {
 775                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 776                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 777         } else
 778                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 779
 780         /*
 781          * Enable interface clock autoidle for all modules.
 782          * Note that in the long run this should be done by clockfw
 783          */
 784         cm_write_mod_reg(
 785                 OMAP3430_AUTO_MODEM |
 786                 OMAP3430ES2_AUTO_MMC3 |
 787                 OMAP3430ES2_AUTO_ICR |
 788                 OMAP3430_AUTO_AES2 |
 789                 OMAP3430_AUTO_SHA12 |
 790                 OMAP3430_AUTO_DES2 |
 791                 OMAP3430_AUTO_MMC2 |
 792                 OMAP3430_AUTO_MMC1 |
 793                 OMAP3430_AUTO_MSPRO |
 794                 OMAP3430_AUTO_HDQ |
 795                 OMAP3430_AUTO_MCSPI4 |
 796                 OMAP3430_AUTO_MCSPI3 |
 797                 OMAP3430_AUTO_MCSPI2 |
 798                 OMAP3430_AUTO_MCSPI1 |
 799                 OMAP3430_AUTO_I2C3 |
 800                 OMAP3430_AUTO_I2C2 |
 801                 OMAP3430_AUTO_I2C1 |
 802                 OMAP3430_AUTO_UART2 |
 803                 OMAP3430_AUTO_UART1 |
 804                 OMAP3430_AUTO_GPT11 |
 805                 OMAP3430_AUTO_GPT10 |
 806                 OMAP3430_AUTO_MCBSP5 |
 807                 OMAP3430_AUTO_MCBSP1 |
 808                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 809                 OMAP3430_AUTO_MAILBOXES |
 810                 OMAP3430_AUTO_OMAPCTRL |
 811                 OMAP3430ES1_AUTO_FSHOSTUSB |
 812                 OMAP3430_AUTO_HSOTGUSB |
 813                 OMAP3430_AUTO_SAD2D |
 814                 OMAP3430_AUTO_SSI,
 815                 CORE_MOD, CM_AUTOIDLE1);
 816
 817         cm_write_mod_reg(
 818                 OMAP3430_AUTO_PKA |
 819                 OMAP3430_AUTO_AES1 |
 820                 OMAP3430_AUTO_RNG |
 821                 OMAP3430_AUTO_SHA11 |
 822                 OMAP3430_AUTO_DES1,
 823                 CORE_MOD, CM_AUTOIDLE2);
 824
 825         if (omap_rev() > OMAP3430_REV_ES1_0) {
 826                 cm_write_mod_reg(
 827                         OMAP3430_AUTO_MAD2D |
 828                         OMAP3430ES2_AUTO_USBTLL,
 829                         CORE_MOD, CM_AUTOIDLE3);
 830         }
 831
 832         cm_write_mod_reg(
 833                 OMAP3430_AUTO_WDT2 |
 834                 OMAP3430_AUTO_WDT1 |
 835                 OMAP3430_AUTO_GPIO1 |
 836                 OMAP3430_AUTO_32KSYNC |
 837                 OMAP3430_AUTO_GPT12 |
 838                 OMAP3430_AUTO_GPT1 ,
 839                 WKUP_MOD, CM_AUTOIDLE);
 840
 841         cm_write_mod_reg(
 842                 OMAP3430_AUTO_DSS,
 843                 OMAP3430_DSS_MOD,
 844                 CM_AUTOIDLE);
 845
 846         cm_write_mod_reg(
 847                 OMAP3430_AUTO_CAM,
 848                 OMAP3430_CAM_MOD,
 849                 CM_AUTOIDLE);
 850
 851         cm_write_mod_reg(
 852                 OMAP3430_AUTO_GPIO6 |
 853                 OMAP3430_AUTO_GPIO5 |
 854                 OMAP3430_AUTO_GPIO4 |
 855                 OMAP3430_AUTO_GPIO3 |
 856                 OMAP3430_AUTO_GPIO2 |
 857                 OMAP3430_AUTO_WDT3 |
 858                 OMAP3430_AUTO_UART3 |
 859                 OMAP3430_AUTO_GPT9 |
 860                 OMAP3430_AUTO_GPT8 |
 861                 OMAP3430_AUTO_GPT7 |
 862                 OMAP3430_AUTO_GPT6 |
 863                 OMAP3430_AUTO_GPT5 |
 864                 OMAP3430_AUTO_GPT4 |
 865                 OMAP3430_AUTO_GPT3 |
 866                 OMAP3430_AUTO_GPT2 |
 867                 OMAP3430_AUTO_MCBSP4 |
 868                 OMAP3430_AUTO_MCBSP3 |
 869                 OMAP3430_AUTO_MCBSP2,
 870                 OMAP3430_PER_MOD,
 871                 CM_AUTOIDLE);
 872
 873         if (omap_rev() > OMAP3430_REV_ES1_0) {
 874                 cm_write_mod_reg(
 875                         OMAP3430ES2_AUTO_USBHOST,
 876                         OMAP3430ES2_USBHOST_MOD,
 877                         CM_AUTOIDLE);
 878         }
 879
 880         /*
 881          * Set all plls to autoidle. This is needed until autoidle is
 882          * enabled by clockfw
 883          */
 884         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 885                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 886         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 887                          MPU_MOD,
 888                          CM_AUTOIDLE2);
 889         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 890                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 891                          PLL_MOD,
 892                          CM_AUTOIDLE);
 893         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 894                          PLL_MOD,
 895                          CM_AUTOIDLE2);
 896
 897         /*
 898          * Enable control of expternal oscillator through
 899          * sys_clkreq. In the long run clock framework should
 900          * take care of this.
 901          */
 902         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 903                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 904                              OMAP3430_GR_MOD,
 905                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 906
 907         /* setup wakup source */
 908         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 909                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 910                           WKUP_MOD, PM_WKEN);
 911         /* No need to write EN_IO, that is always enabled */
 912         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 913                           OMAP3430_EN_GPT12,
 914                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 915         /* For some reason IO doesn't generate wakeup event even if
 916          * it is selected to mpu wakeup goup */
 917         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 918                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 919
 920         /* Enable wakeups in PER */
 921         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 922                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 923                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 924                           OMAP3430_PER_MOD, PM_WKEN);
 925         /* and allow them to wake up MPU */
 926         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 927                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 928                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 929                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 930
 931         /* Don't attach IVA interrupts */
 932         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 933         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 934         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 935         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 936
 937         /* Clear any pending 'reset' flags */
 938         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 939         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 940         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 941         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 942         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 943         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 944         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 945
 946         /* Clear any pending PRCM interrupts */
 947         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 948
 949         /* Don't attach IVA interrupts */
 950         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 951         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 952         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 953         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 954
 955         /* Clear any pending 'reset' flags */
 956         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 957         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 958         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 959         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 960         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 961         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 962         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 963
 964         /* Clear any pending PRCM interrupts */
 965         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 966
 967         omap3_iva_idle();
 968         omap3_d2d_idle();
 969 }
 970
 971 void omap3_pm_off_mode_enable(int enable)
 972 {
 973         struct power_state *pwrst;
 974         u32 state;
 975
 976         if (enable)
 977                 state = PWRDM_POWER_OFF;
 978         else
 979                 state = PWRDM_POWER_RET;
 980
 981         list_for_each_entry(pwrst, &pwrst_list, node) {
 982                 pwrst->next_state = state;
 983                 set_pwrdm_state(pwrst->pwrdm, state);
 984         }
 985 }
 986
 987 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 988 {
 989         struct power_state *pwrst;
 990
 991         list_for_each_entry(pwrst, &pwrst_list, node) {
 992                 if (pwrst->pwrdm == pwrdm)
 993                         return pwrst->next_state;
 994         }
 995         return -EINVAL;
 996 }
 997
 998 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 999 {
1000         struct power_state *pwrst;
1001
1002         list_for_each_entry(pwrst, &pwrst_list, node) {
1003                 if (pwrst->pwrdm == pwrdm) {
1004                         pwrst->next_state = state;
1005                         return 0;
1006                 }
1007         }
1008         return -EINVAL;
1009 }
1010
1011 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
1012 {
1013         struct power_state *pwrst;
1014
1015         if (!pwrdm->pwrsts)
1016                 return 0;
1017
1018         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
1019         if (!pwrst)
1020                 return -ENOMEM;
1021         pwrst->pwrdm = pwrdm;
1022         pwrst->next_state = PWRDM_POWER_RET;
1023         list_add(&pwrst->node, &pwrst_list);
1024
1025         if (pwrdm_has_hdwr_sar(pwrdm))
1026                 pwrdm_enable_hdwr_sar(pwrdm);
1027
1028         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
1029 }
1030
1031 /*
1032  * Enable hw supervised mode for all clockdomains if it's
1033  * supported. Initiate sleep transition for other clockdomains, if
1034  * they are not used
1035  */
1036 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
1037 {
1038         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1039                 omap2_clkdm_allow_idle(clkdm);
1040         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1041                  atomic_read(&clkdm->usecount) == 0)
1042                 omap2_clkdm_sleep(clkdm);
1043         return 0;
1044 }
1045
1046 void omap_push_sram_idle(void)
1047 {
1048         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1049                                         omap34xx_cpu_suspend_sz);
1050         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1051                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1052                                 save_secure_ram_context_sz);
1053 }
1054
1055 static int __init omap3_pm_init(void)
1056 {
1057         struct power_state *pwrst, *tmp;
1058         int ret;
1059
1060         if (!cpu_is_omap34xx())
1061                 return -ENODEV;
1062
1063         printk(KERN_ERR "Power Management for TI OMAP3.\n");
1064
1065         /* XXX prcm_setup_regs needs to be before enabling hw
1066          * supervised mode for powerdomains */
1067         prcm_setup_regs();
1068
1069         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1070                           (irq_handler_t)prcm_interrupt_handler,
1071                           IRQF_DISABLED, "prcm", NULL);
1072         if (ret) {
1073                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1074                        INT_34XX_PRCM_MPU_IRQ);
1075                 goto err1;
1076         }
1077
1078         ret = pwrdm_for_each(pwrdms_setup, NULL);
1079         if (ret) {
1080                 printk(KERN_ERR "Failed to setup powerdomains\n");
1081                 goto err2;
1082         }
1083
1084         (void) clkdm_for_each(clkdms_setup, NULL);
1085
1086         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1087         if (mpu_pwrdm == NULL) {
1088                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1089                 goto err2;
1090         }
1091
1092         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1093         per_pwrdm = pwrdm_lookup("per_pwrdm");
1094         core_pwrdm = pwrdm_lookup("core_pwrdm");
1095         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1096
1097         omap_push_sram_idle();
1098 #ifdef CONFIG_SUSPEND
1099         suspend_set_ops(&omap_pm_ops);
1100 #endif /* CONFIG_SUSPEND */
1101
1102         pm_idle = omap3_pm_idle;
1103         omap3_idle_init();
1104
1105         pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1106         /*
1107          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1108          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
1109          * waking up PER with every CORE wakeup - see
1110          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1111         */
1112         pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1113
1114         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1115                 omap3_secure_ram_storage =
1116                         kmalloc(0x803F, GFP_KERNEL);
1117                 if (!omap3_secure_ram_storage)
1118                         printk(KERN_ERR "Memory allocation failed when"
1119                                         "allocating for secure sram context\n");
1120
1121                 local_irq_disable();
1122                 local_fiq_disable();
1123
1124                 omap_dma_global_context_save();
1125                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1126                 omap_dma_global_context_restore();
1127
1128                 local_irq_enable();
1129                 local_fiq_enable();
1130         }
1131
1132         omap3_save_scratchpad_contents();
1133 err1:
1134         return ret;
1135 err2:
1136         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1137         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1138                 list_del(&pwrst->node);
1139                 kfree(pwrst);
1140         }
1141         return ret;
1142 }
1143
1144 late_initcall(omap3_pm_init);