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   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/clk.h>
  21 #include <linux/list.h>
  22
  23 #include <plat/control.h>
  24 #include <plat/clkdev_omap.h>
  25
  26 #include "clock.h"
  27 #include "clock3xxx.h"
  28 #include "clock34xx.h"
  29 #include "clock36xx.h"
  30 #include "clock3517.h"
  31
  32 #include "cm.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "prm.h"
  35 #include "prm-regbits-34xx.h"
  36
  37 /*
  38  * clocks
  39  */
  40
  41 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  42
  43 /* Maximum DPLL multiplier, divider values for OMAP3 */
  44 #define OMAP3_MAX_DPLL_MULT             2047
  45 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  46 #define OMAP3_MAX_DPLL_DIV              128
  47
  48 /*
  49  * DPLL1 supplies clock to the MPU.
  50  * DPLL2 supplies clock to the IVA2.
  51  * DPLL3 supplies CORE domain clocks.
  52  * DPLL4 supplies peripheral clocks.
  53  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  54  */
  55
  56 /* Forward declarations for DPLL bypass clocks */
  57 static struct clk dpll1_fck;
  58 static struct clk dpll2_fck;
  59
  60 /* PRM CLOCKS */
  61
  62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  63 static struct clk omap_32k_fck = {
  64         .name           = "omap_32k_fck",
  65         .ops            = &clkops_null,
  66         .rate           = 32768,
  67 };
  68
  69 static struct clk secure_32k_fck = {
  70         .name           = "secure_32k_fck",
  71         .ops            = &clkops_null,
  72         .rate           = 32768,
  73 };
  74
  75 /* Virtual source clocks for osc_sys_ck */
  76 static struct clk virt_12m_ck = {
  77         .name           = "virt_12m_ck",
  78         .ops            = &clkops_null,
  79         .rate           = 12000000,
  80 };
  81
  82 static struct clk virt_13m_ck = {
  83         .name           = "virt_13m_ck",
  84         .ops            = &clkops_null,
  85         .rate           = 13000000,
  86 };
  87
  88 static struct clk virt_16_8m_ck = {
  89         .name           = "virt_16_8m_ck",
  90         .ops            = &clkops_null,
  91         .rate           = 16800000,
  92 };
  93
  94 static struct clk virt_19_2m_ck = {
  95         .name           = "virt_19_2m_ck",
  96         .ops            = &clkops_null,
  97         .rate           = 19200000,
  98 };
  99
 100 static struct clk virt_26m_ck = {
 101         .name           = "virt_26m_ck",
 102         .ops            = &clkops_null,
 103         .rate           = 26000000,
 104 };
 105
 106 static struct clk virt_38_4m_ck = {
 107         .name           = "virt_38_4m_ck",
 108         .ops            = &clkops_null,
 109         .rate           = 38400000,
 110 };
 111
 112 static const struct clksel_rate osc_sys_12m_rates[] = {
 113         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 114         { .div = 0 }
 115 };
 116
 117 static const struct clksel_rate osc_sys_13m_rates[] = {
 118         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 119         { .div = 0 }
 120 };
 121
 122 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 123         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 124         { .div = 0 }
 125 };
 126
 127 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 128         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 129         { .div = 0 }
 130 };
 131
 132 static const struct clksel_rate osc_sys_26m_rates[] = {
 133         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 134         { .div = 0 }
 135 };
 136
 137 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 138         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 139         { .div = 0 }
 140 };
 141
 142 static const struct clksel osc_sys_clksel[] = {
 143         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 144         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 145         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 146         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 147         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 148         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 149         { .parent = NULL },
 150 };
 151
 152 /* Oscillator clock */
 153 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 154 static struct clk osc_sys_ck = {
 155         .name           = "osc_sys_ck",
 156         .ops            = &clkops_null,
 157         .init           = &omap2_init_clksel_parent,
 158         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 159         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 160         .clksel         = osc_sys_clksel,
 161         /* REVISIT: deal with autoextclkmode? */
 162         .recalc         = &omap2_clksel_recalc,
 163 };
 164
 165 static const struct clksel_rate div2_rates[] = {
 166         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 167         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 168         { .div = 0 }
 169 };
 170
 171 static const struct clksel sys_clksel[] = {
 172         { .parent = &osc_sys_ck, .rates = div2_rates },
 173         { .parent = NULL }
 174 };
 175
 176 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 177 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 178 static struct clk sys_ck = {
 179         .name           = "sys_ck",
 180         .ops            = &clkops_null,
 181         .parent         = &osc_sys_ck,
 182         .init           = &omap2_init_clksel_parent,
 183         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 184         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 185         .clksel         = sys_clksel,
 186         .recalc         = &omap2_clksel_recalc,
 187 };
 188
 189 static struct clk sys_altclk = {
 190         .name           = "sys_altclk",
 191         .ops            = &clkops_null,
 192 };
 193
 194 /* Optional external clock input for some McBSPs */
 195 static struct clk mcbsp_clks = {
 196         .name           = "mcbsp_clks",
 197         .ops            = &clkops_null,
 198 };
 199
 200 /* PRM EXTERNAL CLOCK OUTPUT */
 201
 202 static struct clk sys_clkout1 = {
 203         .name           = "sys_clkout1",
 204         .ops            = &clkops_omap2_dflt,
 205         .parent         = &osc_sys_ck,
 206         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 207         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 208         .recalc         = &followparent_recalc,
 209 };
 210
 211 /* DPLLS */
 212
 213 /* CM CLOCKS */
 214
 215 static const struct clksel_rate div16_dpll_rates[] = {
 216         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 217         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 218         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 219         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 220         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 221         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 222         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 223         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 224         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 225         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 226         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 227         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 228         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 229         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 230         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 231         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 232         { .div = 0 }
 233 };
 234
 235 static const struct clksel_rate div32_dpll4_rates_3630[] = {
 236         { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
 237         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
 238         { .div = 3, .val = 3, .flags = RATE_IN_36XX },
 239         { .div = 4, .val = 4, .flags = RATE_IN_36XX },
 240         { .div = 5, .val = 5, .flags = RATE_IN_36XX },
 241         { .div = 6, .val = 6, .flags = RATE_IN_36XX },
 242         { .div = 7, .val = 7, .flags = RATE_IN_36XX },
 243         { .div = 8, .val = 8, .flags = RATE_IN_36XX },
 244         { .div = 9, .val = 9, .flags = RATE_IN_36XX },
 245         { .div = 10, .val = 10, .flags = RATE_IN_36XX },
 246         { .div = 11, .val = 11, .flags = RATE_IN_36XX },
 247         { .div = 12, .val = 12, .flags = RATE_IN_36XX },
 248         { .div = 13, .val = 13, .flags = RATE_IN_36XX },
 249         { .div = 14, .val = 14, .flags = RATE_IN_36XX },
 250         { .div = 15, .val = 15, .flags = RATE_IN_36XX },
 251         { .div = 16, .val = 16, .flags = RATE_IN_36XX },
 252         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
 253         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
 254         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
 255         { .div = 20, .val = 20, .flags = RATE_IN_36XX },
 256         { .div = 21, .val = 21, .flags = RATE_IN_36XX },
 257         { .div = 22, .val = 22, .flags = RATE_IN_36XX },
 258         { .div = 23, .val = 23, .flags = RATE_IN_36XX },
 259         { .div = 24, .val = 24, .flags = RATE_IN_36XX },
 260         { .div = 25, .val = 25, .flags = RATE_IN_36XX },
 261         { .div = 26, .val = 26, .flags = RATE_IN_36XX },
 262         { .div = 27, .val = 27, .flags = RATE_IN_36XX },
 263         { .div = 28, .val = 28, .flags = RATE_IN_36XX },
 264         { .div = 29, .val = 29, .flags = RATE_IN_36XX },
 265         { .div = 30, .val = 30, .flags = RATE_IN_36XX },
 266         { .div = 31, .val = 31, .flags = RATE_IN_36XX },
 267         { .div = 32, .val = 32, .flags = RATE_IN_36XX },
 268         { .div = 0 }
 269 };
 270
 271 /* DPLL1 */
 272 /* MPU clock source */
 273 /* Type: DPLL */
 274 static struct dpll_data dpll1_dd = {
 275         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 276         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 277         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 278         .clk_bypass     = &dpll1_fck,
 279         .clk_ref        = &sys_ck,
 280         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 281         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 282         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 283         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 284         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 285         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 286         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 287         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 288         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 289         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 290         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 291         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 292         .min_divider    = 1,
 293         .max_divider    = OMAP3_MAX_DPLL_DIV,
 294         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 295 };
 296
 297 static struct clk dpll1_ck = {
 298         .name           = "dpll1_ck",
 299         .ops            = &clkops_null,
 300         .parent         = &sys_ck,
 301         .dpll_data      = &dpll1_dd,
 302         .round_rate     = &omap2_dpll_round_rate,
 303         .set_rate       = &omap3_noncore_dpll_set_rate,
 304         .clkdm_name     = "dpll1_clkdm",
 305         .recalc         = &omap3_dpll_recalc,
 306 };
 307
 308 /*
 309  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 310  * DPLL isn't bypassed.
 311  */
 312 static struct clk dpll1_x2_ck = {
 313         .name           = "dpll1_x2_ck",
 314         .ops            = &clkops_null,
 315         .parent         = &dpll1_ck,
 316         .clkdm_name     = "dpll1_clkdm",
 317         .recalc         = &omap3_clkoutx2_recalc,
 318 };
 319
 320 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 321 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 322         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 323         { .parent = NULL }
 324 };
 325
 326 /*
 327  * Does not exist in the TRM - needed to separate the M2 divider from
 328  * bypass selection in mpu_ck
 329  */
 330 static struct clk dpll1_x2m2_ck = {
 331         .name           = "dpll1_x2m2_ck",
 332         .ops            = &clkops_null,
 333         .parent         = &dpll1_x2_ck,
 334         .init           = &omap2_init_clksel_parent,
 335         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 336         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 337         .clksel         = div16_dpll1_x2m2_clksel,
 338         .clkdm_name     = "dpll1_clkdm",
 339         .recalc         = &omap2_clksel_recalc,
 340 };
 341
 342 /* DPLL2 */
 343 /* IVA2 clock source */
 344 /* Type: DPLL */
 345
 346 static struct dpll_data dpll2_dd = {
 347         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 348         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 349         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 350         .clk_bypass     = &dpll2_fck,
 351         .clk_ref        = &sys_ck,
 352         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 353         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 354         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 355         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 356                                 (1 << DPLL_LOW_POWER_BYPASS),
 357         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 358         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 359         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 360         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 361         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 362         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 363         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 364         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 365         .min_divider    = 1,
 366         .max_divider    = OMAP3_MAX_DPLL_DIV,
 367         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 368 };
 369
 370 static struct clk dpll2_ck = {
 371         .name           = "dpll2_ck",
 372         .ops            = &clkops_omap3_noncore_dpll_ops,
 373         .parent         = &sys_ck,
 374         .dpll_data      = &dpll2_dd,
 375         .round_rate     = &omap2_dpll_round_rate,
 376         .set_rate       = &omap3_noncore_dpll_set_rate,
 377         .clkdm_name     = "dpll2_clkdm",
 378         .recalc         = &omap3_dpll_recalc,
 379 };
 380
 381 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 382         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 383         { .parent = NULL }
 384 };
 385
 386 /*
 387  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 388  * or CLKOUTX2. CLKOUT seems most plausible.
 389  */
 390 static struct clk dpll2_m2_ck = {
 391         .name           = "dpll2_m2_ck",
 392         .ops            = &clkops_null,
 393         .parent         = &dpll2_ck,
 394         .init           = &omap2_init_clksel_parent,
 395         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 396                                           OMAP3430_CM_CLKSEL2_PLL),
 397         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 398         .clksel         = div16_dpll2_m2x2_clksel,
 399         .clkdm_name     = "dpll2_clkdm",
 400         .recalc         = &omap2_clksel_recalc,
 401 };
 402
 403 /*
 404  * DPLL3
 405  * Source clock for all interfaces and for some device fclks
 406  * REVISIT: Also supports fast relock bypass - not included below
 407  */
 408 static struct dpll_data dpll3_dd = {
 409         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 410         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 411         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 412         .clk_bypass     = &sys_ck,
 413         .clk_ref        = &sys_ck,
 414         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 415         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 417         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 418         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 419         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 420         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 421         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 422         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 423         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 424         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 425         .min_divider    = 1,
 426         .max_divider    = OMAP3_MAX_DPLL_DIV,
 427         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 428 };
 429
 430 static struct clk dpll3_ck = {
 431         .name           = "dpll3_ck",
 432         .ops            = &clkops_null,
 433         .parent         = &sys_ck,
 434         .dpll_data      = &dpll3_dd,
 435         .round_rate     = &omap2_dpll_round_rate,
 436         .clkdm_name     = "dpll3_clkdm",
 437         .recalc         = &omap3_dpll_recalc,
 438 };
 439
 440 /*
 441  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 442  * DPLL isn't bypassed
 443  */
 444 static struct clk dpll3_x2_ck = {
 445         .name           = "dpll3_x2_ck",
 446         .ops            = &clkops_null,
 447         .parent         = &dpll3_ck,
 448         .clkdm_name     = "dpll3_clkdm",
 449         .recalc         = &omap3_clkoutx2_recalc,
 450 };
 451
 452 static const struct clksel_rate div31_dpll3_rates[] = {
 453         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 454         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 455         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 456         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 457         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 458         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 459         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 460         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 461         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 462         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 463         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 464         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 465         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 466         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 467         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 468         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 469         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 470         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 471         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 472         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 473         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 474         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 475         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 476         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 477         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 478         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 479         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 480         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 481         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 482         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 483         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 484         { .div = 0 },
 485 };
 486
 487 static const struct clksel div31_dpll3m2_clksel[] = {
 488         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 489         { .parent = NULL }
 490 };
 491
 492 /* DPLL3 output M2 - primary control point for CORE speed */
 493 static struct clk dpll3_m2_ck = {
 494         .name           = "dpll3_m2_ck",
 495         .ops            = &clkops_null,
 496         .parent         = &dpll3_ck,
 497         .init           = &omap2_init_clksel_parent,
 498         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 499         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 500         .clksel         = div31_dpll3m2_clksel,
 501         .clkdm_name     = "dpll3_clkdm",
 502         .round_rate     = &omap2_clksel_round_rate,
 503         .set_rate       = &omap3_core_dpll_m2_set_rate,
 504         .recalc         = &omap2_clksel_recalc,
 505 };
 506
 507 static struct clk core_ck = {
 508         .name           = "core_ck",
 509         .ops            = &clkops_null,
 510         .parent         = &dpll3_m2_ck,
 511         .recalc         = &followparent_recalc,
 512 };
 513
 514 static struct clk dpll3_m2x2_ck = {
 515         .name           = "dpll3_m2x2_ck",
 516         .ops            = &clkops_null,
 517         .parent         = &dpll3_m2_ck,
 518         .clkdm_name     = "dpll3_clkdm",
 519         .recalc         = &omap3_clkoutx2_recalc,
 520 };
 521
 522 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 523 static const struct clksel div16_dpll3_clksel[] = {
 524         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 525         { .parent = NULL }
 526 };
 527
 528 /* This virtual clock is the source for dpll3_m3x2_ck */
 529 static struct clk dpll3_m3_ck = {
 530         .name           = "dpll3_m3_ck",
 531         .ops            = &clkops_null,
 532         .parent         = &dpll3_ck,
 533         .init           = &omap2_init_clksel_parent,
 534         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 535         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 536         .clksel         = div16_dpll3_clksel,
 537         .clkdm_name     = "dpll3_clkdm",
 538         .recalc         = &omap2_clksel_recalc,
 539 };
 540
 541 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 542 static struct clk dpll3_m3x2_ck = {
 543         .name           = "dpll3_m3x2_ck",
 544         .ops            = &clkops_omap2_dflt_wait,
 545         .parent         = &dpll3_m3_ck,
 546         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 548         .flags          = INVERT_ENABLE,
 549         .clkdm_name     = "dpll3_clkdm",
 550         .recalc         = &omap3_clkoutx2_recalc,
 551 };
 552
 553 static struct clk emu_core_alwon_ck = {
 554         .name           = "emu_core_alwon_ck",
 555         .ops            = &clkops_null,
 556         .parent         = &dpll3_m3x2_ck,
 557         .clkdm_name     = "dpll3_clkdm",
 558         .recalc         = &followparent_recalc,
 559 };
 560
 561 /* DPLL4 */
 562 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563 /* Type: DPLL */
 564 static struct dpll_data dpll4_dd;
 565 static struct dpll_data dpll4_dd_34xx __initdata = {
 566         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 567         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 568         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 569         .clk_bypass     = &sys_ck,
 570         .clk_ref        = &sys_ck,
 571         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 572         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 573         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 574         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 575         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 576         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 577         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 578         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 579         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 580         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 581         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 582         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 583         .min_divider    = 1,
 584         .max_divider    = OMAP3_MAX_DPLL_DIV,
 585         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 586 };
 587
 588 static struct dpll_data dpll4_dd_3630 __initdata = {
 589         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 590         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 591         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 592         .clk_bypass     = &sys_ck,
 593         .clk_ref        = &sys_ck,
 594         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 595         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 596         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 597         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 598         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 599         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 600         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 601         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 602         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 603         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 604         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 605         .min_divider    = 1,
 606         .max_divider    = OMAP3_MAX_DPLL_DIV,
 607         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
 608         .flags          = DPLL_J_TYPE
 609 };
 610
 611 static struct clk dpll4_ck = {
 612         .name           = "dpll4_ck",
 613         .ops            = &clkops_omap3_noncore_dpll_ops,
 614         .parent         = &sys_ck,
 615         .dpll_data      = &dpll4_dd,
 616         .round_rate     = &omap2_dpll_round_rate,
 617         .set_rate       = &omap3_dpll4_set_rate,
 618         .clkdm_name     = "dpll4_clkdm",
 619         .recalc         = &omap3_dpll_recalc,
 620 };
 621
 622 /*
 623  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 624  * DPLL isn't bypassed --
 625  * XXX does this serve any downstream clocks?
 626  */
 627 static struct clk dpll4_x2_ck = {
 628         .name           = "dpll4_x2_ck",
 629         .ops            = &clkops_null,
 630         .parent         = &dpll4_ck,
 631         .clkdm_name     = "dpll4_clkdm",
 632         .recalc         = &omap3_clkoutx2_recalc,
 633 };
 634
 635 static const struct clksel div16_dpll4_clksel[] = {
 636         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 637         { .parent = NULL }
 638 };
 639
 640 static const struct clksel div32_dpll4_clksel[] = {
 641         { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
 642         { .parent = NULL }
 643 };
 644
 645 /* This virtual clock is the source for dpll4_m2x2_ck */
 646 static struct clk dpll4_m2_ck;
 647
 648 static struct clk dpll4_m2_ck_34xx __initdata = {
 649         .name           = "dpll4_m2_ck",
 650         .ops            = &clkops_null,
 651         .parent         = &dpll4_ck,
 652         .init           = &omap2_init_clksel_parent,
 653         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 654         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 655         .clksel         = div16_dpll4_clksel,
 656         .clkdm_name     = "dpll4_clkdm",
 657         .recalc         = &omap2_clksel_recalc,
 658 };
 659
 660 static struct clk dpll4_m2_ck_3630 __initdata  = {
 661         .name           = "dpll4_m2_ck",
 662         .ops            = &clkops_null,
 663         .parent         = &dpll4_ck,
 664         .init           = &omap2_init_clksel_parent,
 665         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 666         .clksel_mask    = OMAP3630_DIV_96M_MASK,
 667         .clksel         = div32_dpll4_clksel,
 668         .clkdm_name     = "dpll4_clkdm",
 669         .recalc         = &omap2_clksel_recalc,
 670 };
 671
 672 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 673 static struct clk dpll4_m2x2_ck = {
 674         .name           = "dpll4_m2x2_ck",
 675         .ops            = &clkops_omap2_dflt_wait,
 676         .parent         = &dpll4_m2_ck,
 677         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 678         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 679         .flags          = INVERT_ENABLE,
 680         .clkdm_name     = "dpll4_clkdm",
 681         .recalc         = &omap3_clkoutx2_recalc,
 682 };
 683
 684 /*
 685  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 686  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 687  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 688  * CM_96K_(F)CLK.
 689  */
 690
 691 /* Adding 192MHz Clock node needed by SGX */
 692 static struct clk omap_192m_alwon_fck = {
 693         .name           = "omap_192m_alwon_fck",
 694         .ops            = &clkops_null,
 695         .parent         = &dpll4_m2x2_ck,
 696         .recalc         = &followparent_recalc,
 697 };
 698
 699 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 700         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
 701         { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
 702         { .div = 0 }
 703 };
 704
 705 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 706         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 707         { .parent = NULL }
 708 };
 709
 710 static const struct clksel_rate omap_96m_dpll_rates[] = {
 711         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 712         { .div = 0 }
 713 };
 714
 715 static const struct clksel_rate omap_96m_sys_rates[] = {
 716         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 717         { .div = 0 }
 718 };
 719
 720 static struct clk omap_96m_alwon_fck = {
 721         .name           = "omap_96m_alwon_fck",
 722         .ops            = &clkops_null,
 723         .parent         = &dpll4_m2x2_ck,
 724         .recalc         = &followparent_recalc,
 725 };
 726
 727 static struct clk omap_96m_alwon_fck_3630 = {
 728         .name           = "omap_96m_alwon_fck",
 729         .parent         = &omap_192m_alwon_fck,
 730         .init           = &omap2_init_clksel_parent,
 731         .ops            = &clkops_null,
 732         .recalc         = &omap2_clksel_recalc,
 733         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 734         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
 735         .clksel         = omap_96m_alwon_fck_clksel
 736 };
 737
 738 static struct clk cm_96m_fck = {
 739         .name           = "cm_96m_fck",
 740         .ops            = &clkops_null,
 741         .parent         = &omap_96m_alwon_fck,
 742         .recalc         = &followparent_recalc,
 743 };
 744
 745 static const struct clksel omap_96m_fck_clksel[] = {
 746         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 747         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 748         { .parent = NULL }
 749 };
 750
 751 static struct clk omap_96m_fck = {
 752         .name           = "omap_96m_fck",
 753         .ops            = &clkops_null,
 754         .parent         = &sys_ck,
 755         .init           = &omap2_init_clksel_parent,
 756         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 757         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 758         .clksel         = omap_96m_fck_clksel,
 759         .recalc         = &omap2_clksel_recalc,
 760 };
 761
 762 /* This virtual clock is the source for dpll4_m3x2_ck */
 763 static struct clk dpll4_m3_ck;
 764
 765 static struct clk dpll4_m3_ck_34xx __initdata = {
 766         .name           = "dpll4_m3_ck",
 767         .ops            = &clkops_null,
 768         .parent         = &dpll4_ck,
 769         .init           = &omap2_init_clksel_parent,
 770         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 771         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 772         .clksel         = div16_dpll4_clksel,
 773         .clkdm_name     = "dpll4_clkdm",
 774         .recalc         = &omap2_clksel_recalc,
 775 };
 776
 777 static struct clk dpll4_m3_ck_3630 __initdata = {
 778         .name           = "dpll4_m3_ck",
 779         .ops            = &clkops_null,
 780         .parent         = &dpll4_ck,
 781         .init           = &omap2_init_clksel_parent,
 782         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 783         .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
 784         .clksel         = div32_dpll4_clksel,
 785         .clkdm_name     = "dpll4_clkdm",
 786         .recalc         = &omap2_clksel_recalc,
 787 };
 788
 789 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 790 static struct clk dpll4_m3x2_ck = {
 791         .name           = "dpll4_m3x2_ck",
 792         .ops            = &clkops_omap2_dflt_wait,
 793         .parent         = &dpll4_m3_ck,
 794         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 795         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 796         .flags          = INVERT_ENABLE,
 797         .clkdm_name     = "dpll4_clkdm",
 798         .recalc         = &omap3_clkoutx2_recalc,
 799 };
 800
 801 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 802         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 803         { .div = 0 }
 804 };
 805
 806 static const struct clksel_rate omap_54m_alt_rates[] = {
 807         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 808         { .div = 0 }
 809 };
 810
 811 static const struct clksel omap_54m_clksel[] = {
 812         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 813         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 814         { .parent = NULL }
 815 };
 816
 817 static struct clk omap_54m_fck = {
 818         .name           = "omap_54m_fck",
 819         .ops            = &clkops_null,
 820         .init           = &omap2_init_clksel_parent,
 821         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 822         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 823         .clksel         = omap_54m_clksel,
 824         .recalc         = &omap2_clksel_recalc,
 825 };
 826
 827 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 828         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 829         { .div = 0 }
 830 };
 831
 832 static const struct clksel_rate omap_48m_alt_rates[] = {
 833         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 834         { .div = 0 }
 835 };
 836
 837 static const struct clksel omap_48m_clksel[] = {
 838         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 839         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 840         { .parent = NULL }
 841 };
 842
 843 static struct clk omap_48m_fck = {
 844         .name           = "omap_48m_fck",
 845         .ops            = &clkops_null,
 846         .init           = &omap2_init_clksel_parent,
 847         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 848         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 849         .clksel         = omap_48m_clksel,
 850         .recalc         = &omap2_clksel_recalc,
 851 };
 852
 853 static struct clk omap_12m_fck = {
 854         .name           = "omap_12m_fck",
 855         .ops            = &clkops_null,
 856         .parent         = &omap_48m_fck,
 857         .fixed_div      = 4,
 858         .recalc         = &omap_fixed_divisor_recalc,
 859 };
 860
 861 /* This virstual clock is the source for dpll4_m4x2_ck */
 862 static struct clk dpll4_m4_ck;
 863
 864 static struct clk dpll4_m4_ck_34xx __initdata = {
 865         .name           = "dpll4_m4_ck",
 866         .ops            = &clkops_null,
 867         .parent         = &dpll4_ck,
 868         .init           = &omap2_init_clksel_parent,
 869         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 870         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 871         .clksel         = div16_dpll4_clksel,
 872         .clkdm_name     = "dpll4_clkdm",
 873         .recalc         = &omap2_clksel_recalc,
 874         .set_rate       = &omap2_clksel_set_rate,
 875         .round_rate     = &omap2_clksel_round_rate,
 876 };
 877
 878 static struct clk dpll4_m4_ck_3630 __initdata = {
 879         .name           = "dpll4_m4_ck",
 880         .ops            = &clkops_null,
 881         .parent         = &dpll4_ck,
 882         .init           = &omap2_init_clksel_parent,
 883         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 884         .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
 885         .clksel         = div32_dpll4_clksel,
 886         .clkdm_name     = "dpll4_clkdm",
 887         .recalc         = &omap2_clksel_recalc,
 888         .set_rate       = &omap2_clksel_set_rate,
 889         .round_rate     = &omap2_clksel_round_rate,
 890 };
 891
 892 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 893 static struct clk dpll4_m4x2_ck = {
 894         .name           = "dpll4_m4x2_ck",
 895         .ops            = &clkops_omap2_dflt_wait,
 896         .parent         = &dpll4_m4_ck,
 897         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 898         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 899         .flags          = INVERT_ENABLE,
 900         .clkdm_name     = "dpll4_clkdm",
 901         .recalc         = &omap3_clkoutx2_recalc,
 902 };
 903
 904 /* This virtual clock is the source for dpll4_m5x2_ck */
 905 static struct clk dpll4_m5_ck;
 906
 907 static struct clk dpll4_m5_ck_34xx __initdata = {
 908         .name           = "dpll4_m5_ck",
 909         .ops            = &clkops_null,
 910         .parent         = &dpll4_ck,
 911         .init           = &omap2_init_clksel_parent,
 912         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 913         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 914         .clksel         = div16_dpll4_clksel,
 915         .clkdm_name     = "dpll4_clkdm",
 916         .set_rate       = &omap2_clksel_set_rate,
 917         .round_rate     = &omap2_clksel_round_rate,
 918         .recalc         = &omap2_clksel_recalc,
 919 };
 920
 921 static struct clk dpll4_m5_ck_3630 __initdata = {
 922         .name           = "dpll4_m5_ck",
 923         .ops            = &clkops_null,
 924         .parent         = &dpll4_ck,
 925         .init           = &omap2_init_clksel_parent,
 926         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 927         .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
 928         .clksel         = div32_dpll4_clksel,
 929         .clkdm_name     = "dpll4_clkdm",
 930         .recalc         = &omap2_clksel_recalc,
 931 };
 932
 933 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 934 static struct clk dpll4_m5x2_ck = {
 935         .name           = "dpll4_m5x2_ck",
 936         .ops            = &clkops_omap2_dflt_wait,
 937         .parent         = &dpll4_m5_ck,
 938         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 939         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 940         .flags          = INVERT_ENABLE,
 941         .clkdm_name     = "dpll4_clkdm",
 942         .recalc         = &omap3_clkoutx2_recalc,
 943 };
 944
 945 /* This virtual clock is the source for dpll4_m6x2_ck */
 946 static struct clk dpll4_m6_ck;
 947
 948 static struct clk dpll4_m6_ck_34xx __initdata = {
 949         .name           = "dpll4_m6_ck",
 950         .ops            = &clkops_null,
 951         .parent         = &dpll4_ck,
 952         .init           = &omap2_init_clksel_parent,
 953         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 954         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 955         .clksel         = div16_dpll4_clksel,
 956         .clkdm_name     = "dpll4_clkdm",
 957         .recalc         = &omap2_clksel_recalc,
 958 };
 959
 960 static struct clk dpll4_m6_ck_3630 __initdata = {
 961         .name           = "dpll4_m6_ck",
 962         .ops            = &clkops_null,
 963         .parent         = &dpll4_ck,
 964         .init           = &omap2_init_clksel_parent,
 965         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 966         .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
 967         .clksel         = div32_dpll4_clksel,
 968         .clkdm_name     = "dpll4_clkdm",
 969         .recalc         = &omap2_clksel_recalc,
 970 };
 971
 972 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 973 static struct clk dpll4_m6x2_ck = {
 974         .name           = "dpll4_m6x2_ck",
 975         .ops            = &clkops_omap2_dflt_wait,
 976         .parent         = &dpll4_m6_ck,
 977         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 978         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 979         .flags          = INVERT_ENABLE,
 980         .clkdm_name     = "dpll4_clkdm",
 981         .recalc         = &omap3_clkoutx2_recalc,
 982 };
 983
 984 static struct clk emu_per_alwon_ck = {
 985         .name           = "emu_per_alwon_ck",
 986         .ops            = &clkops_null,
 987         .parent         = &dpll4_m6x2_ck,
 988         .clkdm_name     = "dpll4_clkdm",
 989         .recalc         = &followparent_recalc,
 990 };
 991
 992 /* DPLL5 */
 993 /* Supplies 120MHz clock, USIM source clock */
 994 /* Type: DPLL */
 995 /* 3430ES2 only */
 996 static struct dpll_data dpll5_dd = {
 997         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 998         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 999         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1000         .clk_bypass     = &sys_ck,
1001         .clk_ref        = &sys_ck,
1002         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1003         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1004         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1005         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1006         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1007         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1008         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1009         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1010         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1011         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1012         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1013         .max_multiplier = OMAP3_MAX_DPLL_MULT,
1014         .min_divider    = 1,
1015         .max_divider    = OMAP3_MAX_DPLL_DIV,
1016         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
1017 };
1018
1019 static struct clk dpll5_ck = {
1020         .name           = "dpll5_ck",
1021         .ops            = &clkops_omap3_noncore_dpll_ops,
1022         .parent         = &sys_ck,
1023         .dpll_data      = &dpll5_dd,
1024         .round_rate     = &omap2_dpll_round_rate,
1025         .set_rate       = &omap3_noncore_dpll_set_rate,
1026         .clkdm_name     = "dpll5_clkdm",
1027         .recalc         = &omap3_dpll_recalc,
1028 };
1029
1030 static const struct clksel div16_dpll5_clksel[] = {
1031         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1032         { .parent = NULL }
1033 };
1034
1035 static struct clk dpll5_m2_ck = {
1036         .name           = "dpll5_m2_ck",
1037         .ops            = &clkops_null,
1038         .parent         = &dpll5_ck,
1039         .init           = &omap2_init_clksel_parent,
1040         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1041         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1042         .clksel         = div16_dpll5_clksel,
1043         .clkdm_name     = "dpll5_clkdm",
1044         .recalc         = &omap2_clksel_recalc,
1045 };
1046
1047 /* CM EXTERNAL CLOCK OUTPUTS */
1048
1049 static const struct clksel_rate clkout2_src_core_rates[] = {
1050         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1051         { .div = 0 }
1052 };
1053
1054 static const struct clksel_rate clkout2_src_sys_rates[] = {
1055         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1056         { .div = 0 }
1057 };
1058
1059 static const struct clksel_rate clkout2_src_96m_rates[] = {
1060         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1061         { .div = 0 }
1062 };
1063
1064 static const struct clksel_rate clkout2_src_54m_rates[] = {
1065         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1066         { .div = 0 }
1067 };
1068
1069 static const struct clksel clkout2_src_clksel[] = {
1070         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1071         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1072         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1073         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1074         { .parent = NULL }
1075 };
1076
1077 static struct clk clkout2_src_ck = {
1078         .name           = "clkout2_src_ck",
1079         .ops            = &clkops_omap2_dflt,
1080         .init           = &omap2_init_clksel_parent,
1081         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1082         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1083         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1084         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1085         .clksel         = clkout2_src_clksel,
1086         .clkdm_name     = "core_clkdm",
1087         .recalc         = &omap2_clksel_recalc,
1088 };
1089
1090 static const struct clksel_rate sys_clkout2_rates[] = {
1091         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1092         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1093         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1094         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1095         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1096         { .div = 0 },
1097 };
1098
1099 static const struct clksel sys_clkout2_clksel[] = {
1100         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1101         { .parent = NULL },
1102 };
1103
1104 static struct clk sys_clkout2 = {
1105         .name           = "sys_clkout2",
1106         .ops            = &clkops_null,
1107         .init           = &omap2_init_clksel_parent,
1108         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1109         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1110         .clksel         = sys_clkout2_clksel,
1111         .recalc         = &omap2_clksel_recalc,
1112 };
1113
1114 /* CM OUTPUT CLOCKS */
1115
1116 static struct clk corex2_fck = {
1117         .name           = "corex2_fck",
1118         .ops            = &clkops_null,
1119         .parent         = &dpll3_m2x2_ck,
1120         .recalc         = &followparent_recalc,
1121 };
1122
1123 /* DPLL power domain clock controls */
1124
1125 static const struct clksel_rate div4_rates[] = {
1126         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1127         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1128         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1129         { .div = 0 }
1130 };
1131
1132 static const struct clksel div4_core_clksel[] = {
1133         { .parent = &core_ck, .rates = div4_rates },
1134         { .parent = NULL }
1135 };
1136
1137 /*
1138  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1139  * may be inconsistent here?
1140  */
1141 static struct clk dpll1_fck = {
1142         .name           = "dpll1_fck",
1143         .ops            = &clkops_null,
1144         .parent         = &core_ck,
1145         .init           = &omap2_init_clksel_parent,
1146         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1147         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1148         .clksel         = div4_core_clksel,
1149         .recalc         = &omap2_clksel_recalc,
1150 };
1151
1152 static struct clk mpu_ck = {
1153         .name           = "mpu_ck",
1154         .ops            = &clkops_null,
1155         .parent         = &dpll1_x2m2_ck,
1156         .clkdm_name     = "mpu_clkdm",
1157         .recalc         = &followparent_recalc,
1158 };
1159
1160 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1161 static const struct clksel_rate arm_fck_rates[] = {
1162         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1163         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1164         { .div = 0 },
1165 };
1166
1167 static const struct clksel arm_fck_clksel[] = {
1168         { .parent = &mpu_ck, .rates = arm_fck_rates },
1169         { .parent = NULL }
1170 };
1171
1172 static struct clk arm_fck = {
1173         .name           = "arm_fck",
1174         .ops            = &clkops_null,
1175         .parent         = &mpu_ck,
1176         .init           = &omap2_init_clksel_parent,
1177         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1178         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1179         .clksel         = arm_fck_clksel,
1180         .clkdm_name     = "mpu_clkdm",
1181         .recalc         = &omap2_clksel_recalc,
1182 };
1183
1184 /* XXX What about neon_clkdm ? */
1185
1186 /*
1187  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1188  * although it is referenced - so this is a guess
1189  */
1190 static struct clk emu_mpu_alwon_ck = {
1191         .name           = "emu_mpu_alwon_ck",
1192         .ops            = &clkops_null,
1193         .parent         = &mpu_ck,
1194         .recalc         = &followparent_recalc,
1195 };
1196
1197 static struct clk dpll2_fck = {
1198         .name           = "dpll2_fck",
1199         .ops            = &clkops_null,
1200         .parent         = &core_ck,
1201         .init           = &omap2_init_clksel_parent,
1202         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1203         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1204         .clksel         = div4_core_clksel,
1205         .recalc         = &omap2_clksel_recalc,
1206 };
1207
1208 static struct clk iva2_ck = {
1209         .name           = "iva2_ck",
1210         .ops            = &clkops_omap2_dflt_wait,
1211         .parent         = &dpll2_m2_ck,
1212         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1213         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1214         .clkdm_name     = "iva2_clkdm",
1215         .recalc         = &followparent_recalc,
1216 };
1217
1218 /* Common interface clocks */
1219
1220 static const struct clksel div2_core_clksel[] = {
1221         { .parent = &core_ck, .rates = div2_rates },
1222         { .parent = NULL }
1223 };
1224
1225 static struct clk l3_ick = {
1226         .name           = "l3_ick",
1227         .ops            = &clkops_null,
1228         .parent         = &core_ck,
1229         .init           = &omap2_init_clksel_parent,
1230         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1231         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1232         .clksel         = div2_core_clksel,
1233         .clkdm_name     = "core_l3_clkdm",
1234         .recalc         = &omap2_clksel_recalc,
1235 };
1236
1237 static const struct clksel div2_l3_clksel[] = {
1238         { .parent = &l3_ick, .rates = div2_rates },
1239         { .parent = NULL }
1240 };
1241
1242 static struct clk l4_ick = {
1243         .name           = "l4_ick",
1244         .ops            = &clkops_null,
1245         .parent         = &l3_ick,
1246         .init           = &omap2_init_clksel_parent,
1247         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1248         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1249         .clksel         = div2_l3_clksel,
1250         .clkdm_name     = "core_l4_clkdm",
1251         .recalc         = &omap2_clksel_recalc,
1252
1253 };
1254
1255 static const struct clksel div2_l4_clksel[] = {
1256         { .parent = &l4_ick, .rates = div2_rates },
1257         { .parent = NULL }
1258 };
1259
1260 static struct clk rm_ick = {
1261         .name           = "rm_ick",
1262         .ops            = &clkops_null,
1263         .parent         = &l4_ick,
1264         .init           = &omap2_init_clksel_parent,
1265         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1266         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1267         .clksel         = div2_l4_clksel,
1268         .recalc         = &omap2_clksel_recalc,
1269 };
1270
1271 /* GFX power domain */
1272
1273 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1274
1275 static const struct clksel gfx_l3_clksel[] = {
1276         { .parent = &l3_ick, .rates = gfx_l3_rates },
1277         { .parent = NULL }
1278 };
1279
1280 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1281 static struct clk gfx_l3_ck = {
1282         .name           = "gfx_l3_ck",
1283         .ops            = &clkops_omap2_dflt_wait,
1284         .parent         = &l3_ick,
1285         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1286         .enable_bit     = OMAP_EN_GFX_SHIFT,
1287         .recalc         = &followparent_recalc,
1288 };
1289
1290 static struct clk gfx_l3_fck = {
1291         .name           = "gfx_l3_fck",
1292         .ops            = &clkops_null,
1293         .parent         = &gfx_l3_ck,
1294         .init           = &omap2_init_clksel_parent,
1295         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1296         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1297         .clksel         = gfx_l3_clksel,
1298         .clkdm_name     = "gfx_3430es1_clkdm",
1299         .recalc         = &omap2_clksel_recalc,
1300 };
1301
1302 static struct clk gfx_l3_ick = {
1303         .name           = "gfx_l3_ick",
1304         .ops            = &clkops_null,
1305         .parent         = &gfx_l3_ck,
1306         .clkdm_name     = "gfx_3430es1_clkdm",
1307         .recalc         = &followparent_recalc,
1308 };
1309
1310 static struct clk gfx_cg1_ck = {
1311         .name           = "gfx_cg1_ck",
1312         .ops            = &clkops_omap2_dflt_wait,
1313         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1314         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1315         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1316         .clkdm_name     = "gfx_3430es1_clkdm",
1317         .recalc         = &followparent_recalc,
1318 };
1319
1320 static struct clk gfx_cg2_ck = {
1321         .name           = "gfx_cg2_ck",
1322         .ops            = &clkops_omap2_dflt_wait,
1323         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1324         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1325         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1326         .clkdm_name     = "gfx_3430es1_clkdm",
1327         .recalc         = &followparent_recalc,
1328 };
1329
1330 /* SGX power domain - 3430ES2 only */
1331
1332 static const struct clksel_rate sgx_core_rates[] = {
1333         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1334         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1335         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1336         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1337         { .div = 0 },
1338 };
1339
1340 static const struct clksel_rate sgx_192m_rates[] = {
1341         { .div = 1,  .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
1342         { .div = 0 },
1343 };
1344
1345 static const struct clksel_rate sgx_corex2_rates[] = {
1346         { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
1347         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1348         { .div = 0 },
1349 };
1350
1351 static const struct clksel_rate sgx_96m_rates[] = {
1352         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1353         { .div = 0 },
1354 };
1355
1356 static const struct clksel sgx_clksel[] = {
1357         { .parent = &core_ck,    .rates = sgx_core_rates },
1358         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1359         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1360         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1361         { .parent = NULL }
1362 };
1363
1364 static struct clk sgx_fck = {
1365         .name           = "sgx_fck",
1366         .ops            = &clkops_omap2_dflt_wait,
1367         .init           = &omap2_init_clksel_parent,
1368         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1369         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1370         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1371         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1372         .clksel         = sgx_clksel,
1373         .clkdm_name     = "sgx_clkdm",
1374         .recalc         = &omap2_clksel_recalc,
1375         .set_rate       = &omap2_clksel_set_rate,
1376         .round_rate     = &omap2_clksel_round_rate
1377 };
1378
1379 static struct clk sgx_ick = {
1380         .name           = "sgx_ick",
1381         .ops            = &clkops_omap2_dflt_wait,
1382         .parent         = &l3_ick,
1383         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1384         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1385         .clkdm_name     = "sgx_clkdm",
1386         .recalc         = &followparent_recalc,
1387 };
1388
1389 /* CORE power domain */
1390
1391 static struct clk d2d_26m_fck = {
1392         .name           = "d2d_26m_fck",
1393         .ops            = &clkops_omap2_dflt_wait,
1394         .parent         = &sys_ck,
1395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1396         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1397         .clkdm_name     = "d2d_clkdm",
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk modem_fck = {
1402         .name           = "modem_fck",
1403         .ops            = &clkops_omap2_dflt_wait,
1404         .parent         = &sys_ck,
1405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1407         .clkdm_name     = "d2d_clkdm",
1408         .recalc         = &followparent_recalc,
1409 };
1410
1411 static struct clk sad2d_ick = {
1412         .name           = "sad2d_ick",
1413         .ops            = &clkops_omap2_dflt_wait,
1414         .parent         = &l3_ick,
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1416         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1417         .clkdm_name     = "d2d_clkdm",
1418         .recalc         = &followparent_recalc,
1419 };
1420
1421 static struct clk mad2d_ick = {
1422         .name           = "mad2d_ick",
1423         .ops            = &clkops_omap2_dflt_wait,
1424         .parent         = &l3_ick,
1425         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1426         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1427         .clkdm_name     = "d2d_clkdm",
1428         .recalc         = &followparent_recalc,
1429 };
1430
1431 static const struct clksel omap343x_gpt_clksel[] = {
1432         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1433         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1434         { .parent = NULL}
1435 };
1436
1437 static struct clk gpt10_fck = {
1438         .name           = "gpt10_fck",
1439         .ops            = &clkops_omap2_dflt_wait,
1440         .parent         = &sys_ck,
1441         .init           = &omap2_init_clksel_parent,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1444         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1445         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1446         .clksel         = omap343x_gpt_clksel,
1447         .clkdm_name     = "core_l4_clkdm",
1448         .recalc         = &omap2_clksel_recalc,
1449 };
1450
1451 static struct clk gpt11_fck = {
1452         .name           = "gpt11_fck",
1453         .ops            = &clkops_omap2_dflt_wait,
1454         .parent         = &sys_ck,
1455         .init           = &omap2_init_clksel_parent,
1456         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1457         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1458         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1459         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1460         .clksel         = omap343x_gpt_clksel,
1461         .clkdm_name     = "core_l4_clkdm",
1462         .recalc         = &omap2_clksel_recalc,
1463 };
1464
1465 static struct clk cpefuse_fck = {
1466         .name           = "cpefuse_fck",
1467         .ops            = &clkops_omap2_dflt,
1468         .parent         = &sys_ck,
1469         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1470         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1471         .recalc         = &followparent_recalc,
1472 };
1473
1474 static struct clk ts_fck = {
1475         .name           = "ts_fck",
1476         .ops            = &clkops_omap2_dflt,
1477         .parent         = &omap_32k_fck,
1478         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1479         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1480         .recalc         = &followparent_recalc,
1481 };
1482
1483 static struct clk usbtll_fck = {
1484         .name           = "usbtll_fck",
1485         .ops            = &clkops_omap2_dflt,
1486         .parent         = &dpll5_m2_ck,
1487         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1488         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 /* CORE 96M FCLK-derived clocks */
1493
1494 static struct clk core_96m_fck = {
1495         .name           = "core_96m_fck",
1496         .ops            = &clkops_null,
1497         .parent         = &omap_96m_fck,
1498         .clkdm_name     = "core_l4_clkdm",
1499         .recalc         = &followparent_recalc,
1500 };
1501
1502 static struct clk mmchs3_fck = {
1503         .name           = "mmchs3_fck",
1504         .ops            = &clkops_omap2_dflt_wait,
1505         .parent         = &core_96m_fck,
1506         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1507         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1508         .clkdm_name     = "core_l4_clkdm",
1509         .recalc         = &followparent_recalc,
1510 };
1511
1512 static struct clk mmchs2_fck = {
1513         .name           = "mmchs2_fck",
1514         .ops            = &clkops_omap2_dflt_wait,
1515         .parent         = &core_96m_fck,
1516         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1518         .clkdm_name     = "core_l4_clkdm",
1519         .recalc         = &followparent_recalc,
1520 };
1521
1522 static struct clk mspro_fck = {
1523         .name           = "mspro_fck",
1524         .ops            = &clkops_omap2_dflt_wait,
1525         .parent         = &core_96m_fck,
1526         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1527         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1528         .clkdm_name     = "core_l4_clkdm",
1529         .recalc         = &followparent_recalc,
1530 };
1531
1532 static struct clk mmchs1_fck = {
1533         .name           = "mmchs1_fck",
1534         .ops            = &clkops_omap2_dflt_wait,
1535         .parent         = &core_96m_fck,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1538         .clkdm_name     = "core_l4_clkdm",
1539         .recalc         = &followparent_recalc,
1540 };
1541
1542 static struct clk i2c3_fck = {
1543         .name           = "i2c3_fck",
1544         .ops            = &clkops_omap2_dflt_wait,
1545         .parent         = &core_96m_fck,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1547         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1548         .clkdm_name     = "core_l4_clkdm",
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk i2c2_fck = {
1553         .name           = "i2c2_fck",
1554         .ops            = &clkops_omap2_dflt_wait,
1555         .parent         = &core_96m_fck,
1556         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1557         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1558         .clkdm_name     = "core_l4_clkdm",
1559         .recalc         = &followparent_recalc,
1560 };
1561
1562 static struct clk i2c1_fck = {
1563         .name           = "i2c1_fck",
1564         .ops            = &clkops_omap2_dflt_wait,
1565         .parent         = &core_96m_fck,
1566         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1567         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1568         .clkdm_name     = "core_l4_clkdm",
1569         .recalc         = &followparent_recalc,
1570 };
1571
1572 /*
1573  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1574  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1575  */
1576 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1577         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1578         { .div = 0 }
1579 };
1580
1581 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1582         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1583         { .div = 0 }
1584 };
1585
1586 static const struct clksel mcbsp_15_clksel[] = {
1587         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1588         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1589         { .parent = NULL }
1590 };
1591
1592 static struct clk mcbsp5_fck = {
1593         .name           = "mcbsp5_fck",
1594         .ops            = &clkops_omap2_dflt_wait,
1595         .init           = &omap2_init_clksel_parent,
1596         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1597         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1598         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1599         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1600         .clksel         = mcbsp_15_clksel,
1601         .clkdm_name     = "core_l4_clkdm",
1602         .recalc         = &omap2_clksel_recalc,
1603 };
1604
1605 static struct clk mcbsp1_fck = {
1606         .name           = "mcbsp1_fck",
1607         .ops            = &clkops_omap2_dflt_wait,
1608         .init           = &omap2_init_clksel_parent,
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1611         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1612         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1613         .clksel         = mcbsp_15_clksel,
1614         .clkdm_name     = "core_l4_clkdm",
1615         .recalc         = &omap2_clksel_recalc,
1616 };
1617
1618 /* CORE_48M_FCK-derived clocks */
1619
1620 static struct clk core_48m_fck = {
1621         .name           = "core_48m_fck",
1622         .ops            = &clkops_null,
1623         .parent         = &omap_48m_fck,
1624         .clkdm_name     = "core_l4_clkdm",
1625         .recalc         = &followparent_recalc,
1626 };
1627
1628 static struct clk mcspi4_fck = {
1629         .name           = "mcspi4_fck",
1630         .ops            = &clkops_omap2_dflt_wait,
1631         .parent         = &core_48m_fck,
1632         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk mcspi3_fck = {
1638         .name           = "mcspi3_fck",
1639         .ops            = &clkops_omap2_dflt_wait,
1640         .parent         = &core_48m_fck,
1641         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1642         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 static struct clk mcspi2_fck = {
1647         .name           = "mcspi2_fck",
1648         .ops            = &clkops_omap2_dflt_wait,
1649         .parent         = &core_48m_fck,
1650         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1651         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk mcspi1_fck = {
1656         .name           = "mcspi1_fck",
1657         .ops            = &clkops_omap2_dflt_wait,
1658         .parent         = &core_48m_fck,
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk uart2_fck = {
1665         .name           = "uart2_fck",
1666         .ops            = &clkops_omap2_dflt_wait,
1667         .parent         = &core_48m_fck,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1669         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1670         .clkdm_name     = "core_l4_clkdm",
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk uart1_fck = {
1675         .name           = "uart1_fck",
1676         .ops            = &clkops_omap2_dflt_wait,
1677         .parent         = &core_48m_fck,
1678         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1679         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1680         .clkdm_name     = "core_l4_clkdm",
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 static struct clk fshostusb_fck = {
1685         .name           = "fshostusb_fck",
1686         .ops            = &clkops_omap2_dflt_wait,
1687         .parent         = &core_48m_fck,
1688         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1689         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 /* CORE_12M_FCK based clocks */
1694
1695 static struct clk core_12m_fck = {
1696         .name           = "core_12m_fck",
1697         .ops            = &clkops_null,
1698         .parent         = &omap_12m_fck,
1699         .clkdm_name     = "core_l4_clkdm",
1700         .recalc         = &followparent_recalc,
1701 };
1702
1703 static struct clk hdq_fck = {
1704         .name           = "hdq_fck",
1705         .ops            = &clkops_omap2_dflt_wait,
1706         .parent         = &core_12m_fck,
1707         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1708         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 /* DPLL3-derived clock */
1713
1714 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1715         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1716         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1717         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1718         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1719         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1720         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1721         { .div = 0 }
1722 };
1723
1724 static const struct clksel ssi_ssr_clksel[] = {
1725         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1726         { .parent = NULL }
1727 };
1728
1729 static struct clk ssi_ssr_fck_3430es1 = {
1730         .name           = "ssi_ssr_fck",
1731         .ops            = &clkops_omap2_dflt,
1732         .init           = &omap2_init_clksel_parent,
1733         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1734         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1735         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1736         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1737         .clksel         = ssi_ssr_clksel,
1738         .clkdm_name     = "core_l4_clkdm",
1739         .recalc         = &omap2_clksel_recalc,
1740 };
1741
1742 static struct clk ssi_ssr_fck_3430es2 = {
1743         .name           = "ssi_ssr_fck",
1744         .ops            = &clkops_omap3430es2_ssi_wait,
1745         .init           = &omap2_init_clksel_parent,
1746         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1747         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1748         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1749         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1750         .clksel         = ssi_ssr_clksel,
1751         .clkdm_name     = "core_l4_clkdm",
1752         .recalc         = &omap2_clksel_recalc,
1753 };
1754
1755 static struct clk ssi_sst_fck_3430es1 = {
1756         .name           = "ssi_sst_fck",
1757         .ops            = &clkops_null,
1758         .parent         = &ssi_ssr_fck_3430es1,
1759         .fixed_div      = 2,
1760         .recalc         = &omap_fixed_divisor_recalc,
1761 };
1762
1763 static struct clk ssi_sst_fck_3430es2 = {
1764         .name           = "ssi_sst_fck",
1765         .ops            = &clkops_null,
1766         .parent         = &ssi_ssr_fck_3430es2,
1767         .fixed_div      = 2,
1768         .recalc         = &omap_fixed_divisor_recalc,
1769 };
1770
1771
1772
1773 /* CORE_L3_ICK based clocks */
1774
1775 /*
1776  * XXX must add clk_enable/clk_disable for these if standard code won't
1777  * handle it
1778  */
1779 static struct clk core_l3_ick = {
1780         .name           = "core_l3_ick",
1781         .ops            = &clkops_null,
1782         .parent         = &l3_ick,
1783         .clkdm_name     = "core_l3_clkdm",
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk hsotgusb_ick_3430es1 = {
1788         .name           = "hsotgusb_ick",
1789         .ops            = &clkops_omap2_dflt,
1790         .parent         = &core_l3_ick,
1791         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1792         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1793         .clkdm_name     = "core_l3_clkdm",
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk hsotgusb_ick_3430es2 = {
1798         .name           = "hsotgusb_ick",
1799         .ops            = &clkops_omap3430es2_hsotgusb_wait,
1800         .parent         = &core_l3_ick,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1803         .clkdm_name     = "core_l3_clkdm",
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 static struct clk sdrc_ick = {
1808         .name           = "sdrc_ick",
1809         .ops            = &clkops_omap2_dflt_wait,
1810         .parent         = &core_l3_ick,
1811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1812         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1813         .flags          = ENABLE_ON_INIT,
1814         .clkdm_name     = "core_l3_clkdm",
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk gpmc_fck = {
1819         .name           = "gpmc_fck",
1820         .ops            = &clkops_null,
1821         .parent         = &core_l3_ick,
1822         .flags          = ENABLE_ON_INIT, /* huh? */
1823         .clkdm_name     = "core_l3_clkdm",
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 /* SECURITY_L3_ICK based clocks */
1828
1829 static struct clk security_l3_ick = {
1830         .name           = "security_l3_ick",
1831         .ops            = &clkops_null,
1832         .parent         = &l3_ick,
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 static struct clk pka_ick = {
1837         .name           = "pka_ick",
1838         .ops            = &clkops_omap2_dflt_wait,
1839         .parent         = &security_l3_ick,
1840         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1841         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 /* CORE_L4_ICK based clocks */
1846
1847 static struct clk core_l4_ick = {
1848         .name           = "core_l4_ick",
1849         .ops            = &clkops_null,
1850         .parent         = &l4_ick,
1851         .clkdm_name     = "core_l4_clkdm",
1852         .recalc         = &followparent_recalc,
1853 };
1854
1855 static struct clk usbtll_ick = {
1856         .name           = "usbtll_ick",
1857         .ops            = &clkops_omap2_dflt_wait,
1858         .parent         = &core_l4_ick,
1859         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1860         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1861         .clkdm_name     = "core_l4_clkdm",
1862         .recalc         = &followparent_recalc,
1863 };
1864
1865 static struct clk mmchs3_ick = {
1866         .name           = "mmchs3_ick",
1867         .ops            = &clkops_omap2_dflt_wait,
1868         .parent         = &core_l4_ick,
1869         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1870         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1871         .clkdm_name     = "core_l4_clkdm",
1872         .recalc         = &followparent_recalc,
1873 };
1874
1875 /* Intersystem Communication Registers - chassis mode only */
1876 static struct clk icr_ick = {
1877         .name           = "icr_ick",
1878         .ops            = &clkops_omap2_dflt_wait,
1879         .parent         = &core_l4_ick,
1880         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1881         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1882         .clkdm_name     = "core_l4_clkdm",
1883         .recalc         = &followparent_recalc,
1884 };
1885
1886 static struct clk aes2_ick = {
1887         .name           = "aes2_ick",
1888         .ops            = &clkops_omap2_dflt_wait,
1889         .parent         = &core_l4_ick,
1890         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1891         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1892         .clkdm_name     = "core_l4_clkdm",
1893         .recalc         = &followparent_recalc,
1894 };
1895
1896 static struct clk sha12_ick = {
1897         .name           = "sha12_ick",
1898         .ops            = &clkops_omap2_dflt_wait,
1899         .parent         = &core_l4_ick,
1900         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1901         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1902         .clkdm_name     = "core_l4_clkdm",
1903         .recalc         = &followparent_recalc,
1904 };
1905
1906 static struct clk des2_ick = {
1907         .name           = "des2_ick",
1908         .ops            = &clkops_omap2_dflt_wait,
1909         .parent         = &core_l4_ick,
1910         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1911         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1912         .clkdm_name     = "core_l4_clkdm",
1913         .recalc         = &followparent_recalc,
1914 };
1915
1916 static struct clk mmchs2_ick = {
1917         .name           = "mmchs2_ick",
1918         .ops            = &clkops_omap2_dflt_wait,
1919         .parent         = &core_l4_ick,
1920         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1921         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1922         .clkdm_name     = "core_l4_clkdm",
1923         .recalc         = &followparent_recalc,
1924 };
1925
1926 static struct clk mmchs1_ick = {
1927         .name           = "mmchs1_ick",
1928         .ops            = &clkops_omap2_dflt_wait,
1929         .parent         = &core_l4_ick,
1930         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1931         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1932         .clkdm_name     = "core_l4_clkdm",
1933         .recalc         = &followparent_recalc,
1934 };
1935
1936 static struct clk mspro_ick = {
1937         .name           = "mspro_ick",
1938         .ops            = &clkops_omap2_dflt_wait,
1939         .parent         = &core_l4_ick,
1940         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1942         .clkdm_name     = "core_l4_clkdm",
1943         .recalc         = &followparent_recalc,
1944 };
1945
1946 static struct clk hdq_ick = {
1947         .name           = "hdq_ick",
1948         .ops            = &clkops_omap2_dflt_wait,
1949         .parent         = &core_l4_ick,
1950         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1951         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1952         .clkdm_name     = "core_l4_clkdm",
1953         .recalc         = &followparent_recalc,
1954 };
1955
1956 static struct clk mcspi4_ick = {
1957         .name           = "mcspi4_ick",
1958         .ops            = &clkops_omap2_dflt_wait,
1959         .parent         = &core_l4_ick,
1960         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1961         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1962         .clkdm_name     = "core_l4_clkdm",
1963         .recalc         = &followparent_recalc,
1964 };
1965
1966 static struct clk mcspi3_ick = {
1967         .name           = "mcspi3_ick",
1968         .ops            = &clkops_omap2_dflt_wait,
1969         .parent         = &core_l4_ick,
1970         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1971         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1972         .clkdm_name     = "core_l4_clkdm",
1973         .recalc         = &followparent_recalc,
1974 };
1975
1976 static struct clk mcspi2_ick = {
1977         .name           = "mcspi2_ick",
1978         .ops            = &clkops_omap2_dflt_wait,
1979         .parent         = &core_l4_ick,
1980         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1981         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1982         .clkdm_name     = "core_l4_clkdm",
1983         .recalc         = &followparent_recalc,
1984 };
1985
1986 static struct clk mcspi1_ick = {
1987         .name           = "mcspi1_ick",
1988         .ops            = &clkops_omap2_dflt_wait,
1989         .parent         = &core_l4_ick,
1990         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1991         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1992         .clkdm_name     = "core_l4_clkdm",
1993         .recalc         = &followparent_recalc,
1994 };
1995
1996 static struct clk i2c3_ick = {
1997         .name           = "i2c3_ick",
1998         .ops            = &clkops_omap2_dflt_wait,
1999         .parent         = &core_l4_ick,
2000         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2001         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
2002         .clkdm_name     = "core_l4_clkdm",
2003         .recalc         = &followparent_recalc,
2004 };
2005
2006 static struct clk i2c2_ick = {
2007         .name           = "i2c2_ick",
2008         .ops            = &clkops_omap2_dflt_wait,
2009         .parent         = &core_l4_ick,
2010         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2011         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2012         .clkdm_name     = "core_l4_clkdm",
2013         .recalc         = &followparent_recalc,
2014 };
2015
2016 static struct clk i2c1_ick = {
2017         .name           = "i2c1_ick",
2018         .ops            = &clkops_omap2_dflt_wait,
2019         .parent         = &core_l4_ick,
2020         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2021         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2022         .clkdm_name     = "core_l4_clkdm",
2023         .recalc         = &followparent_recalc,
2024 };
2025
2026 static struct clk uart2_ick = {
2027         .name           = "uart2_ick",
2028         .ops            = &clkops_omap2_dflt_wait,
2029         .parent         = &core_l4_ick,
2030         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2031         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2032         .clkdm_name     = "core_l4_clkdm",
2033         .recalc         = &followparent_recalc,
2034 };
2035
2036 static struct clk uart1_ick = {
2037         .name           = "uart1_ick",
2038         .ops            = &clkops_omap2_dflt_wait,
2039         .parent         = &core_l4_ick,
2040         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2041         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2042         .clkdm_name     = "core_l4_clkdm",
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk gpt11_ick = {
2047         .name           = "gpt11_ick",
2048         .ops            = &clkops_omap2_dflt_wait,
2049         .parent         = &core_l4_ick,
2050         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2051         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2052         .clkdm_name     = "core_l4_clkdm",
2053         .recalc         = &followparent_recalc,
2054 };
2055
2056 static struct clk gpt10_ick = {
2057         .name           = "gpt10_ick",
2058         .ops            = &clkops_omap2_dflt_wait,
2059         .parent         = &core_l4_ick,
2060         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2061         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2062         .clkdm_name     = "core_l4_clkdm",
2063         .recalc         = &followparent_recalc,
2064 };
2065
2066 static struct clk mcbsp5_ick = {
2067         .name           = "mcbsp5_ick",
2068         .ops            = &clkops_omap2_dflt_wait,
2069         .parent         = &core_l4_ick,
2070         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2071         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2072         .clkdm_name     = "core_l4_clkdm",
2073         .recalc         = &followparent_recalc,
2074 };
2075
2076 static struct clk mcbsp1_ick = {
2077         .name           = "mcbsp1_ick",
2078         .ops            = &clkops_omap2_dflt_wait,
2079         .parent         = &core_l4_ick,
2080         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2081         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2082         .clkdm_name     = "core_l4_clkdm",
2083         .recalc         = &followparent_recalc,
2084 };
2085
2086 static struct clk fac_ick = {
2087         .name           = "fac_ick",
2088         .ops            = &clkops_omap2_dflt_wait,
2089         .parent         = &core_l4_ick,
2090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2091         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2092         .clkdm_name     = "core_l4_clkdm",
2093         .recalc         = &followparent_recalc,
2094 };
2095
2096 static struct clk mailboxes_ick = {
2097         .name           = "mailboxes_ick",
2098         .ops            = &clkops_omap2_dflt_wait,
2099         .parent         = &core_l4_ick,
2100         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2101         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2102         .clkdm_name     = "core_l4_clkdm",
2103         .recalc         = &followparent_recalc,
2104 };
2105
2106 static struct clk omapctrl_ick = {
2107         .name           = "omapctrl_ick",
2108         .ops            = &clkops_omap2_dflt_wait,
2109         .parent         = &core_l4_ick,
2110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2111         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2112         .flags          = ENABLE_ON_INIT,
2113         .recalc         = &followparent_recalc,
2114 };
2115
2116 /* SSI_L4_ICK based clocks */
2117
2118 static struct clk ssi_l4_ick = {
2119         .name           = "ssi_l4_ick",
2120         .ops            = &clkops_null,
2121         .parent         = &l4_ick,
2122         .clkdm_name     = "core_l4_clkdm",
2123         .recalc         = &followparent_recalc,
2124 };
2125
2126 static struct clk ssi_ick_3430es1 = {
2127         .name           = "ssi_ick",
2128         .ops            = &clkops_omap2_dflt,
2129         .parent         = &ssi_l4_ick,
2130         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2131         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2132         .clkdm_name     = "core_l4_clkdm",
2133         .recalc         = &followparent_recalc,
2134 };
2135
2136 static struct clk ssi_ick_3430es2 = {
2137         .name           = "ssi_ick",
2138         .ops            = &clkops_omap3430es2_ssi_wait,
2139         .parent         = &ssi_l4_ick,
2140         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2141         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2142         .clkdm_name     = "core_l4_clkdm",
2143         .recalc         = &followparent_recalc,
2144 };
2145
2146 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2147  * but l4_ick makes more sense to me */
2148
2149 static const struct clksel usb_l4_clksel[] = {
2150         { .parent = &l4_ick, .rates = div2_rates },
2151         { .parent = NULL },
2152 };
2153
2154 static struct clk usb_l4_ick = {
2155         .name           = "usb_l4_ick",
2156         .ops            = &clkops_omap2_dflt_wait,
2157         .parent         = &l4_ick,
2158         .init           = &omap2_init_clksel_parent,
2159         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2160         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2161         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2162         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2163         .clksel         = usb_l4_clksel,
2164         .recalc         = &omap2_clksel_recalc,
2165 };
2166
2167 /* SECURITY_L4_ICK2 based clocks */
2168
2169 static struct clk security_l4_ick2 = {
2170         .name           = "security_l4_ick2",
2171         .ops            = &clkops_null,
2172         .parent         = &l4_ick,
2173         .recalc         = &followparent_recalc,
2174 };
2175
2176 static struct clk aes1_ick = {
2177         .name           = "aes1_ick",
2178         .ops            = &clkops_omap2_dflt_wait,
2179         .parent         = &security_l4_ick2,
2180         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2181         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk rng_ick = {
2186         .name           = "rng_ick",
2187         .ops            = &clkops_omap2_dflt_wait,
2188         .parent         = &security_l4_ick2,
2189         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2190         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 static struct clk sha11_ick = {
2195         .name           = "sha11_ick",
2196         .ops            = &clkops_omap2_dflt_wait,
2197         .parent         = &security_l4_ick2,
2198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2199         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk des1_ick = {
2204         .name           = "des1_ick",
2205         .ops            = &clkops_omap2_dflt_wait,
2206         .parent         = &security_l4_ick2,
2207         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2208         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 /* DSS */
2213 static struct clk dss1_alwon_fck_3430es1 = {
2214         .name           = "dss1_alwon_fck",
2215         .ops            = &clkops_omap2_dflt,
2216         .parent         = &dpll4_m4x2_ck,
2217         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2218         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2219         .clkdm_name     = "dss_clkdm",
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk dss1_alwon_fck_3430es2 = {
2224         .name           = "dss1_alwon_fck",
2225         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2226         .parent         = &dpll4_m4x2_ck,
2227         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2228         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2229         .clkdm_name     = "dss_clkdm",
2230         .recalc         = &followparent_recalc,
2231 };
2232
2233 static struct clk dss_tv_fck = {
2234         .name           = "dss_tv_fck",
2235         .ops            = &clkops_omap2_dflt,
2236         .parent         = &omap_54m_fck,
2237         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2238         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2239         .clkdm_name     = "dss_clkdm",
2240         .recalc         = &followparent_recalc,
2241 };
2242
2243 static struct clk dss_96m_fck = {
2244         .name           = "dss_96m_fck",
2245         .ops            = &clkops_omap2_dflt,
2246         .parent         = &omap_96m_fck,
2247         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2248         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2249         .clkdm_name     = "dss_clkdm",
2250         .recalc         = &followparent_recalc,
2251 };
2252
2253 static struct clk dss2_alwon_fck = {
2254         .name           = "dss2_alwon_fck",
2255         .ops            = &clkops_omap2_dflt,
2256         .parent         = &sys_ck,
2257         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2258         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2259         .clkdm_name     = "dss_clkdm",
2260         .recalc         = &followparent_recalc,
2261 };
2262
2263 static struct clk dss_ick_3430es1 = {
2264         /* Handles both L3 and L4 clocks */
2265         .name           = "dss_ick",
2266         .ops            = &clkops_omap2_dflt,
2267         .parent         = &l4_ick,
2268         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2269         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2270         .clkdm_name     = "dss_clkdm",
2271         .recalc         = &followparent_recalc,
2272 };
2273
2274 static struct clk dss_ick_3430es2 = {
2275         /* Handles both L3 and L4 clocks */
2276         .name           = "dss_ick",
2277         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2278         .parent         = &l4_ick,
2279         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2280         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2281         .clkdm_name     = "dss_clkdm",
2282         .recalc         = &followparent_recalc,
2283 };
2284
2285 /* CAM */
2286
2287 static struct clk cam_mclk = {
2288         .name           = "cam_mclk",
2289         .ops            = &clkops_omap2_dflt,
2290         .parent         = &dpll4_m5x2_ck,
2291         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2292         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2293         .clkdm_name     = "cam_clkdm",
2294         .recalc         = &followparent_recalc,
2295 };
2296
2297 static struct clk cam_ick = {
2298         /* Handles both L3 and L4 clocks */
2299         .name           = "cam_ick",
2300         .ops            = &clkops_omap2_dflt,
2301         .parent         = &l4_ick,
2302         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2303         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2304         .clkdm_name     = "cam_clkdm",
2305         .recalc         = &followparent_recalc,
2306 };
2307
2308 static struct clk csi2_96m_fck = {
2309         .name           = "csi2_96m_fck",
2310         .ops            = &clkops_omap2_dflt,
2311         .parent         = &core_96m_fck,
2312         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2313         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2314         .clkdm_name     = "cam_clkdm",
2315         .recalc         = &followparent_recalc,
2316 };
2317
2318 /* USBHOST - 3430ES2 only */
2319
2320 static struct clk usbhost_120m_fck = {
2321         .name           = "usbhost_120m_fck",
2322         .ops            = &clkops_omap2_dflt,
2323         .parent         = &dpll5_m2_ck,
2324         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2325         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2326         .clkdm_name     = "usbhost_clkdm",
2327         .recalc         = &followparent_recalc,
2328 };
2329
2330 static struct clk usbhost_48m_fck = {
2331         .name           = "usbhost_48m_fck",
2332         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2333         .parent         = &omap_48m_fck,
2334         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2335         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2336         .clkdm_name     = "usbhost_clkdm",
2337         .recalc         = &followparent_recalc,
2338 };
2339
2340 static struct clk usbhost_ick = {
2341         /* Handles both L3 and L4 clocks */
2342         .name           = "usbhost_ick",
2343         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2344         .parent         = &l4_ick,
2345         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2346         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2347         .clkdm_name     = "usbhost_clkdm",
2348         .recalc         = &followparent_recalc,
2349 };
2350
2351 /* WKUP */
2352
2353 static const struct clksel_rate usim_96m_rates[] = {
2354         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2355         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2356         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2357         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2358         { .div = 0 },
2359 };
2360
2361 static const struct clksel_rate usim_120m_rates[] = {
2362         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2363         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2364         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2365         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2366         { .div = 0 },
2367 };
2368
2369 static const struct clksel usim_clksel[] = {
2370         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2371         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2372         { .parent = &sys_ck,            .rates = div2_rates },
2373         { .parent = NULL },
2374 };
2375
2376 /* 3430ES2 only */
2377 static struct clk usim_fck = {
2378         .name           = "usim_fck",
2379         .ops            = &clkops_omap2_dflt_wait,
2380         .init           = &omap2_init_clksel_parent,
2381         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2382         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2383         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2384         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2385         .clksel         = usim_clksel,
2386         .recalc         = &omap2_clksel_recalc,
2387 };
2388
2389 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2390 static struct clk gpt1_fck = {
2391         .name           = "gpt1_fck",
2392         .ops            = &clkops_omap2_dflt_wait,
2393         .init           = &omap2_init_clksel_parent,
2394         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2395         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2396         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2397         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2398         .clksel         = omap343x_gpt_clksel,
2399         .clkdm_name     = "wkup_clkdm",
2400         .recalc         = &omap2_clksel_recalc,
2401 };
2402
2403 static struct clk wkup_32k_fck = {
2404         .name           = "wkup_32k_fck",
2405         .ops            = &clkops_null,
2406         .parent         = &omap_32k_fck,
2407         .clkdm_name     = "wkup_clkdm",
2408         .recalc         = &followparent_recalc,
2409 };
2410
2411 static struct clk gpio1_dbck = {
2412         .name           = "gpio1_dbck",
2413         .ops            = &clkops_omap2_dflt,
2414         .parent         = &wkup_32k_fck,
2415         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2416         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2417         .clkdm_name     = "wkup_clkdm",
2418         .recalc         = &followparent_recalc,
2419 };
2420
2421 static struct clk wdt2_fck = {
2422         .name           = "wdt2_fck",
2423         .ops            = &clkops_omap2_dflt_wait,
2424         .parent         = &wkup_32k_fck,
2425         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2426         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2427         .clkdm_name     = "wkup_clkdm",
2428         .recalc         = &followparent_recalc,
2429 };
2430
2431 static struct clk wkup_l4_ick = {
2432         .name           = "wkup_l4_ick",
2433         .ops            = &clkops_null,
2434         .parent         = &sys_ck,
2435         .clkdm_name     = "wkup_clkdm",
2436         .recalc         = &followparent_recalc,
2437 };
2438
2439 /* 3430ES2 only */
2440 /* Never specifically named in the TRM, so we have to infer a likely name */
2441 static struct clk usim_ick = {
2442         .name           = "usim_ick",
2443         .ops            = &clkops_omap2_dflt_wait,
2444         .parent         = &wkup_l4_ick,
2445         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2446         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2447         .clkdm_name     = "wkup_clkdm",
2448         .recalc         = &followparent_recalc,
2449 };
2450
2451 static struct clk wdt2_ick = {
2452         .name           = "wdt2_ick",
2453         .ops            = &clkops_omap2_dflt_wait,
2454         .parent         = &wkup_l4_ick,
2455         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2456         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2457         .clkdm_name     = "wkup_clkdm",
2458         .recalc         = &followparent_recalc,
2459 };
2460
2461 static struct clk wdt1_ick = {
2462         .name           = "wdt1_ick",
2463         .ops            = &clkops_omap2_dflt_wait,
2464         .parent         = &wkup_l4_ick,
2465         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2466         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2467         .clkdm_name     = "wkup_clkdm",
2468         .recalc         = &followparent_recalc,
2469 };
2470
2471 static struct clk gpio1_ick = {
2472         .name           = "gpio1_ick",
2473         .ops            = &clkops_omap2_dflt_wait,
2474         .parent         = &wkup_l4_ick,
2475         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2476         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2477         .clkdm_name     = "wkup_clkdm",
2478         .recalc         = &followparent_recalc,
2479 };
2480
2481 static struct clk omap_32ksync_ick = {
2482         .name           = "omap_32ksync_ick",
2483         .ops            = &clkops_omap2_dflt_wait,
2484         .parent         = &wkup_l4_ick,
2485         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2486         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2487         .clkdm_name     = "wkup_clkdm",
2488         .recalc         = &followparent_recalc,
2489 };
2490
2491 /* XXX This clock no longer exists in 3430 TRM rev F */
2492 static struct clk gpt12_ick = {
2493         .name           = "gpt12_ick",
2494         .ops            = &clkops_omap2_dflt_wait,
2495         .parent         = &wkup_l4_ick,
2496         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2497         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2498         .clkdm_name     = "wkup_clkdm",
2499         .recalc         = &followparent_recalc,
2500 };
2501
2502 static struct clk gpt1_ick = {
2503         .name           = "gpt1_ick",
2504         .ops            = &clkops_omap2_dflt_wait,
2505         .parent         = &wkup_l4_ick,
2506         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2507         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2508         .clkdm_name     = "wkup_clkdm",
2509         .recalc         = &followparent_recalc,
2510 };
2511
2512
2513
2514 /* PER clock domain */
2515
2516 static struct clk per_96m_fck = {
2517         .name           = "per_96m_fck",
2518         .ops            = &clkops_null,
2519         .parent         = &omap_96m_alwon_fck,
2520         .clkdm_name     = "per_clkdm",
2521         .recalc         = &followparent_recalc,
2522 };
2523
2524 static struct clk per_48m_fck = {
2525         .name           = "per_48m_fck",
2526         .ops            = &clkops_null,
2527         .parent         = &omap_48m_fck,
2528         .clkdm_name     = "per_clkdm",
2529         .recalc         = &followparent_recalc,
2530 };
2531
2532 static struct clk uart3_fck = {
2533         .name           = "uart3_fck",
2534         .ops            = &clkops_omap2_dflt_wait,
2535         .parent         = &per_48m_fck,
2536         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2537         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2538         .clkdm_name     = "per_clkdm",
2539         .recalc         = &followparent_recalc,
2540 };
2541
2542 static struct clk gpt2_fck = {
2543         .name           = "gpt2_fck",
2544         .ops            = &clkops_omap2_dflt_wait,
2545         .init           = &omap2_init_clksel_parent,
2546         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2547         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2548         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2549         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2550         .clksel         = omap343x_gpt_clksel,
2551         .clkdm_name     = "per_clkdm",
2552         .recalc         = &omap2_clksel_recalc,
2553 };
2554
2555 static struct clk gpt3_fck = {
2556         .name           = "gpt3_fck",
2557         .ops            = &clkops_omap2_dflt_wait,
2558         .init           = &omap2_init_clksel_parent,
2559         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2560         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2561         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2562         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2563         .clksel         = omap343x_gpt_clksel,
2564         .clkdm_name     = "per_clkdm",
2565         .recalc         = &omap2_clksel_recalc,
2566 };
2567
2568 static struct clk gpt4_fck = {
2569         .name           = "gpt4_fck",
2570         .ops            = &clkops_omap2_dflt_wait,
2571         .init           = &omap2_init_clksel_parent,
2572         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2573         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2574         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2575         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2576         .clksel         = omap343x_gpt_clksel,
2577         .clkdm_name     = "per_clkdm",
2578         .recalc         = &omap2_clksel_recalc,
2579 };
2580
2581 static struct clk gpt5_fck = {
2582         .name           = "gpt5_fck",
2583         .ops            = &clkops_omap2_dflt_wait,
2584         .init           = &omap2_init_clksel_parent,
2585         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2586         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2587         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2588         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2589         .clksel         = omap343x_gpt_clksel,
2590         .clkdm_name     = "per_clkdm",
2591         .recalc         = &omap2_clksel_recalc,
2592 };
2593
2594 static struct clk gpt6_fck = {
2595         .name           = "gpt6_fck",
2596         .ops            = &clkops_omap2_dflt_wait,
2597         .init           = &omap2_init_clksel_parent,
2598         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2599         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2600         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2601         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2602         .clksel         = omap343x_gpt_clksel,
2603         .clkdm_name     = "per_clkdm",
2604         .recalc         = &omap2_clksel_recalc,
2605 };
2606
2607 static struct clk gpt7_fck = {
2608         .name           = "gpt7_fck",
2609         .ops            = &clkops_omap2_dflt_wait,
2610         .init           = &omap2_init_clksel_parent,
2611         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2612         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2613         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2614         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2615         .clksel         = omap343x_gpt_clksel,
2616         .clkdm_name     = "per_clkdm",
2617         .recalc         = &omap2_clksel_recalc,
2618 };
2619
2620 static struct clk gpt8_fck = {
2621         .name           = "gpt8_fck",
2622         .ops            = &clkops_omap2_dflt_wait,
2623         .init           = &omap2_init_clksel_parent,
2624         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2625         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2626         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2627         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2628         .clksel         = omap343x_gpt_clksel,
2629         .clkdm_name     = "per_clkdm",
2630         .recalc         = &omap2_clksel_recalc,
2631 };
2632
2633 static struct clk gpt9_fck = {
2634         .name           = "gpt9_fck",
2635         .ops            = &clkops_omap2_dflt_wait,
2636         .init           = &omap2_init_clksel_parent,
2637         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2638         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2639         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2640         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2641         .clksel         = omap343x_gpt_clksel,
2642         .clkdm_name     = "per_clkdm",
2643         .recalc         = &omap2_clksel_recalc,
2644 };
2645
2646 static struct clk per_32k_alwon_fck = {
2647         .name           = "per_32k_alwon_fck",
2648         .ops            = &clkops_null,
2649         .parent         = &omap_32k_fck,
2650         .clkdm_name     = "per_clkdm",
2651         .recalc         = &followparent_recalc,
2652 };
2653
2654 static struct clk gpio6_dbck = {
2655         .name           = "gpio6_dbck",
2656         .ops            = &clkops_omap2_dflt,
2657         .parent         = &per_32k_alwon_fck,
2658         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2659         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2660         .clkdm_name     = "per_clkdm",
2661         .recalc         = &followparent_recalc,
2662 };
2663
2664 static struct clk gpio5_dbck = {
2665         .name           = "gpio5_dbck",
2666         .ops            = &clkops_omap2_dflt,
2667         .parent         = &per_32k_alwon_fck,
2668         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2669         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2670         .clkdm_name     = "per_clkdm",
2671         .recalc         = &followparent_recalc,
2672 };
2673
2674 static struct clk gpio4_dbck = {
2675         .name           = "gpio4_dbck",
2676         .ops            = &clkops_omap2_dflt,
2677         .parent         = &per_32k_alwon_fck,
2678         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2679         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2680         .clkdm_name     = "per_clkdm",
2681         .recalc         = &followparent_recalc,
2682 };
2683
2684 static struct clk gpio3_dbck = {
2685         .name           = "gpio3_dbck",
2686         .ops            = &clkops_omap2_dflt,
2687         .parent         = &per_32k_alwon_fck,
2688         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2689         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2690         .clkdm_name     = "per_clkdm",
2691         .recalc         = &followparent_recalc,
2692 };
2693
2694 static struct clk gpio2_dbck = {
2695         .name           = "gpio2_dbck",
2696         .ops            = &clkops_omap2_dflt,
2697         .parent         = &per_32k_alwon_fck,
2698         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2699         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2700         .clkdm_name     = "per_clkdm",
2701         .recalc         = &followparent_recalc,
2702 };
2703
2704 static struct clk wdt3_fck = {
2705         .name           = "wdt3_fck",
2706         .ops            = &clkops_omap2_dflt_wait,
2707         .parent         = &per_32k_alwon_fck,
2708         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2709         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2710         .clkdm_name     = "per_clkdm",
2711         .recalc         = &followparent_recalc,
2712 };
2713
2714 static struct clk per_l4_ick = {
2715         .name           = "per_l4_ick",
2716         .ops            = &clkops_null,
2717         .parent         = &l4_ick,
2718         .clkdm_name     = "per_clkdm",
2719         .recalc         = &followparent_recalc,
2720 };
2721
2722 static struct clk gpio6_ick = {
2723         .name           = "gpio6_ick",
2724         .ops            = &clkops_omap2_dflt_wait,
2725         .parent         = &per_l4_ick,
2726         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2727         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2728         .clkdm_name     = "per_clkdm",
2729         .recalc         = &followparent_recalc,
2730 };
2731
2732 static struct clk gpio5_ick = {
2733         .name           = "gpio5_ick",
2734         .ops            = &clkops_omap2_dflt_wait,
2735         .parent         = &per_l4_ick,
2736         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2737         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2738         .clkdm_name     = "per_clkdm",
2739         .recalc         = &followparent_recalc,
2740 };
2741
2742 static struct clk gpio4_ick = {
2743         .name           = "gpio4_ick",
2744         .ops            = &clkops_omap2_dflt_wait,
2745         .parent         = &per_l4_ick,
2746         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2747         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2748         .clkdm_name     = "per_clkdm",
2749         .recalc         = &followparent_recalc,
2750 };
2751
2752 static struct clk gpio3_ick = {
2753         .name           = "gpio3_ick",
2754         .ops            = &clkops_omap2_dflt_wait,
2755         .parent         = &per_l4_ick,
2756         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2757         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2758         .clkdm_name     = "per_clkdm",
2759         .recalc         = &followparent_recalc,
2760 };
2761
2762 static struct clk gpio2_ick = {
2763         .name           = "gpio2_ick",
2764         .ops            = &clkops_omap2_dflt_wait,
2765         .parent         = &per_l4_ick,
2766         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2767         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2768         .clkdm_name     = "per_clkdm",
2769         .recalc         = &followparent_recalc,
2770 };
2771
2772 static struct clk wdt3_ick = {
2773         .name           = "wdt3_ick",
2774         .ops            = &clkops_omap2_dflt_wait,
2775         .parent         = &per_l4_ick,
2776         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2777         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2778         .clkdm_name     = "per_clkdm",
2779         .recalc         = &followparent_recalc,
2780 };
2781
2782 static struct clk uart3_ick = {
2783         .name           = "uart3_ick",
2784         .ops            = &clkops_omap2_dflt_wait,
2785         .parent         = &per_l4_ick,
2786         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2787         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2788         .clkdm_name     = "per_clkdm",
2789         .recalc         = &followparent_recalc,
2790 };
2791
2792 static struct clk gpt9_ick = {
2793         .name           = "gpt9_ick",
2794         .ops            = &clkops_omap2_dflt_wait,
2795         .parent         = &per_l4_ick,
2796         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2797         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2798         .clkdm_name     = "per_clkdm",
2799         .recalc         = &followparent_recalc,
2800 };
2801
2802 static struct clk gpt8_ick = {
2803         .name           = "gpt8_ick",
2804         .ops            = &clkops_omap2_dflt_wait,
2805         .parent         = &per_l4_ick,
2806         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2807         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2808         .clkdm_name     = "per_clkdm",
2809         .recalc         = &followparent_recalc,
2810 };
2811
2812 static struct clk gpt7_ick = {
2813         .name           = "gpt7_ick",
2814         .ops            = &clkops_omap2_dflt_wait,
2815         .parent         = &per_l4_ick,
2816         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2817         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2818         .clkdm_name     = "per_clkdm",
2819         .recalc         = &followparent_recalc,
2820 };
2821
2822 static struct clk gpt6_ick = {
2823         .name           = "gpt6_ick",
2824         .ops            = &clkops_omap2_dflt_wait,
2825         .parent         = &per_l4_ick,
2826         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2827         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2828         .clkdm_name     = "per_clkdm",
2829         .recalc         = &followparent_recalc,
2830 };
2831
2832 static struct clk gpt5_ick = {
2833         .name           = "gpt5_ick",
2834         .ops            = &clkops_omap2_dflt_wait,
2835         .parent         = &per_l4_ick,
2836         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2837         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2838         .clkdm_name     = "per_clkdm",
2839         .recalc         = &followparent_recalc,
2840 };
2841
2842 static struct clk gpt4_ick = {
2843         .name           = "gpt4_ick",
2844         .ops            = &clkops_omap2_dflt_wait,
2845         .parent         = &per_l4_ick,
2846         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2847         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2848         .clkdm_name     = "per_clkdm",
2849         .recalc         = &followparent_recalc,
2850 };
2851
2852 static struct clk gpt3_ick = {
2853         .name           = "gpt3_ick",
2854         .ops            = &clkops_omap2_dflt_wait,
2855         .parent         = &per_l4_ick,
2856         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2857         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2858         .clkdm_name     = "per_clkdm",
2859         .recalc         = &followparent_recalc,
2860 };
2861
2862 static struct clk gpt2_ick = {
2863         .name           = "gpt2_ick",
2864         .ops            = &clkops_omap2_dflt_wait,
2865         .parent         = &per_l4_ick,
2866         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2867         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2868         .clkdm_name     = "per_clkdm",
2869         .recalc         = &followparent_recalc,
2870 };
2871
2872 static struct clk mcbsp2_ick = {
2873         .name           = "mcbsp2_ick",
2874         .ops            = &clkops_omap2_dflt_wait,
2875         .parent         = &per_l4_ick,
2876         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2877         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2878         .clkdm_name     = "per_clkdm",
2879         .recalc         = &followparent_recalc,
2880 };
2881
2882 static struct clk mcbsp3_ick = {
2883         .name           = "mcbsp3_ick",
2884         .ops            = &clkops_omap2_dflt_wait,
2885         .parent         = &per_l4_ick,
2886         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2887         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2888         .clkdm_name     = "per_clkdm",
2889         .recalc         = &followparent_recalc,
2890 };
2891
2892 static struct clk mcbsp4_ick = {
2893         .name           = "mcbsp4_ick",
2894         .ops            = &clkops_omap2_dflt_wait,
2895         .parent         = &per_l4_ick,
2896         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2897         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2898         .clkdm_name     = "per_clkdm",
2899         .recalc         = &followparent_recalc,
2900 };
2901
2902 static const struct clksel mcbsp_234_clksel[] = {
2903         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2904         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2905         { .parent = NULL }
2906 };
2907
2908 static struct clk mcbsp2_fck = {
2909         .name           = "mcbsp2_fck",
2910         .ops            = &clkops_omap2_dflt_wait,
2911         .init           = &omap2_init_clksel_parent,
2912         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2913         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2914         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2915         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2916         .clksel         = mcbsp_234_clksel,
2917         .clkdm_name     = "per_clkdm",
2918         .recalc         = &omap2_clksel_recalc,
2919 };
2920
2921 static struct clk mcbsp3_fck = {
2922         .name           = "mcbsp3_fck",
2923         .ops            = &clkops_omap2_dflt_wait,
2924         .init           = &omap2_init_clksel_parent,
2925         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2926         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2927         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2928         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2929         .clksel         = mcbsp_234_clksel,
2930         .clkdm_name     = "per_clkdm",
2931         .recalc         = &omap2_clksel_recalc,
2932 };
2933
2934 static struct clk mcbsp4_fck = {
2935         .name           = "mcbsp4_fck",
2936         .ops            = &clkops_omap2_dflt_wait,
2937         .init           = &omap2_init_clksel_parent,
2938         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2939         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2940         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2941         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2942         .clksel         = mcbsp_234_clksel,
2943         .clkdm_name     = "per_clkdm",
2944         .recalc         = &omap2_clksel_recalc,
2945 };
2946
2947 /* EMU clocks */
2948
2949 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2950
2951 static const struct clksel_rate emu_src_sys_rates[] = {
2952         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2953         { .div = 0 },
2954 };
2955
2956 static const struct clksel_rate emu_src_core_rates[] = {
2957         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2958         { .div = 0 },
2959 };
2960
2961 static const struct clksel_rate emu_src_per_rates[] = {
2962         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2963         { .div = 0 },
2964 };
2965
2966 static const struct clksel_rate emu_src_mpu_rates[] = {
2967         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2968         { .div = 0 },
2969 };
2970
2971 static const struct clksel emu_src_clksel[] = {
2972         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2973         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2974         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2975         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2976         { .parent = NULL },
2977 };
2978
2979 /*
2980  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2981  * to switch the source of some of the EMU clocks.
2982  * XXX Are there CLKEN bits for these EMU clks?
2983  */
2984 static struct clk emu_src_ck = {
2985         .name           = "emu_src_ck",
2986         .ops            = &clkops_null,
2987         .init           = &omap2_init_clksel_parent,
2988         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2989         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2990         .clksel         = emu_src_clksel,
2991         .clkdm_name     = "emu_clkdm",
2992         .recalc         = &omap2_clksel_recalc,
2993 };
2994
2995 static const struct clksel_rate pclk_emu_rates[] = {
2996         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2997         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2998         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2999         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3000         { .div = 0 },
3001 };
3002
3003 static const struct clksel pclk_emu_clksel[] = {
3004         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3005         { .parent = NULL },
3006 };
3007
3008 static struct clk pclk_fck = {
3009         .name           = "pclk_fck",
3010         .ops            = &clkops_null,
3011         .init           = &omap2_init_clksel_parent,
3012         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3013         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3014         .clksel         = pclk_emu_clksel,
3015         .clkdm_name     = "emu_clkdm",
3016         .recalc         = &omap2_clksel_recalc,
3017 };
3018
3019 static const struct clksel_rate pclkx2_emu_rates[] = {
3020         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3021         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3022         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3023         { .div = 0 },
3024 };
3025
3026 static const struct clksel pclkx2_emu_clksel[] = {
3027         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3028         { .parent = NULL },
3029 };
3030
3031 static struct clk pclkx2_fck = {
3032         .name           = "pclkx2_fck",
3033         .ops            = &clkops_null,
3034         .init           = &omap2_init_clksel_parent,
3035         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3036         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3037         .clksel         = pclkx2_emu_clksel,
3038         .clkdm_name     = "emu_clkdm",
3039         .recalc         = &omap2_clksel_recalc,
3040 };
3041
3042 static const struct clksel atclk_emu_clksel[] = {
3043         { .parent = &emu_src_ck, .rates = div2_rates },
3044         { .parent = NULL },
3045 };
3046
3047 static struct clk atclk_fck = {
3048         .name           = "atclk_fck",
3049         .ops            = &clkops_null,
3050         .init           = &omap2_init_clksel_parent,
3051         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3052         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3053         .clksel         = atclk_emu_clksel,
3054         .clkdm_name     = "emu_clkdm",
3055         .recalc         = &omap2_clksel_recalc,
3056 };
3057
3058 static struct clk traceclk_src_fck = {
3059         .name           = "traceclk_src_fck",
3060         .ops            = &clkops_null,
3061         .init           = &omap2_init_clksel_parent,
3062         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3063         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3064         .clksel         = emu_src_clksel,
3065         .clkdm_name     = "emu_clkdm",
3066         .recalc         = &omap2_clksel_recalc,
3067 };
3068
3069 static const struct clksel_rate traceclk_rates[] = {
3070         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3071         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3072         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3073         { .div = 0 },
3074 };
3075
3076 static const struct clksel traceclk_clksel[] = {
3077         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3078         { .parent = NULL },
3079 };
3080
3081 static struct clk traceclk_fck = {
3082         .name           = "traceclk_fck",
3083         .ops            = &clkops_null,
3084         .init           = &omap2_init_clksel_parent,
3085         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3086         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3087         .clksel         = traceclk_clksel,
3088         .clkdm_name     = "emu_clkdm",
3089         .recalc         = &omap2_clksel_recalc,
3090 };
3091
3092 /* SR clocks */
3093
3094 /* SmartReflex fclk (VDD1) */
3095 static struct clk sr1_fck = {
3096         .name           = "sr1_fck",
3097         .ops            = &clkops_omap2_dflt_wait,
3098         .parent         = &sys_ck,
3099         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3100         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3101         .recalc         = &followparent_recalc,
3102 };
3103
3104 /* SmartReflex fclk (VDD2) */
3105 static struct clk sr2_fck = {
3106         .name           = "sr2_fck",
3107         .ops            = &clkops_omap2_dflt_wait,
3108         .parent         = &sys_ck,
3109         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3110         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3111         .recalc         = &followparent_recalc,
3112 };
3113
3114 static struct clk sr_l4_ick = {
3115         .name           = "sr_l4_ick",
3116         .ops            = &clkops_null, /* RMK: missing? */
3117         .parent         = &l4_ick,
3118         .clkdm_name     = "core_l4_clkdm",
3119         .recalc         = &followparent_recalc,
3120 };
3121
3122 /* SECURE_32K_FCK clocks */
3123
3124 static struct clk gpt12_fck = {
3125         .name           = "gpt12_fck",
3126         .ops            = &clkops_null,
3127         .parent         = &secure_32k_fck,
3128         .recalc         = &followparent_recalc,
3129 };
3130
3131 static struct clk wdt1_fck = {
3132         .name           = "wdt1_fck",
3133         .ops            = &clkops_null,
3134         .parent         = &secure_32k_fck,
3135         .recalc         = &followparent_recalc,
3136 };
3137
3138 /* Clocks for AM35XX */
3139 static struct clk ipss_ick = {
3140         .name           = "ipss_ick",
3141         .ops            = &clkops_am35xx_ipss_wait,
3142         .parent         = &core_l3_ick,
3143         .clkdm_name     = "core_l3_clkdm",
3144         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3145         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
3146         .recalc         = &followparent_recalc,
3147 };
3148
3149 static struct clk emac_ick = {
3150         .name           = "emac_ick",
3151         .ops            = &clkops_am35xx_ipss_module_wait,
3152         .parent         = &ipss_ick,
3153         .clkdm_name     = "core_l3_clkdm",
3154         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3155         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3156         .recalc         = &followparent_recalc,
3157 };
3158
3159 static struct clk rmii_ck = {
3160         .name           = "rmii_ck",
3161         .ops            = &clkops_null,
3162         .rate           = 50000000,
3163 };
3164
3165 static struct clk emac_fck = {
3166         .name           = "emac_fck",
3167         .ops            = &clkops_omap2_dflt,
3168         .parent         = &rmii_ck,
3169         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3170         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
3171         .recalc         = &followparent_recalc,
3172 };
3173
3174 static struct clk hsotgusb_ick_am35xx = {
3175         .name           = "hsotgusb_ick",
3176         .ops            = &clkops_am35xx_ipss_module_wait,
3177         .parent         = &ipss_ick,
3178         .clkdm_name     = "core_l3_clkdm",
3179         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3180         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3181         .recalc         = &followparent_recalc,
3182 };
3183
3184 static struct clk hsotgusb_fck_am35xx = {
3185         .name           = "hsotgusb_fck",
3186         .ops            = &clkops_omap2_dflt,
3187         .parent         = &sys_ck,
3188         .clkdm_name     = "core_l3_clkdm",
3189         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3190         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
3191         .recalc         = &followparent_recalc,
3192 };
3193
3194 static struct clk hecc_ck = {
3195         .name           = "hecc_ck",
3196         .ops            = &clkops_am35xx_ipss_module_wait,
3197         .parent         = &sys_ck,
3198         .clkdm_name     = "core_l3_clkdm",
3199         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3200         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
3201         .recalc         = &followparent_recalc,
3202 };
3203
3204 static struct clk vpfe_ick = {
3205         .name           = "vpfe_ick",
3206         .ops            = &clkops_am35xx_ipss_module_wait,
3207         .parent         = &ipss_ick,
3208         .clkdm_name     = "core_l3_clkdm",
3209         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3210         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3211         .recalc         = &followparent_recalc,
3212 };
3213
3214 static struct clk pclk_ck = {
3215         .name           = "pclk_ck",
3216         .ops            = &clkops_null,
3217         .rate           = 27000000,
3218 };
3219
3220 static struct clk vpfe_fck = {
3221         .name           = "vpfe_fck",
3222         .ops            = &clkops_omap2_dflt,
3223         .parent         = &pclk_ck,
3224         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3225         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3226         .recalc         = &followparent_recalc,
3227 };
3228
3229 /*
3230  * The UART1/2 functional clock acts as the functional
3231  * clock for UART4. No separate fclk control available.
3232  */
3233 static struct clk uart4_ick_am35xx = {
3234         .name           = "uart4_ick",
3235         .ops            = &clkops_omap2_dflt_wait,
3236         .parent         = &core_l4_ick,
3237         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3238         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3239         .clkdm_name     = "core_l4_clkdm",
3240         .recalc         = &followparent_recalc,
3241 };
3242
3243
3244 /*
3245  * clkdev
3246  */
3247
3248 /* XXX At some point we should rename this file to clock3xxx_data.c */
3249 static struct omap_clk omap3xxx_clks[] = {
3250         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3251         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3252         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3253         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3254         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3255         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
3256         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3257         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3258         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3259         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3260         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3261         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3262         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3263         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3264         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3265         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
3266         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
3267         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3268         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3269         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3270         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3271         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3272         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3273         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3274         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3275         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3276         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3277         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3278         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3279         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3280         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3281         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3282         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3283         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3284         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3285         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3286         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3287         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3288         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3289         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3290         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3291         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3292         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3293         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3294         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3295         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2 | CK_AM35XX),
3296         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2 | CK_AM35XX),
3297         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3298         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3299         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3300         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3301         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3302         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3303         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3304         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
3305         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
3306         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3307         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3308         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3309         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3310         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3311         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3312         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3313         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3314         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2 | CK_3517),
3315         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2 | CK_3517),
3316         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3317         CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
3318         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
3319         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
3320         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3321         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3322         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
3323         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
3324         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
3325         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3326         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
3327         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
3328         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
3329         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
3330         CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_3XXX),
3331         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_3XXX),
3332         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_3XXX),
3333         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
3334         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
3335         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3336         CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_3XXX),
3337         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_3XXX),
3338         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_3XXX),
3339         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_3XXX),
3340         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3341         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3342         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3343         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3344         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
3345         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3346         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
3347         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3348         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
3349         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3350         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3351         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
3352         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3353         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3354         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
3355         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
3356         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3357         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2 | CK_AM35XX),
3358         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
3359         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
3360         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
3361         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
3362         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
3363         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
3364         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
3365         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
3366         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3367         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3368         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3369         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3370         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3371         CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_3XXX),
3372         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_3XXX),
3373         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_3XXX),
3374         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3375         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3376         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3377         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3378         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3379         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3380         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3381         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
3382         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3383         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
3384         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3385         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
3386         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3387         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
3388         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
3389         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
3390         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
3391         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
3392         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
3393         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3394         CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_3XXX),
3395         CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_3XXX),
3396         CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_3XXX),
3397         CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
3398         CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2 | CK_AM35XX),
3399         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
3400         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
3401         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
3402         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3403         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3404         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2 | CK_AM35XX),
3405         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
3406         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3407         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3408         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3409         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
3410         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
3411         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
3412         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3413         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3414         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3415         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3416         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3417         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3418         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3419         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3420         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3421         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3422         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3423         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3424         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3425         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3426         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3427         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3428         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3429         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3430         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3431         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3432         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3433         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3434         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3435         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3436         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3437         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3438         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3439         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3440         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3441         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3442         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3443         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3444         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3445         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3446         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3447         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3448         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3449         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3450         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3451         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3452         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3453         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3454         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3455         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_3XXX),
3456         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_3XXX),
3457         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_3XXX),
3458         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3459         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3460         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3461         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3462         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3463         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3464         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
3465         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
3466         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
3467         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3468         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3469         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3470         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3471         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3472         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3473         CLK("davinci_emac",     "ick",          &emac_ick,      CK_AM35XX),
3474         CLK("davinci_emac",     "fck",          &emac_fck,      CK_AM35XX),
3475         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3476         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3477         CLK("musb_hdrc",        "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
3478         CLK("musb_hdrc",        "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
3479         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3480         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3481 };
3482
3483
3484 int __init omap3xxx_clk_init(void)
3485 {
3486         struct omap_clk *c;
3487         u32 cpu_clkflg = CK_3XXX;
3488
3489         if (cpu_is_omap3517()) {
3490                 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3491                 cpu_clkflg |= CK_3517;
3492         } else if (cpu_is_omap3505()) {
3493                 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3494                 cpu_clkflg |= CK_3505;
3495         } else if (cpu_is_omap34xx()) {
3496                 cpu_mask = RATE_IN_343X;
3497                 cpu_clkflg |= CK_343X;
3498
3499                 /*
3500                  * Update this if there are further clock changes between ES2
3501                  * and production parts
3502                  */
3503                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3504                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3505                         cpu_clkflg |= CK_3430ES1;
3506                 } else {
3507                         cpu_mask |= RATE_IN_3430ES2;
3508                         cpu_clkflg |= CK_3430ES2;
3509                 }
3510         }
3511         if (omap3_has_192mhz_clk())
3512                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3513
3514         if (cpu_is_omap3630()) {
3515                 cpu_mask |= RATE_IN_36XX;
3516                 cpu_clkflg |= CK_36XX;
3517
3518                 /*
3519                  * XXX This type of dynamic rewriting of the clock tree is
3520                  * deprecated and should be revised soon.
3521                  */
3522                 dpll4_m2_ck = dpll4_m2_ck_3630;
3523                 dpll4_m3_ck = dpll4_m3_ck_3630;
3524                 dpll4_m4_ck = dpll4_m4_ck_3630;
3525                 dpll4_m5_ck = dpll4_m5_ck_3630;
3526                 dpll4_m6_ck = dpll4_m6_ck_3630;
3527
3528                 /*
3529                  * For 3630: override clkops_omap2_dflt_wait for the
3530                  * clocks affected from PWRDN reset Limitation
3531                  */
3532                 dpll3_m3x2_ck.ops =
3533                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3534                 dpll4_m2x2_ck.ops =
3535                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3536                 dpll4_m3x2_ck.ops =
3537                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3538                 dpll4_m4x2_ck.ops =
3539                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3540                 dpll4_m5x2_ck.ops =
3541                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3542                 dpll4_m6x2_ck.ops =
3543                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3544         } else {
3545                 /*
3546                  * XXX This type of dynamic rewriting of the clock tree is
3547                  * deprecated and should be revised soon.
3548                  */
3549                 dpll4_m2_ck = dpll4_m2_ck_34xx;
3550                 dpll4_m3_ck = dpll4_m3_ck_34xx;
3551                 dpll4_m4_ck = dpll4_m4_ck_34xx;
3552                 dpll4_m5_ck = dpll4_m5_ck_34xx;
3553                 dpll4_m6_ck = dpll4_m6_ck_34xx;
3554         }
3555
3556         if (cpu_is_omap3630())
3557                 dpll4_dd = dpll4_dd_3630;
3558         else
3559                 dpll4_dd = dpll4_dd_34xx;
3560
3561         clk_init(&omap2_clk_functions);
3562
3563         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3564              c++)
3565                 clk_preinit(c->lk.clk);
3566
3567         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3568              c++)
3569                 if (c->cpu & cpu_clkflg) {
3570                         clkdev_add(&c->lk);
3571                         clk_register(c->lk.clk);
3572                         omap2_init_clk_clkdm(c->lk.clk);
3573                 }
3574
3575         recalculate_root_clocks();
3576
3577         printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3578                "%ld.%01ld/%ld/%ld MHz\n",
3579                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3580                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3581
3582         /*
3583          * Only enable those clocks we will need, let the drivers
3584          * enable other clocks as necessary
3585          */
3586         clk_enable_init_clocks();
3587
3588         /*
3589          * Lock DPLL5 and put it in autoidle.
3590          */
3591         if (omap_rev() >= OMAP3430_REV_ES2_0)
3592                 omap3_clk_lock_dpll5();
3593
3594         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3595         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3596         arm_fck_p = clk_get(NULL, "arm_fck");
3597
3598         return 0;
3599 }