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   1 /*
   2  * Author: MontaVista Software, Inc.
   3  *       <source@mvista.com>
   4  *
   5  * Based on the OMAP devices.c
   6  *
   7  * 2005 (c) MontaVista Software, Inc. This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  *
  12  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version 2
  18  * of the License, or (at your option) any later version.
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27  * MA 02110-1301, USA.
  28  */
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/init.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/gpio.h>
  34
  35 #include <mach/irqs.h>
  36 #include <mach/hardware.h>
  37 #include <mach/common.h>
  38 #include <mach/mmc.h>
  39
  40 #include "devices.h"
  41
  42 /*
  43  * SPI master controller
  44  *
  45  * - i.MX1: 2 channel (slighly different register setting)
  46  * - i.MX21: 2 channel
  47  * - i.MX27: 3 channel
  48  */
  49 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)                                 \
  50         static struct resource mxc_spi_resources ## n[] = {                     \
  51                 {                                                               \
  52                         .start = baseaddr,                                      \
  53                         .end = baseaddr + SZ_4K - 1,                            \
  54                         .flags = IORESOURCE_MEM,                                \
  55                 }, {                                                            \
  56                         .start = irq,                                           \
  57                         .end = irq,                                             \
  58                         .flags = IORESOURCE_IRQ,                                \
  59                 },                                                              \
  60         };                                                                      \
  61                                                                                 \
  62         struct platform_device mxc_spi_device ## n = {                          \
  63                 .name = "spi_imx",                                              \
  64                 .id = n,                                                        \
  65                 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n),            \
  66                 .resource = mxc_spi_resources ## n,                             \
  67         }
  68
  69 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
  70 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
  71
  72 #ifdef CONFIG_MACH_MX27
  73 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
  74 #endif
  75
  76 /*
  77  * General Purpose Timer
  78  * - i.MX21: 3 timers
  79  * - i.MX27: 6 timers
  80  */
  81 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq)                         \
  82         static struct resource timer ## n ##_resources[] = {            \
  83                 {                                                       \
  84                         .start = baseaddr,                              \
  85                         .end = baseaddr + SZ_4K - 1,                    \
  86                         .flags = IORESOURCE_MEM,                        \
  87                 }, {                                                    \
  88                         .start = irq,                                   \
  89                         .end = irq,                                     \
  90                         .flags = IORESOURCE_IRQ,                        \
  91                 }                                                       \
  92         };                                                              \
  93                                                                         \
  94         struct platform_device mxc_gpt ## n = {                         \
  95                 .name = "imx_gpt",                                      \
  96                 .id = n,                                                \
  97                 .num_resources = ARRAY_SIZE(timer ## n ## _resources),  \
  98                 .resource = timer ## n ## _resources,                   \
  99         }
 100
 101 /* We use gpt1 as system timer, so do not add a device for this one */
 102 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
 103 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
 104
 105 #ifdef CONFIG_MACH_MX27
 106 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
 107 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
 108 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
 109 #endif
 110
 111 /*
 112  * Watchdog:
 113  * - i.MX1
 114  * - i.MX21
 115  * - i.MX27
 116  */
 117 static struct resource mxc_wdt_resources[] = {
 118         {
 119                 .start  = WDOG_BASE_ADDR,
 120                 .end    = WDOG_BASE_ADDR + 0x30,
 121                 .flags  = IORESOURCE_MEM,
 122         },
 123 };
 124
 125 struct platform_device mxc_wdt = {
 126         .name = "mxc_wdt",
 127         .id = 0,
 128         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
 129         .resource = mxc_wdt_resources,
 130 };
 131
 132 static struct resource mxc_w1_master_resources[] = {
 133         {
 134                 .start = OWIRE_BASE_ADDR,
 135                 .end   = OWIRE_BASE_ADDR + SZ_4K - 1,
 136                 .flags = IORESOURCE_MEM,
 137         },
 138 };
 139
 140 struct platform_device mxc_w1_master_device = {
 141         .name = "mxc_w1",
 142         .id = 0,
 143         .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
 144         .resource = mxc_w1_master_resources,
 145 };
 146
 147 static struct resource mxc_nand_resources[] = {
 148         {
 149                 .start  = NFC_BASE_ADDR,
 150                 .end    = NFC_BASE_ADDR + 0xfff,
 151                 .flags  = IORESOURCE_MEM,
 152         }, {
 153                 .start  = MXC_INT_NANDFC,
 154                 .end    = MXC_INT_NANDFC,
 155                 .flags  = IORESOURCE_IRQ,
 156         },
 157 };
 158
 159 struct platform_device mxc_nand_device = {
 160         .name = "mxc_nand",
 161         .id = 0,
 162         .num_resources = ARRAY_SIZE(mxc_nand_resources),
 163         .resource = mxc_nand_resources,
 164 };
 165
 166 /*
 167  * lcdc:
 168  * - i.MX1: the basic controller
 169  * - i.MX21: to be checked
 170  * - i.MX27: like i.MX1, with slightly variations
 171  */
 172 static struct resource mxc_fb[] = {
 173         {
 174                 .start = LCDC_BASE_ADDR,
 175                 .end   = LCDC_BASE_ADDR + 0xFFF,
 176                 .flags = IORESOURCE_MEM,
 177         }, {
 178                 .start = MXC_INT_LCDC,
 179                 .end   = MXC_INT_LCDC,
 180                 .flags = IORESOURCE_IRQ,
 181         }
 182 };
 183
 184 /* mxc lcd driver */
 185 struct platform_device mxc_fb_device = {
 186         .name = "imx-fb",
 187         .id = 0,
 188         .num_resources = ARRAY_SIZE(mxc_fb),
 189         .resource = mxc_fb,
 190         .dev = {
 191                 .coherent_dma_mask = 0xFFFFFFFF,
 192         },
 193 };
 194
 195 #ifdef CONFIG_MACH_MX27
 196 static struct resource mxc_fec_resources[] = {
 197         {
 198                 .start  = FEC_BASE_ADDR,
 199                 .end    = FEC_BASE_ADDR + 0xfff,
 200                 .flags  = IORESOURCE_MEM,
 201         }, {
 202                 .start  = MXC_INT_FEC,
 203                 .end    = MXC_INT_FEC,
 204                 .flags  = IORESOURCE_IRQ,
 205         },
 206 };
 207
 208 struct platform_device mxc_fec_device = {
 209         .name = "fec",
 210         .id = 0,
 211         .num_resources = ARRAY_SIZE(mxc_fec_resources),
 212         .resource = mxc_fec_resources,
 213 };
 214 #endif
 215
 216 static struct resource mxc_i2c_1_resources[] = {
 217         {
 218                 .start  = I2C_BASE_ADDR,
 219                 .end    = I2C_BASE_ADDR + 0x0fff,
 220                 .flags  = IORESOURCE_MEM,
 221         }, {
 222                 .start  = MXC_INT_I2C,
 223                 .end    = MXC_INT_I2C,
 224                 .flags  = IORESOURCE_IRQ,
 225         }
 226 };
 227
 228 struct platform_device mxc_i2c_device0 = {
 229         .name = "imx-i2c",
 230         .id = 0,
 231         .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
 232         .resource = mxc_i2c_1_resources,
 233 };
 234
 235 #ifdef CONFIG_MACH_MX27
 236 static struct resource mxc_i2c_2_resources[] = {
 237         {
 238                 .start  = I2C2_BASE_ADDR,
 239                 .end    = I2C2_BASE_ADDR + 0x0fff,
 240                 .flags  = IORESOURCE_MEM,
 241         }, {
 242                 .start  = MXC_INT_I2C2,
 243                 .end    = MXC_INT_I2C2,
 244                 .flags  = IORESOURCE_IRQ,
 245         }
 246 };
 247
 248 struct platform_device mxc_i2c_device1 = {
 249         .name = "imx-i2c",
 250         .id = 1,
 251         .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
 252         .resource = mxc_i2c_2_resources,
 253 };
 254 #endif
 255
 256 static struct resource mxc_pwm_resources[] = {
 257         {
 258                 .start  = PWM_BASE_ADDR,
 259                 .end    = PWM_BASE_ADDR + 0x0fff,
 260                 .flags  = IORESOURCE_MEM,
 261         }, {
 262                 .start   = MXC_INT_PWM,
 263                 .end     = MXC_INT_PWM,
 264                 .flags   = IORESOURCE_IRQ,
 265         }
 266 };
 267
 268 struct platform_device mxc_pwm_device = {
 269         .name = "mxc_pwm",
 270         .id = 0,
 271         .num_resources = ARRAY_SIZE(mxc_pwm_resources),
 272         .resource = mxc_pwm_resources,
 273 };
 274
 275 /*
 276  * Resource definition for the MXC SDHC
 277  */
 278 static struct resource mxc_sdhc1_resources[] = {
 279         {
 280                 .start = SDHC1_BASE_ADDR,
 281                 .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
 282                 .flags = IORESOURCE_MEM,
 283         }, {
 284                 .start = MXC_INT_SDHC1,
 285                 .end   = MXC_INT_SDHC1,
 286                 .flags = IORESOURCE_IRQ,
 287         }, {
 288                 .start  = DMA_REQ_SDHC1,
 289                 .end    = DMA_REQ_SDHC1,
 290                 .flags  = IORESOURCE_DMA,
 291         },
 292 };
 293
 294 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
 295
 296 struct platform_device mxc_sdhc_device0 = {
 297        .name           = "mxc-mmc",
 298        .id             = 0,
 299        .dev            = {
 300                .dma_mask = &mxc_sdhc1_dmamask,
 301                .coherent_dma_mask = 0xffffffff,
 302        },
 303        .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
 304        .resource       = mxc_sdhc1_resources,
 305 };
 306
 307 static struct resource mxc_sdhc2_resources[] = {
 308         {
 309                 .start = SDHC2_BASE_ADDR,
 310                 .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
 311                 .flags = IORESOURCE_MEM,
 312         }, {
 313                 .start = MXC_INT_SDHC2,
 314                 .end   = MXC_INT_SDHC2,
 315                 .flags = IORESOURCE_IRQ,
 316         }, {
 317                 .start  = DMA_REQ_SDHC2,
 318                 .end    = DMA_REQ_SDHC2,
 319                 .flags  = IORESOURCE_DMA,
 320         },
 321 };
 322
 323 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
 324
 325 struct platform_device mxc_sdhc_device1 = {
 326        .name           = "mxc-mmc",
 327        .id             = 1,
 328        .dev            = {
 329                .dma_mask = &mxc_sdhc2_dmamask,
 330                .coherent_dma_mask = 0xffffffff,
 331        },
 332        .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
 333        .resource       = mxc_sdhc2_resources,
 334 };
 335
 336 #ifdef CONFIG_MACH_MX27
 337 static struct resource otg_resources[] = {
 338         {
 339                 .start  = OTG_BASE_ADDR,
 340                 .end    = OTG_BASE_ADDR + 0x1ff,
 341                 .flags  = IORESOURCE_MEM,
 342         }, {
 343                 .start  = MXC_INT_USB3,
 344                 .end    = MXC_INT_USB3,
 345                 .flags  = IORESOURCE_IRQ,
 346         },
 347 };
 348
 349 static u64 otg_dmamask = 0xffffffffUL;
 350
 351 /* OTG gadget device */
 352 struct platform_device mxc_otg_udc_device = {
 353         .name           = "fsl-usb2-udc",
 354         .id             = -1,
 355         .dev            = {
 356                 .dma_mask               = &otg_dmamask,
 357                 .coherent_dma_mask      = 0xffffffffUL,
 358         },
 359         .resource       = otg_resources,
 360         .num_resources  = ARRAY_SIZE(otg_resources),
 361 };
 362
 363 /* OTG host */
 364 struct platform_device mxc_otg_host = {
 365         .name = "mxc-ehci",
 366         .id = 0,
 367         .dev = {
 368                 .coherent_dma_mask = 0xffffffff,
 369                 .dma_mask = &otg_dmamask,
 370         },
 371         .resource = otg_resources,
 372         .num_resources = ARRAY_SIZE(otg_resources),
 373 };
 374
 375 /* USB host 1 */
 376
 377 static u64 usbh1_dmamask = 0xffffffffUL;
 378
 379 static struct resource mxc_usbh1_resources[] = {
 380         {
 381                 .start = OTG_BASE_ADDR + 0x200,
 382                 .end = OTG_BASE_ADDR + 0x3ff,
 383                 .flags = IORESOURCE_MEM,
 384         }, {
 385                 .start = MXC_INT_USB1,
 386                 .end = MXC_INT_USB1,
 387                 .flags = IORESOURCE_IRQ,
 388         },
 389 };
 390
 391 struct platform_device mxc_usbh1 = {
 392         .name = "mxc-ehci",
 393         .id = 1,
 394         .dev = {
 395                 .coherent_dma_mask = 0xffffffff,
 396                 .dma_mask = &usbh1_dmamask,
 397         },
 398         .resource = mxc_usbh1_resources,
 399         .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
 400 };
 401
 402 /* USB host 2 */
 403 static u64 usbh2_dmamask = 0xffffffffUL;
 404
 405 static struct resource mxc_usbh2_resources[] = {
 406         {
 407                 .start = OTG_BASE_ADDR + 0x400,
 408                 .end = OTG_BASE_ADDR + 0x5ff,
 409                 .flags = IORESOURCE_MEM,
 410         }, {
 411                 .start = MXC_INT_USB2,
 412                 .end = MXC_INT_USB2,
 413                 .flags = IORESOURCE_IRQ,
 414         },
 415 };
 416
 417 struct platform_device mxc_usbh2 = {
 418         .name = "mxc-ehci",
 419         .id = 2,
 420         .dev = {
 421                 .coherent_dma_mask = 0xffffffff,
 422                 .dma_mask = &usbh2_dmamask,
 423         },
 424         .resource = mxc_usbh2_resources,
 425         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 426 };
 427 #endif
 428
 429 static struct resource imx_ssi_resources0[] = {
 430         {
 431                 .start  = SSI1_BASE_ADDR,
 432                 .end    = SSI1_BASE_ADDR + 0x6F,
 433                 .flags  = IORESOURCE_MEM,
 434         }, {
 435                 .start  = MXC_INT_SSI1,
 436                 .end    = MXC_INT_SSI1,
 437                 .flags  = IORESOURCE_IRQ,
 438         }, {
 439                 .name   = "tx0",
 440                 .start  = DMA_REQ_SSI1_TX0,
 441                 .end    = DMA_REQ_SSI1_TX0,
 442                 .flags  = IORESOURCE_DMA,
 443         }, {
 444                 .name   = "rx0",
 445                 .start  = DMA_REQ_SSI1_RX0,
 446                 .end    = DMA_REQ_SSI1_RX0,
 447                 .flags  = IORESOURCE_DMA,
 448         }, {
 449                 .name   = "tx1",
 450                 .start  = DMA_REQ_SSI1_TX1,
 451                 .end    = DMA_REQ_SSI1_TX1,
 452                 .flags  = IORESOURCE_DMA,
 453         }, {
 454                 .name   = "rx1",
 455                 .start  = DMA_REQ_SSI1_RX1,
 456                 .end    = DMA_REQ_SSI1_RX1,
 457                 .flags  = IORESOURCE_DMA,
 458         },
 459 };
 460
 461 static struct resource imx_ssi_resources1[] = {
 462         {
 463                 .start  = SSI2_BASE_ADDR,
 464                 .end    = SSI2_BASE_ADDR + 0x6F,
 465                 .flags  = IORESOURCE_MEM,
 466         }, {
 467                 .start  = MXC_INT_SSI2,
 468                 .end    = MXC_INT_SSI2,
 469                 .flags  = IORESOURCE_IRQ,
 470         }, {
 471                 .name   = "tx0",
 472                 .start  = DMA_REQ_SSI2_TX0,
 473                 .end    = DMA_REQ_SSI2_TX0,
 474                 .flags  = IORESOURCE_DMA,
 475         }, {
 476                 .name   = "rx0",
 477                 .start  = DMA_REQ_SSI2_RX0,
 478                 .end    = DMA_REQ_SSI2_RX0,
 479                 .flags  = IORESOURCE_DMA,
 480         }, {
 481                 .name   = "tx1",
 482                 .start  = DMA_REQ_SSI2_TX1,
 483                 .end    = DMA_REQ_SSI2_TX1,
 484                 .flags  = IORESOURCE_DMA,
 485         }, {
 486                 .name   = "rx1",
 487                 .start  = DMA_REQ_SSI2_RX1,
 488                 .end    = DMA_REQ_SSI2_RX1,
 489                 .flags  = IORESOURCE_DMA,
 490         },
 491 };
 492
 493 struct platform_device imx_ssi_device0 = {
 494         .name = "imx-ssi",
 495         .id = 0,
 496         .num_resources = ARRAY_SIZE(imx_ssi_resources0),
 497         .resource = imx_ssi_resources0,
 498 };
 499
 500 struct platform_device imx_ssi_device1 = {
 501         .name = "imx-ssi",
 502         .id = 1,
 503         .num_resources = ARRAY_SIZE(imx_ssi_resources1),
 504         .resource = imx_ssi_resources1,
 505 };
 506
 507 /* GPIO port description */
 508 static struct mxc_gpio_port imx_gpio_ports[] = {
 509         {
 510                 .chip.label = "gpio-0",
 511                 .irq = MXC_INT_GPIO,
 512                 .base = IO_ADDRESS(GPIO_BASE_ADDR),
 513                 .virtual_irq_start = MXC_GPIO_IRQ_START,
 514         }, {
 515                 .chip.label = "gpio-1",
 516                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
 517                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
 518         }, {
 519                 .chip.label = "gpio-2",
 520                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
 521                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
 522         }, {
 523                 .chip.label = "gpio-3",
 524                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
 525                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
 526         }, {
 527                 .chip.label = "gpio-4",
 528                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
 529                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
 530         }, {
 531                 .chip.label = "gpio-5",
 532                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
 533                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
 534         }
 535 };
 536
 537 int __init mxc_register_gpios(void)
 538 {
 539         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 540 }