SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/slab.h>
  17 #include <linux/string.h>
  18 #include <linux/sysdev.h>
  19
  20 #include <asm/hardware.h>
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/setup.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/hardware/amba.h>
  26 #include <asm/hardware/amba_kmi.h>
  27 #include <asm/hardware/amba_clcd.h>
  28 #include <asm/hardware/icst525.h>
  29
  30 #include <asm/arch/cm.h>
  31 #include <asm/arch/lm.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/flash.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach/mmc.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/time.h>
  39
  40 #include "common.h"
  41 #include "clock.h"
  42
  43 #define INTCP_PA_MMC_BASE               0x1c000000
  44 #define INTCP_PA_AACI_BASE              0x1d000000
  45
  46 #define INTCP_PA_FLASH_BASE             0x24000000
  47 #define INTCP_FLASH_SIZE                SZ_32M
  48
  49 #define INTCP_PA_CLCD_BASE              0xc0000000
  50
  51 #define INTCP_VA_CIC_BASE               0xf1000040
  52 #define INTCP_VA_PIC_BASE               0xf1400000
  53 #define INTCP_VA_SIC_BASE               0xfca00000
  54
  55 #define INTCP_PA_ETH_BASE               0xc8000000
  56 #define INTCP_ETH_SIZE                  0x10
  57
  58 #define INTCP_VA_CTRL_BASE              0xfcb00000
  59 #define INTCP_FLASHPROG                 0x04
  60 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  61 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  62
  63 /*
  64  * Logical      Physical
  65  * f1000000     10000000        Core module registers
  66  * f1100000     11000000        System controller registers
  67  * f1200000     12000000        EBI registers
  68  * f1300000     13000000        Counter/Timer
  69  * f1400000     14000000        Interrupt controller
  70  * f1600000     16000000        UART 0
  71  * f1700000     17000000        UART 1
  72  * f1a00000     1a000000        Debug LEDs
  73  * f1b00000     1b000000        GPIO
  74  */
  75
  76 static struct map_desc intcp_io_desc[] __initdata = {
  77  { IO_ADDRESS(INTEGRATOR_HDR_BASE),   INTEGRATOR_HDR_BASE,   SZ_4K,  MT_DEVICE },
  78  { IO_ADDRESS(INTEGRATOR_SC_BASE),    INTEGRATOR_SC_BASE,    SZ_4K,  MT_DEVICE },
  79  { IO_ADDRESS(INTEGRATOR_EBI_BASE),   INTEGRATOR_EBI_BASE,   SZ_4K,  MT_DEVICE },
  80  { IO_ADDRESS(INTEGRATOR_CT_BASE),    INTEGRATOR_CT_BASE,    SZ_4K,  MT_DEVICE },
  81  { IO_ADDRESS(INTEGRATOR_IC_BASE),    INTEGRATOR_IC_BASE,    SZ_4K,  MT_DEVICE },
  82  { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K,  MT_DEVICE },
  83  { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K,  MT_DEVICE },
  84  { IO_ADDRESS(INTEGRATOR_DBG_BASE),   INTEGRATOR_DBG_BASE,   SZ_4K,  MT_DEVICE },
  85  { IO_ADDRESS(INTEGRATOR_GPIO_BASE),  INTEGRATOR_GPIO_BASE,  SZ_4K,  MT_DEVICE },
  86  { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
  87  { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
  88 };
  89
  90 static void __init intcp_map_io(void)
  91 {
  92         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
  93 }
  94
  95 #define cic_writel      __raw_writel
  96 #define cic_readl       __raw_readl
  97 #define pic_writel      __raw_writel
  98 #define pic_readl       __raw_readl
  99 #define sic_writel      __raw_writel
 100 #define sic_readl       __raw_readl
 101
 102 static void cic_mask_irq(unsigned int irq)
 103 {
 104         irq -= IRQ_CIC_START;
 105         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 106 }
 107
 108 static void cic_unmask_irq(unsigned int irq)
 109 {
 110         irq -= IRQ_CIC_START;
 111         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 112 }
 113
 114 static struct irqchip cic_chip = {
 115         .ack    = cic_mask_irq,
 116         .mask   = cic_mask_irq,
 117         .unmask = cic_unmask_irq,
 118 };
 119
 120 static void pic_mask_irq(unsigned int irq)
 121 {
 122         irq -= IRQ_PIC_START;
 123         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 124 }
 125
 126 static void pic_unmask_irq(unsigned int irq)
 127 {
 128         irq -= IRQ_PIC_START;
 129         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 130 }
 131
 132 static struct irqchip pic_chip = {
 133         .ack    = pic_mask_irq,
 134         .mask   = pic_mask_irq,
 135         .unmask = pic_unmask_irq,
 136 };
 137
 138 static void sic_mask_irq(unsigned int irq)
 139 {
 140         irq -= IRQ_SIC_START;
 141         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 142 }
 143
 144 static void sic_unmask_irq(unsigned int irq)
 145 {
 146         irq -= IRQ_SIC_START;
 147         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 148 }
 149
 150 static struct irqchip sic_chip = {
 151         .ack    = sic_mask_irq,
 152         .mask   = sic_mask_irq,
 153         .unmask = sic_unmask_irq,
 154 };
 155
 156 static void
 157 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
 158 {
 159         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 160
 161         if (status == 0) {
 162                 do_bad_IRQ(irq, desc, regs);
 163                 return;
 164         }
 165
 166         do {
 167                 irq = ffs(status) - 1;
 168                 status &= ~(1 << irq);
 169
 170                 irq += IRQ_SIC_START;
 171
 172                 desc = irq_desc + irq;
 173                 desc->handle(irq, desc, regs);
 174         } while (status);
 175 }
 176
 177 static void __init intcp_init_irq(void)
 178 {
 179         unsigned int i;
 180
 181         /*
 182          * Disable all interrupt sources
 183          */
 184         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 185         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 186
 187         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
 188                 if (i == 11)
 189                         i = 22;
 190                 if (i == IRQ_CP_CPPLDINT)
 191                         i++;
 192                 if (i == 29)
 193                         break;
 194                 set_irq_chip(i, &pic_chip);
 195                 set_irq_handler(i, do_level_IRQ);
 196                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 197         }
 198
 199         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 200         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 201
 202         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
 203                 set_irq_chip(i, &cic_chip);
 204                 set_irq_handler(i, do_level_IRQ);
 205                 set_irq_flags(i, IRQF_VALID);
 206         }
 207
 208         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 209         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 210
 211         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 212                 set_irq_chip(i, &sic_chip);
 213                 set_irq_handler(i, do_level_IRQ);
 214                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 215         }
 216
 217         set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 218         pic_unmask_irq(IRQ_CP_CPPLDINT);
 219 }
 220
 221 /*
 222  * Clock handling
 223  */
 224 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
 225 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
 226
 227 static const struct icst525_params cp_auxvco_params = {
 228         .ref            = 24000,
 229         .vco_max        = 320000,
 230         .vd_min         = 8,
 231         .vd_max         = 263,
 232         .rd_min         = 3,
 233         .rd_max         = 65,
 234 };
 235
 236 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
 237 {
 238         u32 val;
 239
 240         val = readl(CM_AUXOSC) & ~0x7ffff;
 241         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 242
 243         writel(0xa05f, CM_LOCK);
 244         writel(val, CM_AUXOSC);
 245         writel(0, CM_LOCK);
 246 }
 247
 248 static struct clk cp_clcd_clk = {
 249         .name   = "CLCDCLK",
 250         .params = &cp_auxvco_params,
 251         .setvco = cp_auxvco_set,
 252 };
 253
 254 static struct clk cp_mmci_clk = {
 255         .name   = "MCLK",
 256         .rate   = 14745600,
 257 };
 258
 259 /*
 260  * Flash handling.
 261  */
 262 static int intcp_flash_init(void)
 263 {
 264         u32 val;
 265
 266         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 267         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 268         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 269
 270         return 0;
 271 }
 272
 273 static void intcp_flash_exit(void)
 274 {
 275         u32 val;
 276
 277         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 278         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 279         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 280 }
 281
 282 static void intcp_flash_set_vpp(int on)
 283 {
 284         u32 val;
 285
 286         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 287         if (on)
 288                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 289         else
 290                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 291         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 292 }
 293
 294 static struct flash_platform_data intcp_flash_data = {
 295         .map_name       = "cfi_probe",
 296         .width          = 4,
 297         .init           = intcp_flash_init,
 298         .exit           = intcp_flash_exit,
 299         .set_vpp        = intcp_flash_set_vpp,
 300 };
 301
 302 static struct resource intcp_flash_resource = {
 303         .start          = INTCP_PA_FLASH_BASE,
 304         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 305         .flags          = IORESOURCE_MEM,
 306 };
 307
 308 static struct platform_device intcp_flash_device = {
 309         .name           = "armflash",
 310         .id             = 0,
 311         .dev            = {
 312                 .platform_data  = &intcp_flash_data,
 313         },
 314         .num_resources  = 1,
 315         .resource       = &intcp_flash_resource,
 316 };
 317
 318 static struct resource smc91x_resources[] = {
 319         [0] = {
 320                 .start  = INTCP_PA_ETH_BASE,
 321                 .end    = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324         [1] = {
 325                 .start  = IRQ_CP_ETHINT,
 326                 .end    = IRQ_CP_ETHINT,
 327                 .flags  = IORESOURCE_IRQ,
 328         },
 329 };
 330
 331 static struct platform_device smc91x_device = {
 332         .name           = "smc91x",
 333         .id             = 0,
 334         .num_resources  = ARRAY_SIZE(smc91x_resources),
 335         .resource       = smc91x_resources,
 336 };
 337
 338 static struct platform_device *intcp_devs[] __initdata = {
 339         &intcp_flash_device,
 340         &smc91x_device,
 341 };
 342
 343 /*
 344  * It seems that the card insertion interrupt remains active after
 345  * we've acknowledged it.  We therefore ignore the interrupt, and
 346  * rely on reading it from the SIC.  This also means that we must
 347  * clear the latched interrupt.
 348  */
 349 static unsigned int mmc_status(struct device *dev)
 350 {
 351         unsigned int status = readl(0xfca00004);
 352         writel(8, 0xfcb00008);
 353
 354         return status & 8;
 355 }
 356
 357 static struct mmc_platform_data mmc_data = {
 358         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 359         .status         = mmc_status,
 360 };
 361
 362 static struct amba_device mmc_device = {
 363         .dev            = {
 364                 .bus_id = "mb:1c",
 365                 .platform_data = &mmc_data,
 366         },
 367         .res            = {
 368                 .start  = INTCP_PA_MMC_BASE,
 369                 .end    = INTCP_PA_MMC_BASE + SZ_4K - 1,
 370                 .flags  = IORESOURCE_MEM,
 371         },
 372         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
 373         .periphid       = 0,
 374 };
 375
 376 static struct amba_device aaci_device = {
 377         .dev            = {
 378                 .bus_id = "mb:1d",
 379         },
 380         .res            = {
 381                 .start  = INTCP_PA_AACI_BASE,
 382                 .end    = INTCP_PA_AACI_BASE + SZ_4K - 1,
 383                 .flags  = IORESOURCE_MEM,
 384         },
 385         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
 386         .periphid       = 0,
 387 };
 388
 389
 390 /*
 391  * CLCD support
 392  */
 393 static struct clcd_panel vga = {
 394         .mode           = {
 395                 .name           = "VGA",
 396                 .refresh        = 60,
 397                 .xres           = 640,
 398                 .yres           = 480,
 399                 .pixclock       = 39721,
 400                 .left_margin    = 40,
 401                 .right_margin   = 24,
 402                 .upper_margin   = 32,
 403                 .lower_margin   = 11,
 404                 .hsync_len      = 96,
 405                 .vsync_len      = 2,
 406                 .sync           = 0,
 407                 .vmode          = FB_VMODE_NONINTERLACED,
 408         },
 409         .width          = -1,
 410         .height         = -1,
 411         .tim2           = TIM2_BCD | TIM2_IPC,
 412         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 413         .bpp            = 16,
 414         .grayscale      = 0,
 415 };
 416
 417 /*
 418  * Ensure VGA is selected.
 419  */
 420 static void cp_clcd_enable(struct clcd_fb *fb)
 421 {
 422         u32 val;
 423
 424         if (fb->fb.var.bits_per_pixel <= 8)
 425                 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
 426         else if (fb->fb.var.bits_per_pixel <= 16)
 427                 val = CM_CTRL_LCDMUXSEL_VGA_16BPP;
 428         else
 429                 val = 0; /* no idea for this, don't trust the docs */
 430
 431         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 432                    CM_CTRL_LCDEN0|
 433                    CM_CTRL_LCDEN1|
 434                    CM_CTRL_STATIC1|
 435                    CM_CTRL_STATIC2|
 436                    CM_CTRL_STATIC|
 437                    CM_CTRL_n24BITEN, val);
 438 }
 439
 440 static unsigned long framesize = SZ_1M;
 441
 442 static int cp_clcd_setup(struct clcd_fb *fb)
 443 {
 444         dma_addr_t dma;
 445
 446         fb->panel = &vga;
 447
 448         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 449                                                     &dma, GFP_KERNEL);
 450         if (!fb->fb.screen_base) {
 451                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 452                 return -ENOMEM;
 453         }
 454
 455         fb->fb.fix.smem_start   = dma;
 456         fb->fb.fix.smem_len     = framesize;
 457
 458         return 0;
 459 }
 460
 461 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 462 {
 463         return dma_mmap_writecombine(&fb->dev->dev, vma,
 464                                      fb->fb.screen_base,
 465                                      fb->fb.fix.smem_start,
 466                                      fb->fb.fix.smem_len);
 467 }
 468
 469 static void cp_clcd_remove(struct clcd_fb *fb)
 470 {
 471         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 472                               fb->fb.screen_base, fb->fb.fix.smem_start);
 473 }
 474
 475 static struct clcd_board clcd_data = {
 476         .name           = "Integrator/CP",
 477         .check          = clcdfb_check,
 478         .decode         = clcdfb_decode,
 479         .enable         = cp_clcd_enable,
 480         .setup          = cp_clcd_setup,
 481         .mmap           = cp_clcd_mmap,
 482         .remove         = cp_clcd_remove,
 483 };
 484
 485 static struct amba_device clcd_device = {
 486         .dev            = {
 487                 .bus_id = "mb:c0",
 488                 .coherent_dma_mask = ~0,
 489                 .platform_data = &clcd_data,
 490         },
 491         .res            = {
 492                 .start  = INTCP_PA_CLCD_BASE,
 493                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
 494                 .flags  = IORESOURCE_MEM,
 495         },
 496         .dma_mask       = ~0,
 497         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
 498         .periphid       = 0,
 499 };
 500
 501 static struct amba_device *amba_devs[] __initdata = {
 502         &mmc_device,
 503         &aaci_device,
 504         &clcd_device,
 505 };
 506
 507 static void __init intcp_init(void)
 508 {
 509         int i;
 510
 511         clk_register(&cp_clcd_clk);
 512         clk_register(&cp_mmci_clk);
 513
 514         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 515
 516         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 517                 struct amba_device *d = amba_devs[i];
 518                 amba_device_register(d, &iomem_resource);
 519         }
 520 }
 521
 522 #define TIMER_CTRL_IE   (1 << 5)                        /* Interrupt Enable */
 523
 524 static void __init intcp_timer_init(void)
 525 {
 526         integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
 527 }
 528
 529 static struct sys_timer cp_timer = {
 530         .init           = intcp_timer_init,
 531         .offset         = integrator_gettimeoffset,
 532 };
 533
 534 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 535         MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
 536         BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
 537         BOOT_PARAMS(0x00000100)
 538         MAPIO(intcp_map_io)
 539         INITIRQ(intcp_init_irq)
 540         .timer          = &cp_timer,
 541         INIT_MACHINE(intcp_init)
 542 MACHINE_END