SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/slab.h>
  17 #include <linux/string.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/amba/bus.h>
  20 #include <linux/amba/kmi.h>
  21 #include <linux/amba/clcd.h>
  22 #include <linux/amba/mmci.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/clkdev.h>
  26 #include <mach/clkdev.h>
  27 #include <mach/hardware.h>
  28 #include <mach/platform.h>
  29 #include <asm/irq.h>
  30 #include <asm/setup.h>
  31 #include <asm/mach-types.h>
  32 #include <asm/hardware/arm_timer.h>
  33 #include <asm/hardware/icst.h>
  34
  35 #include <mach/cm.h>
  36 #include <mach/lm.h>
  37
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/flash.h>
  40 #include <asm/mach/irq.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach/time.h>
  43
  44 #include <plat/timer-sp.h>
  45
  46 #include "common.h"
  47
  48 #define INTCP_PA_FLASH_BASE             0x24000000
  49 #define INTCP_FLASH_SIZE                SZ_32M
  50
  51 #define INTCP_PA_CLCD_BASE              0xc0000000
  52
  53 #define INTCP_VA_CIC_BASE               IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
  54 #define INTCP_VA_PIC_BASE               IO_ADDRESS(INTEGRATOR_IC_BASE)
  55 #define INTCP_VA_SIC_BASE               IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
  56
  57 #define INTCP_ETH_SIZE                  0x10
  58
  59 #define INTCP_VA_CTRL_BASE              IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
  60 #define INTCP_FLASHPROG                 0x04
  61 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  62 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  63
  64 /*
  65  * Logical      Physical
  66  * f1000000     10000000        Core module registers
  67  * f1100000     11000000        System controller registers
  68  * f1200000     12000000        EBI registers
  69  * f1300000     13000000        Counter/Timer
  70  * f1400000     14000000        Interrupt controller
  71  * f1600000     16000000        UART 0
  72  * f1700000     17000000        UART 1
  73  * f1a00000     1a000000        Debug LEDs
  74  * fc900000     c9000000        GPIO
  75  * fca00000     ca000000        SIC
  76  * fcb00000     cb000000        CP system control
  77  */
  78
  79 static struct map_desc intcp_io_desc[] __initdata = {
  80         {
  81                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  82                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  83                 .length         = SZ_4K,
  84                 .type           = MT_DEVICE
  85         }, {
  86                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  87                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  88                 .length         = SZ_4K,
  89                 .type           = MT_DEVICE
  90         }, {
  91                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  92                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  93                 .length         = SZ_4K,
  94                 .type           = MT_DEVICE
  95         }, {
  96                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  97                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
  98                 .length         = SZ_4K,
  99                 .type           = MT_DEVICE
 100         }, {
 101                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 102                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 103                 .length         = SZ_4K,
 104                 .type           = MT_DEVICE
 105         }, {
 106                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 107                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 108                 .length         = SZ_4K,
 109                 .type           = MT_DEVICE
 110         }, {
 111                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 112                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 113                 .length         = SZ_4K,
 114                 .type           = MT_DEVICE
 115         }, {
 116                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 117                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE
 120         }, {
 121                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
 122                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
 123                 .length         = SZ_4K,
 124                 .type           = MT_DEVICE
 125         }, {
 126                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
 127                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE
 130         }, {
 131                 .virtual        = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
 132                 .pfn            = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
 133                 .length         = SZ_4K,
 134                 .type           = MT_DEVICE
 135         }
 136 };
 137
 138 static void __init intcp_map_io(void)
 139 {
 140         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 141 }
 142
 143 #define cic_writel      __raw_writel
 144 #define cic_readl       __raw_readl
 145 #define pic_writel      __raw_writel
 146 #define pic_readl       __raw_readl
 147 #define sic_writel      __raw_writel
 148 #define sic_readl       __raw_readl
 149
 150 static void cic_mask_irq(unsigned int irq)
 151 {
 152         irq -= IRQ_CIC_START;
 153         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 154 }
 155
 156 static void cic_unmask_irq(unsigned int irq)
 157 {
 158         irq -= IRQ_CIC_START;
 159         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 160 }
 161
 162 static struct irq_chip cic_chip = {
 163         .name   = "CIC",
 164         .ack    = cic_mask_irq,
 165         .mask   = cic_mask_irq,
 166         .unmask = cic_unmask_irq,
 167 };
 168
 169 static void pic_mask_irq(unsigned int irq)
 170 {
 171         irq -= IRQ_PIC_START;
 172         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 173 }
 174
 175 static void pic_unmask_irq(unsigned int irq)
 176 {
 177         irq -= IRQ_PIC_START;
 178         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 179 }
 180
 181 static struct irq_chip pic_chip = {
 182         .name   = "PIC",
 183         .ack    = pic_mask_irq,
 184         .mask   = pic_mask_irq,
 185         .unmask = pic_unmask_irq,
 186 };
 187
 188 static void sic_mask_irq(unsigned int irq)
 189 {
 190         irq -= IRQ_SIC_START;
 191         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 192 }
 193
 194 static void sic_unmask_irq(unsigned int irq)
 195 {
 196         irq -= IRQ_SIC_START;
 197         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 198 }
 199
 200 static struct irq_chip sic_chip = {
 201         .name   = "SIC",
 202         .ack    = sic_mask_irq,
 203         .mask   = sic_mask_irq,
 204         .unmask = sic_unmask_irq,
 205 };
 206
 207 static void
 208 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
 209 {
 210         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 211
 212         if (status == 0) {
 213                 do_bad_IRQ(irq, desc);
 214                 return;
 215         }
 216
 217         do {
 218                 irq = ffs(status) - 1;
 219                 status &= ~(1 << irq);
 220
 221                 irq += IRQ_SIC_START;
 222
 223                 generic_handle_irq(irq);
 224         } while (status);
 225 }
 226
 227 static void __init intcp_init_irq(void)
 228 {
 229         unsigned int i;
 230
 231         /*
 232          * Disable all interrupt sources
 233          */
 234         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 235         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 236
 237         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
 238                 if (i == 11)
 239                         i = 22;
 240                 if (i == 29)
 241                         break;
 242                 set_irq_chip(i, &pic_chip);
 243                 set_irq_handler(i, handle_level_irq);
 244                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 245         }
 246
 247         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 248         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 249
 250         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
 251                 set_irq_chip(i, &cic_chip);
 252                 set_irq_handler(i, handle_level_irq);
 253                 set_irq_flags(i, IRQF_VALID);
 254         }
 255
 256         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 257         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 258
 259         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 260                 set_irq_chip(i, &sic_chip);
 261                 set_irq_handler(i, handle_level_irq);
 262                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 263         }
 264
 265         set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 266 }
 267
 268 /*
 269  * Clock handling
 270  */
 271 #define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
 272 #define CM_AUXOSC IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x1c)
 273
 274 static const struct icst_params cp_auxvco_params = {
 275         .ref            = 24000000,
 276         .vco_max        = ICST525_VCO_MAX_5V,
 277         .vco_min        = ICST525_VCO_MIN,
 278         .vd_min         = 8,
 279         .vd_max         = 263,
 280         .rd_min         = 3,
 281         .rd_max         = 65,
 282         .s2div          = icst525_s2div,
 283         .idx2s          = icst525_idx2s,
 284 };
 285
 286 static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
 287 {
 288         u32 val;
 289
 290         val = readl(CM_AUXOSC) & ~0x7ffff;
 291         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 292
 293         writel(0xa05f, CM_LOCK);
 294         writel(val, CM_AUXOSC);
 295         writel(0, CM_LOCK);
 296 }
 297
 298 static struct clk cp_auxclk = {
 299         .params = &cp_auxvco_params,
 300         .setvco = cp_auxvco_set,
 301 };
 302
 303 static struct clk_lookup cp_lookups[] = {
 304         {       /* CLCD */
 305                 .dev_id         = "mb:c0",
 306                 .clk            = &cp_auxclk,
 307         },
 308 };
 309
 310 /*
 311  * Flash handling.
 312  */
 313 static int intcp_flash_init(void)
 314 {
 315         u32 val;
 316
 317         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 318         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 319         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 320
 321         return 0;
 322 }
 323
 324 static void intcp_flash_exit(void)
 325 {
 326         u32 val;
 327
 328         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 329         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 330         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 331 }
 332
 333 static void intcp_flash_set_vpp(int on)
 334 {
 335         u32 val;
 336
 337         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 338         if (on)
 339                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 340         else
 341                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 342         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 343 }
 344
 345 static struct flash_platform_data intcp_flash_data = {
 346         .map_name       = "cfi_probe",
 347         .width          = 4,
 348         .init           = intcp_flash_init,
 349         .exit           = intcp_flash_exit,
 350         .set_vpp        = intcp_flash_set_vpp,
 351 };
 352
 353 static struct resource intcp_flash_resource = {
 354         .start          = INTCP_PA_FLASH_BASE,
 355         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 356         .flags          = IORESOURCE_MEM,
 357 };
 358
 359 static struct platform_device intcp_flash_device = {
 360         .name           = "armflash",
 361         .id             = 0,
 362         .dev            = {
 363                 .platform_data  = &intcp_flash_data,
 364         },
 365         .num_resources  = 1,
 366         .resource       = &intcp_flash_resource,
 367 };
 368
 369 static struct resource smc91x_resources[] = {
 370         [0] = {
 371                 .start  = INTEGRATOR_CP_ETH_BASE,
 372                 .end    = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
 373                 .flags  = IORESOURCE_MEM,
 374         },
 375         [1] = {
 376                 .start  = IRQ_CP_ETHINT,
 377                 .end    = IRQ_CP_ETHINT,
 378                 .flags  = IORESOURCE_IRQ,
 379         },
 380 };
 381
 382 static struct platform_device smc91x_device = {
 383         .name           = "smc91x",
 384         .id             = 0,
 385         .num_resources  = ARRAY_SIZE(smc91x_resources),
 386         .resource       = smc91x_resources,
 387 };
 388
 389 static struct platform_device *intcp_devs[] __initdata = {
 390         &intcp_flash_device,
 391         &smc91x_device,
 392 };
 393
 394 /*
 395  * It seems that the card insertion interrupt remains active after
 396  * we've acknowledged it.  We therefore ignore the interrupt, and
 397  * rely on reading it from the SIC.  This also means that we must
 398  * clear the latched interrupt.
 399  */
 400 static unsigned int mmc_status(struct device *dev)
 401 {
 402         unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
 403         writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
 404
 405         return status & 8;
 406 }
 407
 408 static struct mmci_platform_data mmc_data = {
 409         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 410         .status         = mmc_status,
 411         .gpio_wp        = -1,
 412         .gpio_cd        = -1,
 413 };
 414
 415 static struct amba_device mmc_device = {
 416         .dev            = {
 417                 .init_name = "mb:1c",
 418                 .platform_data = &mmc_data,
 419         },
 420         .res            = {
 421                 .start  = INTEGRATOR_CP_MMC_BASE,
 422                 .end    = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
 423                 .flags  = IORESOURCE_MEM,
 424         },
 425         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
 426         .periphid       = 0,
 427 };
 428
 429 static struct amba_device aaci_device = {
 430         .dev            = {
 431                 .init_name = "mb:1d",
 432         },
 433         .res            = {
 434                 .start  = INTEGRATOR_CP_AACI_BASE,
 435                 .end    = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
 436                 .flags  = IORESOURCE_MEM,
 437         },
 438         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
 439         .periphid       = 0,
 440 };
 441
 442
 443 /*
 444  * CLCD support
 445  */
 446 static struct clcd_panel vga = {
 447         .mode           = {
 448                 .name           = "VGA",
 449                 .refresh        = 60,
 450                 .xres           = 640,
 451                 .yres           = 480,
 452                 .pixclock       = 39721,
 453                 .left_margin    = 40,
 454                 .right_margin   = 24,
 455                 .upper_margin   = 32,
 456                 .lower_margin   = 11,
 457                 .hsync_len      = 96,
 458                 .vsync_len      = 2,
 459                 .sync           = 0,
 460                 .vmode          = FB_VMODE_NONINTERLACED,
 461         },
 462         .width          = -1,
 463         .height         = -1,
 464         .tim2           = TIM2_BCD | TIM2_IPC,
 465         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 466         .bpp            = 16,
 467         .grayscale      = 0,
 468 };
 469
 470 /*
 471  * Ensure VGA is selected.
 472  */
 473 static void cp_clcd_enable(struct clcd_fb *fb)
 474 {
 475         u32 val;
 476
 477         if (fb->fb.var.bits_per_pixel <= 8)
 478                 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
 479         else if (fb->fb.var.bits_per_pixel <= 16)
 480                 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
 481                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
 482                         | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
 483         else
 484                 val = 0; /* no idea for this, don't trust the docs */
 485
 486         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 487                    CM_CTRL_LCDEN0|
 488                    CM_CTRL_LCDEN1|
 489                    CM_CTRL_STATIC1|
 490                    CM_CTRL_STATIC2|
 491                    CM_CTRL_STATIC|
 492                    CM_CTRL_n24BITEN, val);
 493 }
 494
 495 static unsigned long framesize = SZ_1M;
 496
 497 static int cp_clcd_setup(struct clcd_fb *fb)
 498 {
 499         dma_addr_t dma;
 500
 501         fb->panel = &vga;
 502
 503         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 504                                                     &dma, GFP_KERNEL);
 505         if (!fb->fb.screen_base) {
 506                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 507                 return -ENOMEM;
 508         }
 509
 510         fb->fb.fix.smem_start   = dma;
 511         fb->fb.fix.smem_len     = framesize;
 512
 513         return 0;
 514 }
 515
 516 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 517 {
 518         return dma_mmap_writecombine(&fb->dev->dev, vma,
 519                                      fb->fb.screen_base,
 520                                      fb->fb.fix.smem_start,
 521                                      fb->fb.fix.smem_len);
 522 }
 523
 524 static void cp_clcd_remove(struct clcd_fb *fb)
 525 {
 526         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 527                               fb->fb.screen_base, fb->fb.fix.smem_start);
 528 }
 529
 530 static struct clcd_board clcd_data = {
 531         .name           = "Integrator/CP",
 532         .check          = clcdfb_check,
 533         .decode         = clcdfb_decode,
 534         .enable         = cp_clcd_enable,
 535         .setup          = cp_clcd_setup,
 536         .mmap           = cp_clcd_mmap,
 537         .remove         = cp_clcd_remove,
 538 };
 539
 540 static struct amba_device clcd_device = {
 541         .dev            = {
 542                 .init_name = "mb:c0",
 543                 .coherent_dma_mask = ~0,
 544                 .platform_data = &clcd_data,
 545         },
 546         .res            = {
 547                 .start  = INTCP_PA_CLCD_BASE,
 548                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
 549                 .flags  = IORESOURCE_MEM,
 550         },
 551         .dma_mask       = ~0,
 552         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
 553         .periphid       = 0,
 554 };
 555
 556 static struct amba_device *amba_devs[] __initdata = {
 557         &mmc_device,
 558         &aaci_device,
 559         &clcd_device,
 560 };
 561
 562 static void __init intcp_init(void)
 563 {
 564         int i;
 565
 566         clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
 567         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 568
 569         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 570                 struct amba_device *d = amba_devs[i];
 571                 amba_device_register(d, &iomem_resource);
 572         }
 573 }
 574
 575 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
 576 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
 577 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 578
 579 static void __init intcp_timer_init(void)
 580 {
 581         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 582         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 583         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 584
 585         sp804_clocksource_init(TIMER2_VA_BASE);
 586         sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
 587 }
 588
 589 static struct sys_timer cp_timer = {
 590         .init           = intcp_timer_init,
 591 };
 592
 593 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 594         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 595         .phys_io        = 0x16000000,
 596         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
 597         .boot_params    = 0x00000100,
 598         .map_io         = intcp_map_io,
 599         .init_irq       = intcp_init_irq,
 600         .timer          = &cp_timer,
 601         .init_machine   = intcp_init,
 602 MACHINE_END