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   1 /*
   2  *  linux/arch/arm/mach-integrator/core.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/termios.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/clkdev.h>
  26 #include <mach/clkdev.h>
  27 #include <mach/hardware.h>
  28 #include <mach/platform.h>
  29 #include <asm/irq.h>
  30 #include <asm/hardware/arm_timer.h>
  31 #include <mach/cm.h>
  32 #include <asm/system.h>
  33 #include <asm/leds.h>
  34 #include <asm/mach/time.h>
  35
  36 #include "common.h"
  37
  38 static struct amba_pl010_data integrator_uart_data;
  39
  40 static struct amba_device rtc_device = {
  41         .dev            = {
  42                 .init_name = "mb:15",
  43         },
  44         .res            = {
  45                 .start  = INTEGRATOR_RTC_BASE,
  46                 .end    = INTEGRATOR_RTC_BASE + SZ_4K - 1,
  47                 .flags  = IORESOURCE_MEM,
  48         },
  49         .irq            = { IRQ_RTCINT, NO_IRQ },
  50         .periphid       = 0x00041030,
  51 };
  52
  53 static struct amba_device uart0_device = {
  54         .dev            = {
  55                 .init_name = "mb:16",
  56                 .platform_data = &integrator_uart_data,
  57         },
  58         .res            = {
  59                 .start  = INTEGRATOR_UART0_BASE,
  60                 .end    = INTEGRATOR_UART0_BASE + SZ_4K - 1,
  61                 .flags  = IORESOURCE_MEM,
  62         },
  63         .irq            = { IRQ_UARTINT0, NO_IRQ },
  64         .periphid       = 0x0041010,
  65 };
  66
  67 static struct amba_device uart1_device = {
  68         .dev            = {
  69                 .init_name = "mb:17",
  70                 .platform_data = &integrator_uart_data,
  71         },
  72         .res            = {
  73                 .start  = INTEGRATOR_UART1_BASE,
  74                 .end    = INTEGRATOR_UART1_BASE + SZ_4K - 1,
  75                 .flags  = IORESOURCE_MEM,
  76         },
  77         .irq            = { IRQ_UARTINT1, NO_IRQ },
  78         .periphid       = 0x0041010,
  79 };
  80
  81 static struct amba_device kmi0_device = {
  82         .dev            = {
  83                 .init_name = "mb:18",
  84         },
  85         .res            = {
  86                 .start  = KMI0_BASE,
  87                 .end    = KMI0_BASE + SZ_4K - 1,
  88                 .flags  = IORESOURCE_MEM,
  89         },
  90         .irq            = { IRQ_KMIINT0, NO_IRQ },
  91         .periphid       = 0x00041050,
  92 };
  93
  94 static struct amba_device kmi1_device = {
  95         .dev            = {
  96                 .init_name = "mb:19",
  97         },
  98         .res            = {
  99                 .start  = KMI1_BASE,
 100                 .end    = KMI1_BASE + SZ_4K - 1,
 101                 .flags  = IORESOURCE_MEM,
 102         },
 103         .irq            = { IRQ_KMIINT1, NO_IRQ },
 104         .periphid       = 0x00041050,
 105 };
 106
 107 static struct amba_device *amba_devs[] __initdata = {
 108         &rtc_device,
 109         &uart0_device,
 110         &uart1_device,
 111         &kmi0_device,
 112         &kmi1_device,
 113 };
 114
 115 /*
 116  * These are fixed clocks.
 117  */
 118 static struct clk clk24mhz = {
 119         .rate   = 24000000,
 120 };
 121
 122 static struct clk uartclk = {
 123         .rate   = 14745600,
 124 };
 125
 126 static struct clk_lookup lookups[] = {
 127         {       /* UART0 */
 128                 .dev_id         = "mb:16",
 129                 .clk            = &uartclk,
 130         }, {    /* UART1 */
 131                 .dev_id         = "mb:17",
 132                 .clk            = &uartclk,
 133         }, {    /* KMI0 */
 134                 .dev_id         = "mb:18",
 135                 .clk            = &clk24mhz,
 136         }, {    /* KMI1 */
 137                 .dev_id         = "mb:19",
 138                 .clk            = &clk24mhz,
 139         }, {    /* MMCI - IntegratorCP */
 140                 .dev_id         = "mb:1c",
 141                 .clk            = &uartclk,
 142         }
 143 };
 144
 145 static int __init integrator_init(void)
 146 {
 147         int i;
 148
 149         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 150
 151         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 152                 struct amba_device *d = amba_devs[i];
 153                 amba_device_register(d, &iomem_resource);
 154         }
 155
 156         return 0;
 157 }
 158
 159 arch_initcall(integrator_init);
 160
 161 /*
 162  * On the Integrator platform, the port RTS and DTR are provided by
 163  * bits in the following SC_CTRLS register bits:
 164  *        RTS  DTR
 165  *  UART0  7    6
 166  *  UART1  5    4
 167  */
 168 #define SC_CTRLC        (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
 169 #define SC_CTRLS        (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
 170
 171 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 172 {
 173         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 174
 175         if (dev == &uart0_device) {
 176                 rts_mask = 1 << 4;
 177                 dtr_mask = 1 << 5;
 178         } else {
 179                 rts_mask = 1 << 6;
 180                 dtr_mask = 1 << 7;
 181         }
 182
 183         if (mctrl & TIOCM_RTS)
 184                 ctrlc |= rts_mask;
 185         else
 186                 ctrls |= rts_mask;
 187
 188         if (mctrl & TIOCM_DTR)
 189                 ctrlc |= dtr_mask;
 190         else
 191                 ctrls |= dtr_mask;
 192
 193         __raw_writel(ctrls, SC_CTRLS);
 194         __raw_writel(ctrlc, SC_CTRLC);
 195 }
 196
 197 static struct amba_pl010_data integrator_uart_data = {
 198         .set_mctrl = integrator_uart_set_mctrl,
 199 };
 200
 201 #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET
 202
 203 static DEFINE_SPINLOCK(cm_lock);
 204
 205 /**
 206  * cm_control - update the CM_CTRL register.
 207  * @mask: bits to change
 208  * @set: bits to set
 209  */
 210 void cm_control(u32 mask, u32 set)
 211 {
 212         unsigned long flags;
 213         u32 val;
 214
 215         spin_lock_irqsave(&cm_lock, flags);
 216         val = readl(CM_CTRL) & ~mask;
 217         writel(val | set, CM_CTRL);
 218         spin_unlock_irqrestore(&cm_lock, flags);
 219 }
 220
 221 EXPORT_SYMBOL(cm_control);
 222
 223 /*
 224  * Where is the timer (VA)?
 225  */
 226 #define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000)
 227 #define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100)
 228 #define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200)
 229
 230 /*
 231  * How long is the timer interval?
 232  */
 233 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 234 #if TIMER_INTERVAL >= 0x100000
 235 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 236 #elif TIMER_INTERVAL >= 0x10000
 237 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 238 #else
 239 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 240 #endif
 241
 242 static unsigned long timer_reload;
 243
 244 static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
 245
 246 static cycle_t timersp_read(struct clocksource *cs)
 247 {
 248         return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
 249 }
 250
 251 static struct clocksource clocksource_timersp = {
 252         .name           = "timer2",
 253         .rating         = 200,
 254         .read           = timersp_read,
 255         .mask           = CLOCKSOURCE_MASK(16),
 256         .shift          = 16,
 257         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 258 };
 259
 260 static void integrator_clocksource_init(u32 khz)
 261 {
 262         struct clocksource *cs = &clocksource_timersp;
 263         void __iomem *base = clksrc_base;
 264         u32 ctrl = TIMER_CTRL_ENABLE;
 265
 266         if (khz >= 1500) {
 267                 khz /= 16;
 268                 ctrl = TIMER_CTRL_DIV16;
 269         }
 270
 271         writel(ctrl, base + TIMER_CTRL);
 272         writel(0xffff, base + TIMER_LOAD);
 273
 274         cs->mult = clocksource_khz2mult(khz, cs->shift);
 275         clocksource_register(cs);
 276 }
 277
 278 /*
 279  * IRQ handler for the timer
 280  */
 281 static irqreturn_t
 282 integrator_timer_interrupt(int irq, void *dev_id)
 283 {
 284         /*
 285          * clear the interrupt
 286          */
 287         writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
 288
 289         timer_tick();
 290
 291         return IRQ_HANDLED;
 292 }
 293
 294 static struct irqaction integrator_timer_irq = {
 295         .name           = "Integrator Timer Tick",
 296         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 297         .handler        = integrator_timer_interrupt,
 298 };
 299
 300 /*
 301  * Set up timer interrupt, and return the current time in seconds.
 302  */
 303 void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
 304 {
 305         unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 306
 307         integrator_clocksource_init(reload * HZ / 1000);
 308
 309         timer_reload = reload;
 310         timer_ctrl |= ctrl;
 311
 312         if (timer_reload > 0x100000) {
 313                 timer_reload >>= 8;
 314                 timer_ctrl |= TIMER_CTRL_DIV256;
 315         } else if (timer_reload > 0x010000) {
 316                 timer_reload >>= 4;
 317                 timer_ctrl |= TIMER_CTRL_DIV16;
 318         }
 319
 320         /*
 321          * Initialise to a known state (all timers off)
 322          */
 323         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 324         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 325         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 326
 327         writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD);
 328         writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE);
 329         writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL);
 330
 331         /*
 332          * Make irqs happen for the system timer
 333          */
 334         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 335 }