2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/spinlock.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/ethtool.h>
31 #include <linux/phy.h>
35 #include <asm/uaccess.h>
37 #define MII_M1011_IEVENT 0x13
38 #define MII_M1011_IEVENT_CLEAR 0x0000
40 #define MII_M1011_IMASK 0x12
41 #define MII_M1011_IMASK_INIT 0x6400
42 #define MII_M1011_IMASK_CLEAR 0x0000
44 #define MII_M1011_PHY_SCR 0x10
45 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
47 #define MII_M1145_PHY_EXT_CR 0x14
48 #define MII_M1145_RGMII_RX_DELAY 0x0080
49 #define MII_M1145_RGMII_TX_DELAY 0x0002
51 #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
53 #define MII_M1111_PHY_LED_CONTROL 0x18
54 #define MII_M1111_PHY_LED_DIRECT 0x4100
55 #define MII_M1111_PHY_LED_COMBINE 0x411c
56 #define MII_M1111_PHY_EXT_CR 0x14
57 #define MII_M1111_RX_DELAY 0x80
58 #define MII_M1111_TX_DELAY 0x2
59 #define MII_M1111_PHY_EXT_SR 0x1b
61 #define MII_M1111_HWCFG_MODE_MASK 0xf
62 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
63 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
64 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
65 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
66 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
67 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
69 #define MII_M1111_COPPER 0
70 #define MII_M1111_FIBER 1
72 #define MII_88E1121_PHY_LED_CTRL 16
73 #define MII_88E1121_PHY_LED_PAGE 3
74 #define MII_88E1121_PHY_LED_DEF 0x0030
75 #define MII_88E1121_PHY_PAGE 22
77 #define MII_M1011_PHY_STATUS 0x11
78 #define MII_M1011_PHY_STATUS_1000 0x8000
79 #define MII_M1011_PHY_STATUS_100 0x4000
80 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
81 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
82 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
83 #define MII_M1011_PHY_STATUS_LINK 0x0400
86 MODULE_DESCRIPTION("Marvell PHY driver");
87 MODULE_AUTHOR("Andy Fleming");
88 MODULE_LICENSE("GPL");
90 static int marvell_ack_interrupt(struct phy_device *phydev)
94 /* Clear the interrupts by reading the reg */
95 err = phy_read(phydev, MII_M1011_IEVENT);
103 static int marvell_config_intr(struct phy_device *phydev)
107 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
108 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
110 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
115 static int marvell_config_aneg(struct phy_device *phydev)
119 /* The Marvell PHY has an errata which requires
120 * that certain registers get written in order
121 * to restart autonegotiation */
122 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
127 err = phy_write(phydev, 0x1d, 0x1f);
131 err = phy_write(phydev, 0x1e, 0x200c);
135 err = phy_write(phydev, 0x1d, 0x5);
139 err = phy_write(phydev, 0x1e, 0);
143 err = phy_write(phydev, 0x1e, 0x100);
147 err = phy_write(phydev, MII_M1011_PHY_SCR,
148 MII_M1011_PHY_SCR_AUTO_CROSS);
152 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
153 MII_M1111_PHY_LED_DIRECT);
157 err = genphy_config_aneg(phydev);
161 if (phydev->autoneg != AUTONEG_ENABLE) {
165 * A write to speed/duplex bits (that is performed by
166 * genphy_config_aneg() call above) must be followed by
167 * a software reset. Otherwise, the write has no effect.
169 bmcr = phy_read(phydev, MII_BMCR);
173 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
181 static int m88e1121_config_aneg(struct phy_device *phydev)
185 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
189 err = phy_write(phydev, MII_M1011_PHY_SCR,
190 MII_M1011_PHY_SCR_AUTO_CROSS);
194 temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
196 phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
197 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
198 phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
200 err = genphy_config_aneg(phydev);
205 static int m88e1111_config_init(struct phy_device *phydev)
210 /* Enable Fiber/Copper auto selection */
211 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
212 temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
213 phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
215 temp = phy_read(phydev, MII_BMCR);
217 phy_write(phydev, MII_BMCR, temp);
219 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
220 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
221 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
222 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
224 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
228 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
229 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
230 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
231 temp &= ~MII_M1111_TX_DELAY;
232 temp |= MII_M1111_RX_DELAY;
233 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
234 temp &= ~MII_M1111_RX_DELAY;
235 temp |= MII_M1111_TX_DELAY;
238 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
242 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
246 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
248 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
249 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
251 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
253 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
258 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
259 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
263 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
264 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
265 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
267 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
272 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
273 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
276 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
277 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
281 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
284 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
285 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
286 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
291 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
295 temp = phy_read(phydev, MII_BMCR);
296 while (temp & BMCR_RESET);
298 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
301 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
302 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
303 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
309 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
316 static int m88e1118_config_aneg(struct phy_device *phydev)
320 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
324 err = phy_write(phydev, MII_M1011_PHY_SCR,
325 MII_M1011_PHY_SCR_AUTO_CROSS);
329 err = genphy_config_aneg(phydev);
333 static int m88e1118_config_init(struct phy_device *phydev)
338 err = phy_write(phydev, 0x16, 0x0002);
342 /* Enable 1000 Mbit */
343 err = phy_write(phydev, 0x15, 0x1070);
348 err = phy_write(phydev, 0x16, 0x0003);
352 /* Adjust LED Control */
353 err = phy_write(phydev, 0x10, 0x021e);
358 err = phy_write(phydev, 0x16, 0x0);
362 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
369 static int m88e1145_config_init(struct phy_device *phydev)
373 /* Take care of errata E0 & E1 */
374 err = phy_write(phydev, 0x1d, 0x001b);
378 err = phy_write(phydev, 0x1e, 0x418f);
382 err = phy_write(phydev, 0x1d, 0x0016);
386 err = phy_write(phydev, 0x1e, 0xa2da);
390 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
391 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
395 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
397 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
401 if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
402 err = phy_write(phydev, 0x1d, 0x0012);
406 temp = phy_read(phydev, 0x1e);
411 temp |= 2 << 9; /* 36 ohm */
412 temp |= 2 << 6; /* 39 ohm */
414 err = phy_write(phydev, 0x1e, temp);
418 err = phy_write(phydev, 0x1d, 0x3);
422 err = phy_write(phydev, 0x1e, 0x8000);
431 /* marvell_read_status
433 * Generic status code does not detect Fiber correctly!
435 * Check the link, then figure out the current state
436 * by comparing what we advertise with what the link partner
437 * advertises. Start by checking the gigabit possibilities,
438 * then move on to 10/100.
440 static int marvell_read_status(struct phy_device *phydev)
447 /* Update the link, but return if there
449 err = genphy_update_link(phydev);
453 if (AUTONEG_ENABLE == phydev->autoneg) {
454 status = phy_read(phydev, MII_M1011_PHY_STATUS);
458 lpa = phy_read(phydev, MII_LPA);
462 adv = phy_read(phydev, MII_ADVERTISE);
468 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
469 phydev->duplex = DUPLEX_FULL;
471 phydev->duplex = DUPLEX_HALF;
473 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
474 phydev->pause = phydev->asym_pause = 0;
477 case MII_M1011_PHY_STATUS_1000:
478 phydev->speed = SPEED_1000;
481 case MII_M1011_PHY_STATUS_100:
482 phydev->speed = SPEED_100;
486 phydev->speed = SPEED_10;
490 if (phydev->duplex == DUPLEX_FULL) {
491 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
492 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
495 int bmcr = phy_read(phydev, MII_BMCR);
500 if (bmcr & BMCR_FULLDPLX)
501 phydev->duplex = DUPLEX_FULL;
503 phydev->duplex = DUPLEX_HALF;
505 if (bmcr & BMCR_SPEED1000)
506 phydev->speed = SPEED_1000;
507 else if (bmcr & BMCR_SPEED100)
508 phydev->speed = SPEED_100;
510 phydev->speed = SPEED_10;
512 phydev->pause = phydev->asym_pause = 0;
518 static int m88e1121_did_interrupt(struct phy_device *phydev)
522 imask = phy_read(phydev, MII_M1011_IEVENT);
524 if (imask & MII_M1011_IMASK_INIT)
530 static struct phy_driver marvell_drivers[] = {
532 .phy_id = 0x01410c60,
533 .phy_id_mask = 0xfffffff0,
534 .name = "Marvell 88E1101",
535 .features = PHY_GBIT_FEATURES,
536 .flags = PHY_HAS_INTERRUPT,
537 .config_aneg = &marvell_config_aneg,
538 .read_status = &genphy_read_status,
539 .ack_interrupt = &marvell_ack_interrupt,
540 .config_intr = &marvell_config_intr,
541 .driver = { .owner = THIS_MODULE },
544 .phy_id = 0x01410c90,
545 .phy_id_mask = 0xfffffff0,
546 .name = "Marvell 88E1112",
547 .features = PHY_GBIT_FEATURES,
548 .flags = PHY_HAS_INTERRUPT,
549 .config_init = &m88e1111_config_init,
550 .config_aneg = &marvell_config_aneg,
551 .read_status = &genphy_read_status,
552 .ack_interrupt = &marvell_ack_interrupt,
553 .config_intr = &marvell_config_intr,
554 .driver = { .owner = THIS_MODULE },
557 .phy_id = 0x01410cc0,
558 .phy_id_mask = 0xfffffff0,
559 .name = "Marvell 88E1111",
560 .features = PHY_GBIT_FEATURES,
561 .flags = PHY_HAS_INTERRUPT,
562 .config_init = &m88e1111_config_init,
563 .config_aneg = &marvell_config_aneg,
564 .read_status = &marvell_read_status,
565 .ack_interrupt = &marvell_ack_interrupt,
566 .config_intr = &marvell_config_intr,
567 .driver = { .owner = THIS_MODULE },
570 .phy_id = 0x01410e10,
571 .phy_id_mask = 0xfffffff0,
572 .name = "Marvell 88E1118",
573 .features = PHY_GBIT_FEATURES,
574 .flags = PHY_HAS_INTERRUPT,
575 .config_init = &m88e1118_config_init,
576 .config_aneg = &m88e1118_config_aneg,
577 .read_status = &genphy_read_status,
578 .ack_interrupt = &marvell_ack_interrupt,
579 .config_intr = &marvell_config_intr,
580 .driver = {.owner = THIS_MODULE,},
583 .phy_id = 0x01410cb0,
584 .phy_id_mask = 0xfffffff0,
585 .name = "Marvell 88E1121R",
586 .features = PHY_GBIT_FEATURES,
587 .flags = PHY_HAS_INTERRUPT,
588 .config_aneg = &m88e1121_config_aneg,
589 .read_status = &marvell_read_status,
590 .ack_interrupt = &marvell_ack_interrupt,
591 .config_intr = &marvell_config_intr,
592 .did_interrupt = &m88e1121_did_interrupt,
593 .driver = { .owner = THIS_MODULE },
596 .phy_id = 0x01410cd0,
597 .phy_id_mask = 0xfffffff0,
598 .name = "Marvell 88E1145",
599 .features = PHY_GBIT_FEATURES,
600 .flags = PHY_HAS_INTERRUPT,
601 .config_init = &m88e1145_config_init,
602 .config_aneg = &marvell_config_aneg,
603 .read_status = &genphy_read_status,
604 .ack_interrupt = &marvell_ack_interrupt,
605 .config_intr = &marvell_config_intr,
606 .driver = { .owner = THIS_MODULE },
609 .phy_id = 0x01410e30,
610 .phy_id_mask = 0xfffffff0,
611 .name = "Marvell 88E1240",
612 .features = PHY_GBIT_FEATURES,
613 .flags = PHY_HAS_INTERRUPT,
614 .config_init = &m88e1111_config_init,
615 .config_aneg = &marvell_config_aneg,
616 .read_status = &genphy_read_status,
617 .ack_interrupt = &marvell_ack_interrupt,
618 .config_intr = &marvell_config_intr,
619 .driver = { .owner = THIS_MODULE },
623 static int __init marvell_init(void)
628 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
629 ret = phy_driver_register(&marvell_drivers[i]);
633 phy_driver_unregister(&marvell_drivers[i]);
641 static void __exit marvell_exit(void)
645 for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
646 phy_driver_unregister(&marvell_drivers[i]);
649 module_init(marvell_init);
650 module_exit(marvell_exit);
652 static struct mdio_device_id marvell_tbl[] = {
653 { 0x01410c60, 0xfffffff0 },
654 { 0x01410c90, 0xfffffff0 },
655 { 0x01410cc0, 0xfffffff0 },
656 { 0x01410e10, 0xfffffff0 },
657 { 0x01410cb0, 0xfffffff0 },
658 { 0x01410cd0, 0xfffffff0 },
659 { 0x01410e30, 0xfffffff0 },
663 MODULE_DEVICE_TABLE(mdio, marvell_tbl);