SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/firmware.h>
  30 #include <linux/platform_device.h>
  31 #include "drmP.h"
  32 #include "radeon_drm.h"
  33 #include "radeon.h"
  34 #include "radeon_mode.h"
  35 #include "r600d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define PFP_UCODE_SIZE 576
  40 #define PM4_UCODE_SIZE 1792
  41 #define RLC_UCODE_SIZE 768
  42 #define R700_PFP_UCODE_SIZE 848
  43 #define R700_PM4_UCODE_SIZE 1360
  44 #define R700_RLC_UCODE_SIZE 1024
  45
  46 /* Firmware Names */
  47 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  48 MODULE_FIRMWARE("radeon/R600_me.bin");
  49 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV610_me.bin");
  51 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV630_me.bin");
  53 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV620_me.bin");
  55 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV635_me.bin");
  57 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV670_me.bin");
  59 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RS780_me.bin");
  61 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV770_me.bin");
  63 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV730_me.bin");
  65 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV710_me.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69
  70 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  71
  72 /* r600,rv610,rv630,rv620,rv635,rv670 */
  73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  74 void r600_gpu_init(struct radeon_device *rdev);
  75 void r600_fini(struct radeon_device *rdev);
  76
  77 /* hpd for digital panel detect/disconnect */
  78 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  79 {
  80         bool connected = false;
  81
  82         if (ASIC_IS_DCE3(rdev)) {
  83                 switch (hpd) {
  84                 case RADEON_HPD_1:
  85                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  86                                 connected = true;
  87                         break;
  88                 case RADEON_HPD_2:
  89                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  90                                 connected = true;
  91                         break;
  92                 case RADEON_HPD_3:
  93                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  94                                 connected = true;
  95                         break;
  96                 case RADEON_HPD_4:
  97                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  98                                 connected = true;
  99                         break;
 100                         /* DCE 3.2 */
 101                 case RADEON_HPD_5:
 102                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 103                                 connected = true;
 104                         break;
 105                 case RADEON_HPD_6:
 106                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 107                                 connected = true;
 108                         break;
 109                 default:
 110                         break;
 111                 }
 112         } else {
 113                 switch (hpd) {
 114                 case RADEON_HPD_1:
 115                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 116                                 connected = true;
 117                         break;
 118                 case RADEON_HPD_2:
 119                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 120                                 connected = true;
 121                         break;
 122                 case RADEON_HPD_3:
 123                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 124                                 connected = true;
 125                         break;
 126                 default:
 127                         break;
 128                 }
 129         }
 130         return connected;
 131 }
 132
 133 void r600_hpd_set_polarity(struct radeon_device *rdev,
 134                            enum radeon_hpd_id hpd)
 135 {
 136         u32 tmp;
 137         bool connected = r600_hpd_sense(rdev, hpd);
 138
 139         if (ASIC_IS_DCE3(rdev)) {
 140                 switch (hpd) {
 141                 case RADEON_HPD_1:
 142                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 143                         if (connected)
 144                                 tmp &= ~DC_HPDx_INT_POLARITY;
 145                         else
 146                                 tmp |= DC_HPDx_INT_POLARITY;
 147                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 148                         break;
 149                 case RADEON_HPD_2:
 150                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 151                         if (connected)
 152                                 tmp &= ~DC_HPDx_INT_POLARITY;
 153                         else
 154                                 tmp |= DC_HPDx_INT_POLARITY;
 155                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 156                         break;
 157                 case RADEON_HPD_3:
 158                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 159                         if (connected)
 160                                 tmp &= ~DC_HPDx_INT_POLARITY;
 161                         else
 162                                 tmp |= DC_HPDx_INT_POLARITY;
 163                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 164                         break;
 165                 case RADEON_HPD_4:
 166                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 167                         if (connected)
 168                                 tmp &= ~DC_HPDx_INT_POLARITY;
 169                         else
 170                                 tmp |= DC_HPDx_INT_POLARITY;
 171                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 172                         break;
 173                 case RADEON_HPD_5:
 174                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 175                         if (connected)
 176                                 tmp &= ~DC_HPDx_INT_POLARITY;
 177                         else
 178                                 tmp |= DC_HPDx_INT_POLARITY;
 179                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 180                         break;
 181                         /* DCE 3.2 */
 182                 case RADEON_HPD_6:
 183                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 184                         if (connected)
 185                                 tmp &= ~DC_HPDx_INT_POLARITY;
 186                         else
 187                                 tmp |= DC_HPDx_INT_POLARITY;
 188                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 189                         break;
 190                 default:
 191                         break;
 192                 }
 193         } else {
 194                 switch (hpd) {
 195                 case RADEON_HPD_1:
 196                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 197                         if (connected)
 198                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 199                         else
 200                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 201                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 202                         break;
 203                 case RADEON_HPD_2:
 204                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 205                         if (connected)
 206                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 207                         else
 208                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 209                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 210                         break;
 211                 case RADEON_HPD_3:
 212                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 213                         if (connected)
 214                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 215                         else
 216                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 217                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 218                         break;
 219                 default:
 220                         break;
 221                 }
 222         }
 223 }
 224
 225 void r600_hpd_init(struct radeon_device *rdev)
 226 {
 227         struct drm_device *dev = rdev->ddev;
 228         struct drm_connector *connector;
 229
 230         if (ASIC_IS_DCE3(rdev)) {
 231                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 232                 if (ASIC_IS_DCE32(rdev))
 233                         tmp |= DC_HPDx_EN;
 234
 235                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 236                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 237                         switch (radeon_connector->hpd.hpd) {
 238                         case RADEON_HPD_1:
 239                                 WREG32(DC_HPD1_CONTROL, tmp);
 240                                 rdev->irq.hpd[0] = true;
 241                                 break;
 242                         case RADEON_HPD_2:
 243                                 WREG32(DC_HPD2_CONTROL, tmp);
 244                                 rdev->irq.hpd[1] = true;
 245                                 break;
 246                         case RADEON_HPD_3:
 247                                 WREG32(DC_HPD3_CONTROL, tmp);
 248                                 rdev->irq.hpd[2] = true;
 249                                 break;
 250                         case RADEON_HPD_4:
 251                                 WREG32(DC_HPD4_CONTROL, tmp);
 252                                 rdev->irq.hpd[3] = true;
 253                                 break;
 254                                 /* DCE 3.2 */
 255                         case RADEON_HPD_5:
 256                                 WREG32(DC_HPD5_CONTROL, tmp);
 257                                 rdev->irq.hpd[4] = true;
 258                                 break;
 259                         case RADEON_HPD_6:
 260                                 WREG32(DC_HPD6_CONTROL, tmp);
 261                                 rdev->irq.hpd[5] = true;
 262                                 break;
 263                         default:
 264                                 break;
 265                         }
 266                 }
 267         } else {
 268                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 269                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 270                         switch (radeon_connector->hpd.hpd) {
 271                         case RADEON_HPD_1:
 272                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 273                                 rdev->irq.hpd[0] = true;
 274                                 break;
 275                         case RADEON_HPD_2:
 276                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 277                                 rdev->irq.hpd[1] = true;
 278                                 break;
 279                         case RADEON_HPD_3:
 280                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 281                                 rdev->irq.hpd[2] = true;
 282                                 break;
 283                         default:
 284                                 break;
 285                         }
 286                 }
 287         }
 288         if (rdev->irq.installed)
 289                 r600_irq_set(rdev);
 290 }
 291
 292 void r600_hpd_fini(struct radeon_device *rdev)
 293 {
 294         struct drm_device *dev = rdev->ddev;
 295         struct drm_connector *connector;
 296
 297         if (ASIC_IS_DCE3(rdev)) {
 298                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 299                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 300                         switch (radeon_connector->hpd.hpd) {
 301                         case RADEON_HPD_1:
 302                                 WREG32(DC_HPD1_CONTROL, 0);
 303                                 rdev->irq.hpd[0] = false;
 304                                 break;
 305                         case RADEON_HPD_2:
 306                                 WREG32(DC_HPD2_CONTROL, 0);
 307                                 rdev->irq.hpd[1] = false;
 308                                 break;
 309                         case RADEON_HPD_3:
 310                                 WREG32(DC_HPD3_CONTROL, 0);
 311                                 rdev->irq.hpd[2] = false;
 312                                 break;
 313                         case RADEON_HPD_4:
 314                                 WREG32(DC_HPD4_CONTROL, 0);
 315                                 rdev->irq.hpd[3] = false;
 316                                 break;
 317                                 /* DCE 3.2 */
 318                         case RADEON_HPD_5:
 319                                 WREG32(DC_HPD5_CONTROL, 0);
 320                                 rdev->irq.hpd[4] = false;
 321                                 break;
 322                         case RADEON_HPD_6:
 323                                 WREG32(DC_HPD6_CONTROL, 0);
 324                                 rdev->irq.hpd[5] = false;
 325                                 break;
 326                         default:
 327                                 break;
 328                         }
 329                 }
 330         } else {
 331                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 332                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 333                         switch (radeon_connector->hpd.hpd) {
 334                         case RADEON_HPD_1:
 335                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 336                                 rdev->irq.hpd[0] = false;
 337                                 break;
 338                         case RADEON_HPD_2:
 339                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 340                                 rdev->irq.hpd[1] = false;
 341                                 break;
 342                         case RADEON_HPD_3:
 343                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 344                                 rdev->irq.hpd[2] = false;
 345                                 break;
 346                         default:
 347                                 break;
 348                         }
 349                 }
 350         }
 351 }
 352
 353 /*
 354  * R600 PCIE GART
 355  */
 356 int r600_gart_clear_page(struct radeon_device *rdev, int i)
 357 {
 358         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 359         u64 pte;
 360
 361         if (i < 0 || i > rdev->gart.num_gpu_pages)
 362                 return -EINVAL;
 363         pte = 0;
 364         writeq(pte, ((void __iomem *)ptr) + (i * 8));
 365         return 0;
 366 }
 367
 368 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 369 {
 370         unsigned i;
 371         u32 tmp;
 372
 373         /* flush hdp cache so updates hit vram */
 374         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 375
 376         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 377         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 378         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 379         for (i = 0; i < rdev->usec_timeout; i++) {
 380                 /* read MC_STATUS */
 381                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 382                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 383                 if (tmp == 2) {
 384                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 385                         return;
 386                 }
 387                 if (tmp) {
 388                         return;
 389                 }
 390                 udelay(1);
 391         }
 392 }
 393
 394 int r600_pcie_gart_init(struct radeon_device *rdev)
 395 {
 396         int r;
 397
 398         if (rdev->gart.table.vram.robj) {
 399                 WARN(1, "R600 PCIE GART already initialized.\n");
 400                 return 0;
 401         }
 402         /* Initialize common gart structure */
 403         r = radeon_gart_init(rdev);
 404         if (r)
 405                 return r;
 406         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 407         return radeon_gart_table_vram_alloc(rdev);
 408 }
 409
 410 int r600_pcie_gart_enable(struct radeon_device *rdev)
 411 {
 412         u32 tmp;
 413         int r, i;
 414
 415         if (rdev->gart.table.vram.robj == NULL) {
 416                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 417                 return -EINVAL;
 418         }
 419         r = radeon_gart_table_vram_pin(rdev);
 420         if (r)
 421                 return r;
 422         radeon_gart_restore(rdev);
 423
 424         /* Setup L2 cache */
 425         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 426                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 427                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 428         WREG32(VM_L2_CNTL2, 0);
 429         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 430         /* Setup TLB control */
 431         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 432                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 433                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 434                 ENABLE_WAIT_L2_QUERY;
 435         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 436         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 437         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 438         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 439         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 440         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 441         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 442         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 443         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 444         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 445         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 446         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 447         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 448         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 449         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 450         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 451         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 452         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 453                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 454         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 455                         (u32)(rdev->dummy_page.addr >> 12));
 456         for (i = 1; i < 7; i++)
 457                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 458
 459         r600_pcie_gart_tlb_flush(rdev);
 460         rdev->gart.ready = true;
 461         return 0;
 462 }
 463
 464 void r600_pcie_gart_disable(struct radeon_device *rdev)
 465 {
 466         u32 tmp;
 467         int i, r;
 468
 469         /* Disable all tables */
 470         for (i = 0; i < 7; i++)
 471                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 472
 473         /* Disable L2 cache */
 474         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 475                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 476         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 477         /* Setup L1 TLB control */
 478         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 479                 ENABLE_WAIT_L2_QUERY;
 480         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 481         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 482         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 483         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 484         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 485         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 486         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 487         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 488         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 489         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 490         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 491         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 492         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 493         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 494         if (rdev->gart.table.vram.robj) {
 495                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 496                 if (likely(r == 0)) {
 497                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 498                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 499                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 500                 }
 501         }
 502 }
 503
 504 void r600_pcie_gart_fini(struct radeon_device *rdev)
 505 {
 506         r600_pcie_gart_disable(rdev);
 507         radeon_gart_table_vram_free(rdev);
 508         radeon_gart_fini(rdev);
 509 }
 510
 511 void r600_agp_enable(struct radeon_device *rdev)
 512 {
 513         u32 tmp;
 514         int i;
 515
 516         /* Setup L2 cache */
 517         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 518                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 519                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 520         WREG32(VM_L2_CNTL2, 0);
 521         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 522         /* Setup TLB control */
 523         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 524                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 525                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 526                 ENABLE_WAIT_L2_QUERY;
 527         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 528         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 529         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 530         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 531         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 532         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 533         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 534         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 535         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 536         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 537         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 538         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 539         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 540         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 541         for (i = 0; i < 7; i++)
 542                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 543 }
 544
 545 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 546 {
 547         unsigned i;
 548         u32 tmp;
 549
 550         for (i = 0; i < rdev->usec_timeout; i++) {
 551                 /* read MC_STATUS */
 552                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 553                 if (!tmp)
 554                         return 0;
 555                 udelay(1);
 556         }
 557         return -1;
 558 }
 559
 560 static void r600_mc_program(struct radeon_device *rdev)
 561 {
 562         struct rv515_mc_save save;
 563         u32 tmp;
 564         int i, j;
 565
 566         /* Initialize HDP */
 567         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 568                 WREG32((0x2c14 + j), 0x00000000);
 569                 WREG32((0x2c18 + j), 0x00000000);
 570                 WREG32((0x2c1c + j), 0x00000000);
 571                 WREG32((0x2c20 + j), 0x00000000);
 572                 WREG32((0x2c24 + j), 0x00000000);
 573         }
 574         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 575
 576         rv515_mc_stop(rdev, &save);
 577         if (r600_mc_wait_for_idle(rdev)) {
 578                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 579         }
 580         /* Lockout access through VGA aperture (doesn't exist before R600) */
 581         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 582         /* Update configuration */
 583         if (rdev->flags & RADEON_IS_AGP) {
 584                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 585                         /* VRAM before AGP */
 586                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 587                                 rdev->mc.vram_start >> 12);
 588                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 589                                 rdev->mc.gtt_end >> 12);
 590                 } else {
 591                         /* VRAM after AGP */
 592                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 593                                 rdev->mc.gtt_start >> 12);
 594                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 595                                 rdev->mc.vram_end >> 12);
 596                 }
 597         } else {
 598                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 599                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 600         }
 601         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 602         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 603         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 604         WREG32(MC_VM_FB_LOCATION, tmp);
 605         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 606         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 607         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 608         if (rdev->flags & RADEON_IS_AGP) {
 609                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 610                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 611                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 612         } else {
 613                 WREG32(MC_VM_AGP_BASE, 0);
 614                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 615                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 616         }
 617         if (r600_mc_wait_for_idle(rdev)) {
 618                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 619         }
 620         rv515_mc_resume(rdev, &save);
 621         /* we need to own VRAM, so turn off the VGA renderer here
 622          * to stop it overwriting our objects */
 623         rv515_vga_render_disable(rdev);
 624 }
 625
 626 int r600_mc_init(struct radeon_device *rdev)
 627 {
 628         fixed20_12 a;
 629         u32 tmp;
 630         int chansize, numchan;
 631
 632         /* Get VRAM informations */
 633         rdev->mc.vram_is_ddr = true;
 634         tmp = RREG32(RAMCFG);
 635         if (tmp & CHANSIZE_OVERRIDE) {
 636                 chansize = 16;
 637         } else if (tmp & CHANSIZE_MASK) {
 638                 chansize = 64;
 639         } else {
 640                 chansize = 32;
 641         }
 642         tmp = RREG32(CHMAP);
 643         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 644         case 0:
 645         default:
 646                 numchan = 1;
 647                 break;
 648         case 1:
 649                 numchan = 2;
 650                 break;
 651         case 2:
 652                 numchan = 4;
 653                 break;
 654         case 3:
 655                 numchan = 8;
 656                 break;
 657         }
 658         rdev->mc.vram_width = numchan * chansize;
 659         /* Could aper size report 0 ? */
 660         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 661         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 662         /* Setup GPU memory space */
 663         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 664         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 665
 666         if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
 667                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 668
 669         if (rdev->mc.real_vram_size > rdev->mc.aper_size)
 670                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 671
 672         if (rdev->flags & RADEON_IS_AGP) {
 673                 /* gtt_size is setup by radeon_agp_init */
 674                 rdev->mc.gtt_location = rdev->mc.agp_base;
 675                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
 676                 /* Try to put vram before or after AGP because we
 677                  * we want SYSTEM_APERTURE to cover both VRAM and
 678                  * AGP so that GPU can catch out of VRAM/AGP access
 679                  */
 680                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 681                         /* Enought place before */
 682                         rdev->mc.vram_location = rdev->mc.gtt_location -
 683                                                         rdev->mc.mc_vram_size;
 684                 } else if (tmp > rdev->mc.mc_vram_size) {
 685                         /* Enought place after */
 686                         rdev->mc.vram_location = rdev->mc.gtt_location +
 687                                                         rdev->mc.gtt_size;
 688                 } else {
 689                         /* Try to setup VRAM then AGP might not
 690                          * not work on some card
 691                          */
 692                         rdev->mc.vram_location = 0x00000000UL;
 693                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 694                 }
 695         } else {
 696                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 697                 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
 698                                                         0xFFFF) << 24;
 699                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
 700                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
 701                         /* Enough place after vram */
 702                         rdev->mc.gtt_location = tmp;
 703                 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
 704                         /* Enough place before vram */
 705                         rdev->mc.gtt_location = 0;
 706                 } else {
 707                         /* Not enough place after or before shrink
 708                          * gart size
 709                          */
 710                         if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
 711                                 rdev->mc.gtt_location = 0;
 712                                 rdev->mc.gtt_size = rdev->mc.vram_location;
 713                         } else {
 714                                 rdev->mc.gtt_location = tmp;
 715                                 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
 716                         }
 717                 }
 718                 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
 719         }
 720         rdev->mc.vram_start = rdev->mc.vram_location;
 721         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
 722         rdev->mc.gtt_start = rdev->mc.gtt_location;
 723         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
 724         /* FIXME: we should enforce default clock in case GPU is not in
 725          * default setup
 726          */
 727         a.full = rfixed_const(100);
 728         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 729         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 730
 731         if (rdev->flags & RADEON_IS_IGP)
 732                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 733
 734         return 0;
 735 }
 736
 737 /* We doesn't check that the GPU really needs a reset we simply do the
 738  * reset, it's up to the caller to determine if the GPU needs one. We
 739  * might add an helper function to check that.
 740  */
 741 int r600_gpu_soft_reset(struct radeon_device *rdev)
 742 {
 743         struct rv515_mc_save save;
 744         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 745                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 746                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 747                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 748                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 749                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 750                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 751                                 S_008010_GUI_ACTIVE(1);
 752         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 753                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 754                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 755                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 756                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 757                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 758                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 759                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 760         u32 srbm_reset = 0;
 761         u32 tmp;
 762
 763         dev_info(rdev->dev, "GPU softreset \n");
 764         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 765                 RREG32(R_008010_GRBM_STATUS));
 766         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 767                 RREG32(R_008014_GRBM_STATUS2));
 768         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 769                 RREG32(R_000E50_SRBM_STATUS));
 770         rv515_mc_stop(rdev, &save);
 771         if (r600_mc_wait_for_idle(rdev)) {
 772                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 773         }
 774         /* Disable CP parsing/prefetching */
 775         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 776         /* Check if any of the rendering block is busy and reset it */
 777         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 778             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 779                 tmp = S_008020_SOFT_RESET_CR(1) |
 780                         S_008020_SOFT_RESET_DB(1) |
 781                         S_008020_SOFT_RESET_CB(1) |
 782                         S_008020_SOFT_RESET_PA(1) |
 783                         S_008020_SOFT_RESET_SC(1) |
 784                         S_008020_SOFT_RESET_SMX(1) |
 785                         S_008020_SOFT_RESET_SPI(1) |
 786                         S_008020_SOFT_RESET_SX(1) |
 787                         S_008020_SOFT_RESET_SH(1) |
 788                         S_008020_SOFT_RESET_TC(1) |
 789                         S_008020_SOFT_RESET_TA(1) |
 790                         S_008020_SOFT_RESET_VC(1) |
 791                         S_008020_SOFT_RESET_VGT(1);
 792                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 793                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 794                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 795                 udelay(50);
 796                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 797                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 798         }
 799         /* Reset CP (we always reset CP) */
 800         tmp = S_008020_SOFT_RESET_CP(1);
 801         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 802         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 803         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 804         udelay(50);
 805         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 806         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 807         /* Reset others GPU block if necessary */
 808         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 809                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 810         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 811                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 812         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 813                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 814         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 815                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 816         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 817                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 818         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 819                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 820         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 821                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 822         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 823                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 824         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 825                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 826         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 827                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 828         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 829                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 830         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 831                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 832         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 833         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 834         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 835         udelay(50);
 836         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 837         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 838         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 839         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 840         udelay(50);
 841         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 842         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 843         /* Wait a little for things to settle down */
 844         udelay(50);
 845         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 846                 RREG32(R_008010_GRBM_STATUS));
 847         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 848                 RREG32(R_008014_GRBM_STATUS2));
 849         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 850                 RREG32(R_000E50_SRBM_STATUS));
 851         /* After reset we need to reinit the asic as GPU often endup in an
 852          * incoherent state.
 853          */
 854         atom_asic_init(rdev->mode_info.atom_context);
 855         rv515_mc_resume(rdev, &save);
 856         return 0;
 857 }
 858
 859 int r600_gpu_reset(struct radeon_device *rdev)
 860 {
 861         return r600_gpu_soft_reset(rdev);
 862 }
 863
 864 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 865                                              u32 num_backends,
 866                                              u32 backend_disable_mask)
 867 {
 868         u32 backend_map = 0;
 869         u32 enabled_backends_mask;
 870         u32 enabled_backends_count;
 871         u32 cur_pipe;
 872         u32 swizzle_pipe[R6XX_MAX_PIPES];
 873         u32 cur_backend;
 874         u32 i;
 875
 876         if (num_tile_pipes > R6XX_MAX_PIPES)
 877                 num_tile_pipes = R6XX_MAX_PIPES;
 878         if (num_tile_pipes < 1)
 879                 num_tile_pipes = 1;
 880         if (num_backends > R6XX_MAX_BACKENDS)
 881                 num_backends = R6XX_MAX_BACKENDS;
 882         if (num_backends < 1)
 883                 num_backends = 1;
 884
 885         enabled_backends_mask = 0;
 886         enabled_backends_count = 0;
 887         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 888                 if (((backend_disable_mask >> i) & 1) == 0) {
 889                         enabled_backends_mask |= (1 << i);
 890                         ++enabled_backends_count;
 891                 }
 892                 if (enabled_backends_count == num_backends)
 893                         break;
 894         }
 895
 896         if (enabled_backends_count == 0) {
 897                 enabled_backends_mask = 1;
 898                 enabled_backends_count = 1;
 899         }
 900
 901         if (enabled_backends_count != num_backends)
 902                 num_backends = enabled_backends_count;
 903
 904         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 905         switch (num_tile_pipes) {
 906         case 1:
 907                 swizzle_pipe[0] = 0;
 908                 break;
 909         case 2:
 910                 swizzle_pipe[0] = 0;
 911                 swizzle_pipe[1] = 1;
 912                 break;
 913         case 3:
 914                 swizzle_pipe[0] = 0;
 915                 swizzle_pipe[1] = 1;
 916                 swizzle_pipe[2] = 2;
 917                 break;
 918         case 4:
 919                 swizzle_pipe[0] = 0;
 920                 swizzle_pipe[1] = 1;
 921                 swizzle_pipe[2] = 2;
 922                 swizzle_pipe[3] = 3;
 923                 break;
 924         case 5:
 925                 swizzle_pipe[0] = 0;
 926                 swizzle_pipe[1] = 1;
 927                 swizzle_pipe[2] = 2;
 928                 swizzle_pipe[3] = 3;
 929                 swizzle_pipe[4] = 4;
 930                 break;
 931         case 6:
 932                 swizzle_pipe[0] = 0;
 933                 swizzle_pipe[1] = 2;
 934                 swizzle_pipe[2] = 4;
 935                 swizzle_pipe[3] = 5;
 936                 swizzle_pipe[4] = 1;
 937                 swizzle_pipe[5] = 3;
 938                 break;
 939         case 7:
 940                 swizzle_pipe[0] = 0;
 941                 swizzle_pipe[1] = 2;
 942                 swizzle_pipe[2] = 4;
 943                 swizzle_pipe[3] = 6;
 944                 swizzle_pipe[4] = 1;
 945                 swizzle_pipe[5] = 3;
 946                 swizzle_pipe[6] = 5;
 947                 break;
 948         case 8:
 949                 swizzle_pipe[0] = 0;
 950                 swizzle_pipe[1] = 2;
 951                 swizzle_pipe[2] = 4;
 952                 swizzle_pipe[3] = 6;
 953                 swizzle_pipe[4] = 1;
 954                 swizzle_pipe[5] = 3;
 955                 swizzle_pipe[6] = 5;
 956                 swizzle_pipe[7] = 7;
 957                 break;
 958         }
 959
 960         cur_backend = 0;
 961         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 962                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 963                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 964
 965                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 966
 967                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 968         }
 969
 970         return backend_map;
 971 }
 972
 973 int r600_count_pipe_bits(uint32_t val)
 974 {
 975         int i, ret = 0;
 976
 977         for (i = 0; i < 32; i++) {
 978                 ret += val & 1;
 979                 val >>= 1;
 980         }
 981         return ret;
 982 }
 983
 984 void r600_gpu_init(struct radeon_device *rdev)
 985 {
 986         u32 tiling_config;
 987         u32 ramcfg;
 988         u32 tmp;
 989         int i, j;
 990         u32 sq_config;
 991         u32 sq_gpr_resource_mgmt_1 = 0;
 992         u32 sq_gpr_resource_mgmt_2 = 0;
 993         u32 sq_thread_resource_mgmt = 0;
 994         u32 sq_stack_resource_mgmt_1 = 0;
 995         u32 sq_stack_resource_mgmt_2 = 0;
 996
 997         /* FIXME: implement */
 998         switch (rdev->family) {
 999         case CHIP_R600:
1000                 rdev->config.r600.max_pipes = 4;
1001                 rdev->config.r600.max_tile_pipes = 8;
1002                 rdev->config.r600.max_simds = 4;
1003                 rdev->config.r600.max_backends = 4;
1004                 rdev->config.r600.max_gprs = 256;
1005                 rdev->config.r600.max_threads = 192;
1006                 rdev->config.r600.max_stack_entries = 256;
1007                 rdev->config.r600.max_hw_contexts = 8;
1008                 rdev->config.r600.max_gs_threads = 16;
1009                 rdev->config.r600.sx_max_export_size = 128;
1010                 rdev->config.r600.sx_max_export_pos_size = 16;
1011                 rdev->config.r600.sx_max_export_smx_size = 128;
1012                 rdev->config.r600.sq_num_cf_insts = 2;
1013                 break;
1014         case CHIP_RV630:
1015         case CHIP_RV635:
1016                 rdev->config.r600.max_pipes = 2;
1017                 rdev->config.r600.max_tile_pipes = 2;
1018                 rdev->config.r600.max_simds = 3;
1019                 rdev->config.r600.max_backends = 1;
1020                 rdev->config.r600.max_gprs = 128;
1021                 rdev->config.r600.max_threads = 192;
1022                 rdev->config.r600.max_stack_entries = 128;
1023                 rdev->config.r600.max_hw_contexts = 8;
1024                 rdev->config.r600.max_gs_threads = 4;
1025                 rdev->config.r600.sx_max_export_size = 128;
1026                 rdev->config.r600.sx_max_export_pos_size = 16;
1027                 rdev->config.r600.sx_max_export_smx_size = 128;
1028                 rdev->config.r600.sq_num_cf_insts = 2;
1029                 break;
1030         case CHIP_RV610:
1031         case CHIP_RV620:
1032         case CHIP_RS780:
1033         case CHIP_RS880:
1034                 rdev->config.r600.max_pipes = 1;
1035                 rdev->config.r600.max_tile_pipes = 1;
1036                 rdev->config.r600.max_simds = 2;
1037                 rdev->config.r600.max_backends = 1;
1038                 rdev->config.r600.max_gprs = 128;
1039                 rdev->config.r600.max_threads = 192;
1040                 rdev->config.r600.max_stack_entries = 128;
1041                 rdev->config.r600.max_hw_contexts = 4;
1042                 rdev->config.r600.max_gs_threads = 4;
1043                 rdev->config.r600.sx_max_export_size = 128;
1044                 rdev->config.r600.sx_max_export_pos_size = 16;
1045                 rdev->config.r600.sx_max_export_smx_size = 128;
1046                 rdev->config.r600.sq_num_cf_insts = 1;
1047                 break;
1048         case CHIP_RV670:
1049                 rdev->config.r600.max_pipes = 4;
1050                 rdev->config.r600.max_tile_pipes = 4;
1051                 rdev->config.r600.max_simds = 4;
1052                 rdev->config.r600.max_backends = 4;
1053                 rdev->config.r600.max_gprs = 192;
1054                 rdev->config.r600.max_threads = 192;
1055                 rdev->config.r600.max_stack_entries = 256;
1056                 rdev->config.r600.max_hw_contexts = 8;
1057                 rdev->config.r600.max_gs_threads = 16;
1058                 rdev->config.r600.sx_max_export_size = 128;
1059                 rdev->config.r600.sx_max_export_pos_size = 16;
1060                 rdev->config.r600.sx_max_export_smx_size = 128;
1061                 rdev->config.r600.sq_num_cf_insts = 2;
1062                 break;
1063         default:
1064                 break;
1065         }
1066
1067         /* Initialize HDP */
1068         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1069                 WREG32((0x2c14 + j), 0x00000000);
1070                 WREG32((0x2c18 + j), 0x00000000);
1071                 WREG32((0x2c1c + j), 0x00000000);
1072                 WREG32((0x2c20 + j), 0x00000000);
1073                 WREG32((0x2c24 + j), 0x00000000);
1074         }
1075
1076         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1077
1078         /* Setup tiling */
1079         tiling_config = 0;
1080         ramcfg = RREG32(RAMCFG);
1081         switch (rdev->config.r600.max_tile_pipes) {
1082         case 1:
1083                 tiling_config |= PIPE_TILING(0);
1084                 rdev->config.r600.tiling_npipes = 1;
1085                 break;
1086         case 2:
1087                 tiling_config |= PIPE_TILING(1);
1088                 rdev->config.r600.tiling_npipes = 2;
1089                 break;
1090         case 4:
1091                 tiling_config |= PIPE_TILING(2);
1092                 rdev->config.r600.tiling_npipes = 4;
1093                 break;
1094         case 8:
1095                 tiling_config |= PIPE_TILING(3);
1096                 rdev->config.r600.tiling_npipes = 8;
1097                 break;
1098         default:
1099                 break;
1100         }
1101         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1102         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1103         tiling_config |= GROUP_SIZE(0);
1104         rdev->config.r600.tiling_group_size = 256;
1105         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1106         if (tmp > 3) {
1107                 tiling_config |= ROW_TILING(3);
1108                 tiling_config |= SAMPLE_SPLIT(3);
1109         } else {
1110                 tiling_config |= ROW_TILING(tmp);
1111                 tiling_config |= SAMPLE_SPLIT(tmp);
1112         }
1113         tiling_config |= BANK_SWAPS(1);
1114         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1115                                                 rdev->config.r600.max_backends,
1116                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
1117         tiling_config |= BACKEND_MAP(tmp);
1118         WREG32(GB_TILING_CONFIG, tiling_config);
1119         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1120         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1121
1122         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1123         WREG32(CC_RB_BACKEND_DISABLE, tmp);
1124
1125         /* Setup pipes */
1126         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1127         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1128         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
1129         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
1130
1131         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
1132         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1133         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1134
1135         /* Setup some CP states */
1136         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1137         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1138
1139         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1140                              SYNC_WALKER | SYNC_ALIGNER));
1141         /* Setup various GPU states */
1142         if (rdev->family == CHIP_RV670)
1143                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1144
1145         tmp = RREG32(SX_DEBUG_1);
1146         tmp |= SMX_EVENT_RELEASE;
1147         if ((rdev->family > CHIP_R600))
1148                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1149         WREG32(SX_DEBUG_1, tmp);
1150
1151         if (((rdev->family) == CHIP_R600) ||
1152             ((rdev->family) == CHIP_RV630) ||
1153             ((rdev->family) == CHIP_RV610) ||
1154             ((rdev->family) == CHIP_RV620) ||
1155             ((rdev->family) == CHIP_RS780) ||
1156             ((rdev->family) == CHIP_RS880)) {
1157                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1158         } else {
1159                 WREG32(DB_DEBUG, 0);
1160         }
1161         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1162                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1163
1164         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1165         WREG32(VGT_NUM_INSTANCES, 0);
1166
1167         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1168         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1169
1170         tmp = RREG32(SQ_MS_FIFO_SIZES);
1171         if (((rdev->family) == CHIP_RV610) ||
1172             ((rdev->family) == CHIP_RV620) ||
1173             ((rdev->family) == CHIP_RS780) ||
1174             ((rdev->family) == CHIP_RS880)) {
1175                 tmp = (CACHE_FIFO_SIZE(0xa) |
1176                        FETCH_FIFO_HIWATER(0xa) |
1177                        DONE_FIFO_HIWATER(0xe0) |
1178                        ALU_UPDATE_FIFO_HIWATER(0x8));
1179         } else if (((rdev->family) == CHIP_R600) ||
1180                    ((rdev->family) == CHIP_RV630)) {
1181                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1182                 tmp |= DONE_FIFO_HIWATER(0x4);
1183         }
1184         WREG32(SQ_MS_FIFO_SIZES, tmp);
1185
1186         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1187          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1188          */
1189         sq_config = RREG32(SQ_CONFIG);
1190         sq_config &= ~(PS_PRIO(3) |
1191                        VS_PRIO(3) |
1192                        GS_PRIO(3) |
1193                        ES_PRIO(3));
1194         sq_config |= (DX9_CONSTS |
1195                       VC_ENABLE |
1196                       PS_PRIO(0) |
1197                       VS_PRIO(1) |
1198                       GS_PRIO(2) |
1199                       ES_PRIO(3));
1200
1201         if ((rdev->family) == CHIP_R600) {
1202                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1203                                           NUM_VS_GPRS(124) |
1204                                           NUM_CLAUSE_TEMP_GPRS(4));
1205                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1206                                           NUM_ES_GPRS(0));
1207                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1208                                            NUM_VS_THREADS(48) |
1209                                            NUM_GS_THREADS(4) |
1210                                            NUM_ES_THREADS(4));
1211                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1212                                             NUM_VS_STACK_ENTRIES(128));
1213                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1214                                             NUM_ES_STACK_ENTRIES(0));
1215         } else if (((rdev->family) == CHIP_RV610) ||
1216                    ((rdev->family) == CHIP_RV620) ||
1217                    ((rdev->family) == CHIP_RS780) ||
1218                    ((rdev->family) == CHIP_RS880)) {
1219                 /* no vertex cache */
1220                 sq_config &= ~VC_ENABLE;
1221
1222                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1223                                           NUM_VS_GPRS(44) |
1224                                           NUM_CLAUSE_TEMP_GPRS(2));
1225                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1226                                           NUM_ES_GPRS(17));
1227                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1228                                            NUM_VS_THREADS(78) |
1229                                            NUM_GS_THREADS(4) |
1230                                            NUM_ES_THREADS(31));
1231                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1232                                             NUM_VS_STACK_ENTRIES(40));
1233                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1234                                             NUM_ES_STACK_ENTRIES(16));
1235         } else if (((rdev->family) == CHIP_RV630) ||
1236                    ((rdev->family) == CHIP_RV635)) {
1237                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1238                                           NUM_VS_GPRS(44) |
1239                                           NUM_CLAUSE_TEMP_GPRS(2));
1240                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1241                                           NUM_ES_GPRS(18));
1242                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1243                                            NUM_VS_THREADS(78) |
1244                                            NUM_GS_THREADS(4) |
1245                                            NUM_ES_THREADS(31));
1246                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1247                                             NUM_VS_STACK_ENTRIES(40));
1248                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1249                                             NUM_ES_STACK_ENTRIES(16));
1250         } else if ((rdev->family) == CHIP_RV670) {
1251                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1252                                           NUM_VS_GPRS(44) |
1253                                           NUM_CLAUSE_TEMP_GPRS(2));
1254                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1255                                           NUM_ES_GPRS(17));
1256                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1257                                            NUM_VS_THREADS(78) |
1258                                            NUM_GS_THREADS(4) |
1259                                            NUM_ES_THREADS(31));
1260                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1261                                             NUM_VS_STACK_ENTRIES(64));
1262                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1263                                             NUM_ES_STACK_ENTRIES(64));
1264         }
1265
1266         WREG32(SQ_CONFIG, sq_config);
1267         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1268         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1269         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1270         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1271         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1272
1273         if (((rdev->family) == CHIP_RV610) ||
1274             ((rdev->family) == CHIP_RV620) ||
1275             ((rdev->family) == CHIP_RS780) ||
1276             ((rdev->family) == CHIP_RS880)) {
1277                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1278         } else {
1279                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1280         }
1281
1282         /* More default values. 2D/3D driver should adjust as needed */
1283         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1284                                          S1_X(0x4) | S1_Y(0xc)));
1285         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1286                                          S1_X(0x2) | S1_Y(0x2) |
1287                                          S2_X(0xa) | S2_Y(0x6) |
1288                                          S3_X(0x6) | S3_Y(0xa)));
1289         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1290                                              S1_X(0x4) | S1_Y(0xc) |
1291                                              S2_X(0x1) | S2_Y(0x6) |
1292                                              S3_X(0xa) | S3_Y(0xe)));
1293         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1294                                              S5_X(0x0) | S5_Y(0x0) |
1295                                              S6_X(0xb) | S6_Y(0x4) |
1296                                              S7_X(0x7) | S7_Y(0x8)));
1297
1298         WREG32(VGT_STRMOUT_EN, 0);
1299         tmp = rdev->config.r600.max_pipes * 16;
1300         switch (rdev->family) {
1301         case CHIP_RV610:
1302         case CHIP_RV620:
1303         case CHIP_RS780:
1304         case CHIP_RS880:
1305                 tmp += 32;
1306                 break;
1307         case CHIP_RV670:
1308                 tmp += 128;
1309                 break;
1310         default:
1311                 break;
1312         }
1313         if (tmp > 256) {
1314                 tmp = 256;
1315         }
1316         WREG32(VGT_ES_PER_GS, 128);
1317         WREG32(VGT_GS_PER_ES, tmp);
1318         WREG32(VGT_GS_PER_VS, 2);
1319         WREG32(VGT_GS_VERTEX_REUSE, 16);
1320
1321         /* more default values. 2D/3D driver should adjust as needed */
1322         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1323         WREG32(VGT_STRMOUT_EN, 0);
1324         WREG32(SX_MISC, 0);
1325         WREG32(PA_SC_MODE_CNTL, 0);
1326         WREG32(PA_SC_AA_CONFIG, 0);
1327         WREG32(PA_SC_LINE_STIPPLE, 0);
1328         WREG32(SPI_INPUT_Z, 0);
1329         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1330         WREG32(CB_COLOR7_FRAG, 0);
1331
1332         /* Clear render buffer base addresses */
1333         WREG32(CB_COLOR0_BASE, 0);
1334         WREG32(CB_COLOR1_BASE, 0);
1335         WREG32(CB_COLOR2_BASE, 0);
1336         WREG32(CB_COLOR3_BASE, 0);
1337         WREG32(CB_COLOR4_BASE, 0);
1338         WREG32(CB_COLOR5_BASE, 0);
1339         WREG32(CB_COLOR6_BASE, 0);
1340         WREG32(CB_COLOR7_BASE, 0);
1341         WREG32(CB_COLOR7_FRAG, 0);
1342
1343         switch (rdev->family) {
1344         case CHIP_RV610:
1345         case CHIP_RV620:
1346         case CHIP_RS780:
1347         case CHIP_RS880:
1348                 tmp = TC_L2_SIZE(8);
1349                 break;
1350         case CHIP_RV630:
1351         case CHIP_RV635:
1352                 tmp = TC_L2_SIZE(4);
1353                 break;
1354         case CHIP_R600:
1355                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1356                 break;
1357         default:
1358                 tmp = TC_L2_SIZE(0);
1359                 break;
1360         }
1361         WREG32(TC_CNTL, tmp);
1362
1363         tmp = RREG32(HDP_HOST_PATH_CNTL);
1364         WREG32(HDP_HOST_PATH_CNTL, tmp);
1365
1366         tmp = RREG32(ARB_POP);
1367         tmp |= ENABLE_TC128;
1368         WREG32(ARB_POP, tmp);
1369
1370         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1371         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1372                                NUM_CLIP_SEQ(3)));
1373         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1374 }
1375
1376
1377 /*
1378  * Indirect registers accessor
1379  */
1380 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1381 {
1382         u32 r;
1383
1384         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1385         (void)RREG32(PCIE_PORT_INDEX);
1386         r = RREG32(PCIE_PORT_DATA);
1387         return r;
1388 }
1389
1390 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1391 {
1392         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1393         (void)RREG32(PCIE_PORT_INDEX);
1394         WREG32(PCIE_PORT_DATA, (v));
1395         (void)RREG32(PCIE_PORT_DATA);
1396 }
1397
1398 /*
1399  * CP & Ring
1400  */
1401 void r600_cp_stop(struct radeon_device *rdev)
1402 {
1403         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1404 }
1405
1406 int r600_init_microcode(struct radeon_device *rdev)
1407 {
1408         struct platform_device *pdev;
1409         const char *chip_name;
1410         const char *rlc_chip_name;
1411         size_t pfp_req_size, me_req_size, rlc_req_size;
1412         char fw_name[30];
1413         int err;
1414
1415         DRM_DEBUG("\n");
1416
1417         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1418         err = IS_ERR(pdev);
1419         if (err) {
1420                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1421                 return -EINVAL;
1422         }
1423
1424         switch (rdev->family) {
1425         case CHIP_R600:
1426                 chip_name = "R600";
1427                 rlc_chip_name = "R600";
1428                 break;
1429         case CHIP_RV610:
1430                 chip_name = "RV610";
1431                 rlc_chip_name = "R600";
1432                 break;
1433         case CHIP_RV630:
1434                 chip_name = "RV630";
1435                 rlc_chip_name = "R600";
1436                 break;
1437         case CHIP_RV620:
1438                 chip_name = "RV620";
1439                 rlc_chip_name = "R600";
1440                 break;
1441         case CHIP_RV635:
1442                 chip_name = "RV635";
1443                 rlc_chip_name = "R600";
1444                 break;
1445         case CHIP_RV670:
1446                 chip_name = "RV670";
1447                 rlc_chip_name = "R600";
1448                 break;
1449         case CHIP_RS780:
1450         case CHIP_RS880:
1451                 chip_name = "RS780";
1452                 rlc_chip_name = "R600";
1453                 break;
1454         case CHIP_RV770:
1455                 chip_name = "RV770";
1456                 rlc_chip_name = "R700";
1457                 break;
1458         case CHIP_RV730:
1459         case CHIP_RV740:
1460                 chip_name = "RV730";
1461                 rlc_chip_name = "R700";
1462                 break;
1463         case CHIP_RV710:
1464                 chip_name = "RV710";
1465                 rlc_chip_name = "R700";
1466                 break;
1467         default: BUG();
1468         }
1469
1470         if (rdev->family >= CHIP_RV770) {
1471                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1472                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1473                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1474         } else {
1475                 pfp_req_size = PFP_UCODE_SIZE * 4;
1476                 me_req_size = PM4_UCODE_SIZE * 12;
1477                 rlc_req_size = RLC_UCODE_SIZE * 4;
1478         }
1479
1480         DRM_INFO("Loading %s Microcode\n", chip_name);
1481
1482         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1483         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1484         if (err)
1485                 goto out;
1486         if (rdev->pfp_fw->size != pfp_req_size) {
1487                 printk(KERN_ERR
1488                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1489                        rdev->pfp_fw->size, fw_name);
1490                 err = -EINVAL;
1491                 goto out;
1492         }
1493
1494         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1495         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1496         if (err)
1497                 goto out;
1498         if (rdev->me_fw->size != me_req_size) {
1499                 printk(KERN_ERR
1500                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1501                        rdev->me_fw->size, fw_name);
1502                 err = -EINVAL;
1503         }
1504
1505         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1506         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1507         if (err)
1508                 goto out;
1509         if (rdev->rlc_fw->size != rlc_req_size) {
1510                 printk(KERN_ERR
1511                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1512                        rdev->rlc_fw->size, fw_name);
1513                 err = -EINVAL;
1514         }
1515
1516 out:
1517         platform_device_unregister(pdev);
1518
1519         if (err) {
1520                 if (err != -EINVAL)
1521                         printk(KERN_ERR
1522                                "r600_cp: Failed to load firmware \"%s\"\n",
1523                                fw_name);
1524                 release_firmware(rdev->pfp_fw);
1525                 rdev->pfp_fw = NULL;
1526                 release_firmware(rdev->me_fw);
1527                 rdev->me_fw = NULL;
1528                 release_firmware(rdev->rlc_fw);
1529                 rdev->rlc_fw = NULL;
1530         }
1531         return err;
1532 }
1533
1534 static int r600_cp_load_microcode(struct radeon_device *rdev)
1535 {
1536         const __be32 *fw_data;
1537         int i;
1538
1539         if (!rdev->me_fw || !rdev->pfp_fw)
1540                 return -EINVAL;
1541
1542         r600_cp_stop(rdev);
1543
1544         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1545
1546         /* Reset cp */
1547         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1548         RREG32(GRBM_SOFT_RESET);
1549         mdelay(15);
1550         WREG32(GRBM_SOFT_RESET, 0);
1551
1552         WREG32(CP_ME_RAM_WADDR, 0);
1553
1554         fw_data = (const __be32 *)rdev->me_fw->data;
1555         WREG32(CP_ME_RAM_WADDR, 0);
1556         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1557                 WREG32(CP_ME_RAM_DATA,
1558                        be32_to_cpup(fw_data++));
1559
1560         fw_data = (const __be32 *)rdev->pfp_fw->data;
1561         WREG32(CP_PFP_UCODE_ADDR, 0);
1562         for (i = 0; i < PFP_UCODE_SIZE; i++)
1563                 WREG32(CP_PFP_UCODE_DATA,
1564                        be32_to_cpup(fw_data++));
1565
1566         WREG32(CP_PFP_UCODE_ADDR, 0);
1567         WREG32(CP_ME_RAM_WADDR, 0);
1568         WREG32(CP_ME_RAM_RADDR, 0);
1569         return 0;
1570 }
1571
1572 int r600_cp_start(struct radeon_device *rdev)
1573 {
1574         int r;
1575         uint32_t cp_me;
1576
1577         r = radeon_ring_lock(rdev, 7);
1578         if (r) {
1579                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1580                 return r;
1581         }
1582         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1583         radeon_ring_write(rdev, 0x1);
1584         if (rdev->family < CHIP_RV770) {
1585                 radeon_ring_write(rdev, 0x3);
1586                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1587         } else {
1588                 radeon_ring_write(rdev, 0x0);
1589                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1590         }
1591         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1592         radeon_ring_write(rdev, 0);
1593         radeon_ring_write(rdev, 0);
1594         radeon_ring_unlock_commit(rdev);
1595
1596         cp_me = 0xff;
1597         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1598         return 0;
1599 }
1600
1601 int r600_cp_resume(struct radeon_device *rdev)
1602 {
1603         u32 tmp;
1604         u32 rb_bufsz;
1605         int r;
1606
1607         /* Reset cp */
1608         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1609         RREG32(GRBM_SOFT_RESET);
1610         mdelay(15);
1611         WREG32(GRBM_SOFT_RESET, 0);
1612
1613         /* Set ring buffer size */
1614         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1615         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1616 #ifdef __BIG_ENDIAN
1617         tmp |= BUF_SWAP_32BIT;
1618 #endif
1619         WREG32(CP_RB_CNTL, tmp);
1620         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1621
1622         /* Set the write pointer delay */
1623         WREG32(CP_RB_WPTR_DELAY, 0);
1624
1625         /* Initialize the ring buffer's read and write pointers */
1626         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1627         WREG32(CP_RB_RPTR_WR, 0);
1628         WREG32(CP_RB_WPTR, 0);
1629         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1630         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1631         mdelay(1);
1632         WREG32(CP_RB_CNTL, tmp);
1633
1634         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1635         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1636
1637         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1638         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1639
1640         r600_cp_start(rdev);
1641         rdev->cp.ready = true;
1642         r = radeon_ring_test(rdev);
1643         if (r) {
1644                 rdev->cp.ready = false;
1645                 return r;
1646         }
1647         return 0;
1648 }
1649
1650 void r600_cp_commit(struct radeon_device *rdev)
1651 {
1652         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1653         (void)RREG32(CP_RB_WPTR);
1654 }
1655
1656 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1657 {
1658         u32 rb_bufsz;
1659
1660         /* Align ring size */
1661         rb_bufsz = drm_order(ring_size / 8);
1662         ring_size = (1 << (rb_bufsz + 1)) * 4;
1663         rdev->cp.ring_size = ring_size;
1664         rdev->cp.align_mask = 16 - 1;
1665 }
1666
1667 void r600_cp_fini(struct radeon_device *rdev)
1668 {
1669         r600_cp_stop(rdev);
1670         radeon_ring_fini(rdev);
1671 }
1672
1673
1674 /*
1675  * GPU scratch registers helpers function.
1676  */
1677 void r600_scratch_init(struct radeon_device *rdev)
1678 {
1679         int i;
1680
1681         rdev->scratch.num_reg = 7;
1682         for (i = 0; i < rdev->scratch.num_reg; i++) {
1683                 rdev->scratch.free[i] = true;
1684                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1685         }
1686 }
1687
1688 int r600_ring_test(struct radeon_device *rdev)
1689 {
1690         uint32_t scratch;
1691         uint32_t tmp = 0;
1692         unsigned i;
1693         int r;
1694
1695         r = radeon_scratch_get(rdev, &scratch);
1696         if (r) {
1697                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1698                 return r;
1699         }
1700         WREG32(scratch, 0xCAFEDEAD);
1701         r = radeon_ring_lock(rdev, 3);
1702         if (r) {
1703                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1704                 radeon_scratch_free(rdev, scratch);
1705                 return r;
1706         }
1707         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1708         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1709         radeon_ring_write(rdev, 0xDEADBEEF);
1710         radeon_ring_unlock_commit(rdev);
1711         for (i = 0; i < rdev->usec_timeout; i++) {
1712                 tmp = RREG32(scratch);
1713                 if (tmp == 0xDEADBEEF)
1714                         break;
1715                 DRM_UDELAY(1);
1716         }
1717         if (i < rdev->usec_timeout) {
1718                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1719         } else {
1720                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1721                           scratch, tmp);
1722                 r = -EINVAL;
1723         }
1724         radeon_scratch_free(rdev, scratch);
1725         return r;
1726 }
1727
1728 void r600_wb_disable(struct radeon_device *rdev)
1729 {
1730         int r;
1731
1732         WREG32(SCRATCH_UMSK, 0);
1733         if (rdev->wb.wb_obj) {
1734                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1735                 if (unlikely(r != 0))
1736                         return;
1737                 radeon_bo_kunmap(rdev->wb.wb_obj);
1738                 radeon_bo_unpin(rdev->wb.wb_obj);
1739                 radeon_bo_unreserve(rdev->wb.wb_obj);
1740         }
1741 }
1742
1743 void r600_wb_fini(struct radeon_device *rdev)
1744 {
1745         r600_wb_disable(rdev);
1746         if (rdev->wb.wb_obj) {
1747                 radeon_bo_unref(&rdev->wb.wb_obj);
1748                 rdev->wb.wb = NULL;
1749                 rdev->wb.wb_obj = NULL;
1750         }
1751 }
1752
1753 int r600_wb_enable(struct radeon_device *rdev)
1754 {
1755         int r;
1756
1757         if (rdev->wb.wb_obj == NULL) {
1758                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1759                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1760                 if (r) {
1761                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1762                         return r;
1763                 }
1764                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1765                 if (unlikely(r != 0)) {
1766                         r600_wb_fini(rdev);
1767                         return r;
1768                 }
1769                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1770                                 &rdev->wb.gpu_addr);
1771                 if (r) {
1772                         radeon_bo_unreserve(rdev->wb.wb_obj);
1773                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1774                         r600_wb_fini(rdev);
1775                         return r;
1776                 }
1777                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1778                 radeon_bo_unreserve(rdev->wb.wb_obj);
1779                 if (r) {
1780                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1781                         r600_wb_fini(rdev);
1782                         return r;
1783                 }
1784         }
1785         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1786         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1787         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1788         WREG32(SCRATCH_UMSK, 0xff);
1789         return 0;
1790 }
1791
1792 void r600_fence_ring_emit(struct radeon_device *rdev,
1793                           struct radeon_fence *fence)
1794 {
1795         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1796
1797         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1798         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1799         /* wait for 3D idle clean */
1800         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1801         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1802         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1803         /* Emit fence sequence & fire IRQ */
1804         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1805         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1806         radeon_ring_write(rdev, fence->seq);
1807         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1808         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1809         radeon_ring_write(rdev, RB_INT_STAT);
1810 }
1811
1812 int r600_copy_blit(struct radeon_device *rdev,
1813                    uint64_t src_offset, uint64_t dst_offset,
1814                    unsigned num_pages, struct radeon_fence *fence)
1815 {
1816         int r;
1817
1818         mutex_lock(&rdev->r600_blit.mutex);
1819         rdev->r600_blit.vb_ib = NULL;
1820         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1821         if (r) {
1822                 if (rdev->r600_blit.vb_ib)
1823                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1824                 mutex_unlock(&rdev->r600_blit.mutex);
1825                 return r;
1826         }
1827         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1828         r600_blit_done_copy(rdev, fence);
1829         mutex_unlock(&rdev->r600_blit.mutex);
1830         return 0;
1831 }
1832
1833 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1834                          uint32_t tiling_flags, uint32_t pitch,
1835                          uint32_t offset, uint32_t obj_size)
1836 {
1837         /* FIXME: implement */
1838         return 0;
1839 }
1840
1841 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1842 {
1843         /* FIXME: implement */
1844 }
1845
1846
1847 bool r600_card_posted(struct radeon_device *rdev)
1848 {
1849         uint32_t reg;
1850
1851         /* first check CRTCs */
1852         reg = RREG32(D1CRTC_CONTROL) |
1853                 RREG32(D2CRTC_CONTROL);
1854         if (reg & CRTC_EN)
1855                 return true;
1856
1857         /* then check MEM_SIZE, in case the crtcs are off */
1858         if (RREG32(CONFIG_MEMSIZE))
1859                 return true;
1860
1861         return false;
1862 }
1863
1864 int r600_startup(struct radeon_device *rdev)
1865 {
1866         int r;
1867
1868         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1869                 r = r600_init_microcode(rdev);
1870                 if (r) {
1871                         DRM_ERROR("Failed to load firmware!\n");
1872                         return r;
1873                 }
1874         }
1875
1876         r600_mc_program(rdev);
1877         if (rdev->flags & RADEON_IS_AGP) {
1878                 r600_agp_enable(rdev);
1879         } else {
1880                 r = r600_pcie_gart_enable(rdev);
1881                 if (r)
1882                         return r;
1883         }
1884         r600_gpu_init(rdev);
1885         r = r600_blit_init(rdev);
1886         if (r) {
1887                 r600_blit_fini(rdev);
1888                 rdev->asic->copy = NULL;
1889                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1890         }
1891         /* pin copy shader into vram */
1892         if (rdev->r600_blit.shader_obj) {
1893                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1894                 if (unlikely(r != 0))
1895                         return r;
1896                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1897                                 &rdev->r600_blit.shader_gpu_addr);
1898                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1899                 if (r) {
1900                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1901                         return r;
1902                 }
1903         }
1904         /* Enable IRQ */
1905         r = r600_irq_init(rdev);
1906         if (r) {
1907                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1908                 radeon_irq_kms_fini(rdev);
1909                 return r;
1910         }
1911         r600_irq_set(rdev);
1912
1913         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1914         if (r)
1915                 return r;
1916         r = r600_cp_load_microcode(rdev);
1917         if (r)
1918                 return r;
1919         r = r600_cp_resume(rdev);
1920         if (r)
1921                 return r;
1922         /* write back buffer are not vital so don't worry about failure */
1923         r600_wb_enable(rdev);
1924         return 0;
1925 }
1926
1927 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1928 {
1929         uint32_t temp;
1930
1931         temp = RREG32(CONFIG_CNTL);
1932         if (state == false) {
1933                 temp &= ~(1<<0);
1934                 temp |= (1<<1);
1935         } else {
1936                 temp &= ~(1<<1);
1937         }
1938         WREG32(CONFIG_CNTL, temp);
1939 }
1940
1941 int r600_resume(struct radeon_device *rdev)
1942 {
1943         int r;
1944
1945         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1946          * posting will perform necessary task to bring back GPU into good
1947          * shape.
1948          */
1949         /* post card */
1950         atom_asic_init(rdev->mode_info.atom_context);
1951         /* Initialize clocks */
1952         r = radeon_clocks_init(rdev);
1953         if (r) {
1954                 return r;
1955         }
1956
1957         r = r600_startup(rdev);
1958         if (r) {
1959                 DRM_ERROR("r600 startup failed on resume\n");
1960                 return r;
1961         }
1962
1963         r = r600_ib_test(rdev);
1964         if (r) {
1965                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1966                 return r;
1967         }
1968         return r;
1969 }
1970
1971 int r600_suspend(struct radeon_device *rdev)
1972 {
1973         int r;
1974
1975         /* FIXME: we should wait for ring to be empty */
1976         r600_cp_stop(rdev);
1977         rdev->cp.ready = false;
1978         r600_irq_suspend(rdev);
1979         r600_wb_disable(rdev);
1980         r600_pcie_gart_disable(rdev);
1981         /* unpin shaders bo */
1982         if (rdev->r600_blit.shader_obj) {
1983                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1984                 if (!r) {
1985                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1986                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1987                 }
1988         }
1989         return 0;
1990 }
1991
1992 /* Plan is to move initialization in that function and use
1993  * helper function so that radeon_device_init pretty much
1994  * do nothing more than calling asic specific function. This
1995  * should also allow to remove a bunch of callback function
1996  * like vram_info.
1997  */
1998 int r600_init(struct radeon_device *rdev)
1999 {
2000         int r;
2001
2002         r = radeon_dummy_page_init(rdev);
2003         if (r)
2004                 return r;
2005         if (r600_debugfs_mc_info_init(rdev)) {
2006                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2007         }
2008         /* This don't do much */
2009         r = radeon_gem_init(rdev);
2010         if (r)
2011                 return r;
2012         /* Read BIOS */
2013         if (!radeon_get_bios(rdev)) {
2014                 if (ASIC_IS_AVIVO(rdev))
2015                         return -EINVAL;
2016         }
2017         /* Must be an ATOMBIOS */
2018         if (!rdev->is_atom_bios) {
2019                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2020                 return -EINVAL;
2021         }
2022         r = radeon_atombios_init(rdev);
2023         if (r)
2024                 return r;
2025         /* Post card if necessary */
2026         if (!r600_card_posted(rdev)) {
2027                 if (!rdev->bios) {
2028                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2029                         return -EINVAL;
2030                 }
2031                 DRM_INFO("GPU not posted. posting now...\n");
2032                 atom_asic_init(rdev->mode_info.atom_context);
2033         }
2034         /* Initialize scratch registers */
2035         r600_scratch_init(rdev);
2036         /* Initialize surface registers */
2037         radeon_surface_init(rdev);
2038         /* Initialize clocks */
2039         radeon_get_clock_info(rdev->ddev);
2040         r = radeon_clocks_init(rdev);
2041         if (r)
2042                 return r;
2043         /* Initialize power management */
2044         radeon_pm_init(rdev);
2045         /* Fence driver */
2046         r = radeon_fence_driver_init(rdev);
2047         if (r)
2048                 return r;
2049         if (rdev->flags & RADEON_IS_AGP) {
2050                 r = radeon_agp_init(rdev);
2051                 if (r)
2052                         radeon_agp_disable(rdev);
2053         }
2054         r = r600_mc_init(rdev);
2055         if (r)
2056                 return r;
2057         /* Memory manager */
2058         r = radeon_bo_init(rdev);
2059         if (r)
2060                 return r;
2061
2062         r = radeon_irq_kms_init(rdev);
2063         if (r)
2064                 return r;
2065
2066         rdev->cp.ring_obj = NULL;
2067         r600_ring_init(rdev, 1024 * 1024);
2068
2069         rdev->ih.ring_obj = NULL;
2070         r600_ih_ring_init(rdev, 64 * 1024);
2071
2072         r = r600_pcie_gart_init(rdev);
2073         if (r)
2074                 return r;
2075
2076         rdev->accel_working = true;
2077         r = r600_startup(rdev);
2078         if (r) {
2079                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2080                 r600_cp_fini(rdev);
2081                 r600_wb_fini(rdev);
2082                 r600_irq_fini(rdev);
2083                 radeon_irq_kms_fini(rdev);
2084                 r600_pcie_gart_fini(rdev);
2085                 rdev->accel_working = false;
2086         }
2087         if (rdev->accel_working) {
2088                 r = radeon_ib_pool_init(rdev);
2089                 if (r) {
2090                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2091                         rdev->accel_working = false;
2092                 } else {
2093                         r = r600_ib_test(rdev);
2094                         if (r) {
2095                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2096                                 rdev->accel_working = false;
2097                         }
2098                 }
2099         }
2100
2101         r = r600_audio_init(rdev);
2102         if (r)
2103                 return r; /* TODO error handling */
2104         return 0;
2105 }
2106
2107 void r600_fini(struct radeon_device *rdev)
2108 {
2109         r600_audio_fini(rdev);
2110         r600_blit_fini(rdev);
2111         r600_cp_fini(rdev);
2112         r600_wb_fini(rdev);
2113         r600_irq_fini(rdev);
2114         radeon_irq_kms_fini(rdev);
2115         r600_pcie_gart_fini(rdev);
2116         radeon_agp_fini(rdev);
2117         radeon_gem_fini(rdev);
2118         radeon_fence_driver_fini(rdev);
2119         radeon_clocks_fini(rdev);
2120         radeon_bo_fini(rdev);
2121         radeon_atombios_fini(rdev);
2122         kfree(rdev->bios);
2123         rdev->bios = NULL;
2124         radeon_dummy_page_fini(rdev);
2125 }
2126
2127
2128 /*
2129  * CS stuff
2130  */
2131 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2132 {
2133         /* FIXME: implement */
2134         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2135         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2136         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2137         radeon_ring_write(rdev, ib->length_dw);
2138 }
2139
2140 int r600_ib_test(struct radeon_device *rdev)
2141 {
2142         struct radeon_ib *ib;
2143         uint32_t scratch;
2144         uint32_t tmp = 0;
2145         unsigned i;
2146         int r;
2147
2148         r = radeon_scratch_get(rdev, &scratch);
2149         if (r) {
2150                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2151                 return r;
2152         }
2153         WREG32(scratch, 0xCAFEDEAD);
2154         r = radeon_ib_get(rdev, &ib);
2155         if (r) {
2156                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2157                 return r;
2158         }
2159         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2160         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2161         ib->ptr[2] = 0xDEADBEEF;
2162         ib->ptr[3] = PACKET2(0);
2163         ib->ptr[4] = PACKET2(0);
2164         ib->ptr[5] = PACKET2(0);
2165         ib->ptr[6] = PACKET2(0);
2166         ib->ptr[7] = PACKET2(0);
2167         ib->ptr[8] = PACKET2(0);
2168         ib->ptr[9] = PACKET2(0);
2169         ib->ptr[10] = PACKET2(0);
2170         ib->ptr[11] = PACKET2(0);
2171         ib->ptr[12] = PACKET2(0);
2172         ib->ptr[13] = PACKET2(0);
2173         ib->ptr[14] = PACKET2(0);
2174         ib->ptr[15] = PACKET2(0);
2175         ib->length_dw = 16;
2176         r = radeon_ib_schedule(rdev, ib);
2177         if (r) {
2178                 radeon_scratch_free(rdev, scratch);
2179                 radeon_ib_free(rdev, &ib);
2180                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2181                 return r;
2182         }
2183         r = radeon_fence_wait(ib->fence, false);
2184         if (r) {
2185                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2186                 return r;
2187         }
2188         for (i = 0; i < rdev->usec_timeout; i++) {
2189                 tmp = RREG32(scratch);
2190                 if (tmp == 0xDEADBEEF)
2191                         break;
2192                 DRM_UDELAY(1);
2193         }
2194         if (i < rdev->usec_timeout) {
2195                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2196         } else {
2197                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2198                           scratch, tmp);
2199                 r = -EINVAL;
2200         }
2201         radeon_scratch_free(rdev, scratch);
2202         radeon_ib_free(rdev, &ib);
2203         return r;
2204 }
2205
2206 /*
2207  * Interrupts
2208  *
2209  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2210  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2211  * writing to the ring and the GPU consuming, the GPU writes to the ring
2212  * and host consumes.  As the host irq handler processes interrupts, it
2213  * increments the rptr.  When the rptr catches up with the wptr, all the
2214  * current interrupts have been processed.
2215  */
2216
2217 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2218 {
2219         u32 rb_bufsz;
2220
2221         /* Align ring size */
2222         rb_bufsz = drm_order(ring_size / 4);
2223         ring_size = (1 << rb_bufsz) * 4;
2224         rdev->ih.ring_size = ring_size;
2225         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2226         rdev->ih.rptr = 0;
2227 }
2228
2229 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2230 {
2231         int r;
2232
2233         /* Allocate ring buffer */
2234         if (rdev->ih.ring_obj == NULL) {
2235                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2236                                      true,
2237                                      RADEON_GEM_DOMAIN_GTT,
2238                                      &rdev->ih.ring_obj);
2239                 if (r) {
2240                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2241                         return r;
2242                 }
2243                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2244                 if (unlikely(r != 0))
2245                         return r;
2246                 r = radeon_bo_pin(rdev->ih.ring_obj,
2247                                   RADEON_GEM_DOMAIN_GTT,
2248                                   &rdev->ih.gpu_addr);
2249                 if (r) {
2250                         radeon_bo_unreserve(rdev->ih.ring_obj);
2251                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2252                         return r;
2253                 }
2254                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2255                                    (void **)&rdev->ih.ring);
2256                 radeon_bo_unreserve(rdev->ih.ring_obj);
2257                 if (r) {
2258                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2259                         return r;
2260                 }
2261         }
2262         return 0;
2263 }
2264
2265 static void r600_ih_ring_fini(struct radeon_device *rdev)
2266 {
2267         int r;
2268         if (rdev->ih.ring_obj) {
2269                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2270                 if (likely(r == 0)) {
2271                         radeon_bo_kunmap(rdev->ih.ring_obj);
2272                         radeon_bo_unpin(rdev->ih.ring_obj);
2273                         radeon_bo_unreserve(rdev->ih.ring_obj);
2274                 }
2275                 radeon_bo_unref(&rdev->ih.ring_obj);
2276                 rdev->ih.ring = NULL;
2277                 rdev->ih.ring_obj = NULL;
2278         }
2279 }
2280
2281 static void r600_rlc_stop(struct radeon_device *rdev)
2282 {
2283
2284         if (rdev->family >= CHIP_RV770) {
2285                 /* r7xx asics need to soft reset RLC before halting */
2286                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2287                 RREG32(SRBM_SOFT_RESET);
2288                 udelay(15000);
2289                 WREG32(SRBM_SOFT_RESET, 0);
2290                 RREG32(SRBM_SOFT_RESET);
2291         }
2292
2293         WREG32(RLC_CNTL, 0);
2294 }
2295
2296 static void r600_rlc_start(struct radeon_device *rdev)
2297 {
2298         WREG32(RLC_CNTL, RLC_ENABLE);
2299 }
2300
2301 static int r600_rlc_init(struct radeon_device *rdev)
2302 {
2303         u32 i;
2304         const __be32 *fw_data;
2305
2306         if (!rdev->rlc_fw)
2307                 return -EINVAL;
2308
2309         r600_rlc_stop(rdev);
2310
2311         WREG32(RLC_HB_BASE, 0);
2312         WREG32(RLC_HB_CNTL, 0);
2313         WREG32(RLC_HB_RPTR, 0);
2314         WREG32(RLC_HB_WPTR, 0);
2315         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2316         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2317         WREG32(RLC_MC_CNTL, 0);
2318         WREG32(RLC_UCODE_CNTL, 0);
2319
2320         fw_data = (const __be32 *)rdev->rlc_fw->data;
2321         if (rdev->family >= CHIP_RV770) {
2322                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2323                         WREG32(RLC_UCODE_ADDR, i);
2324                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2325                 }
2326         } else {
2327                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2328                         WREG32(RLC_UCODE_ADDR, i);
2329                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2330                 }
2331         }
2332         WREG32(RLC_UCODE_ADDR, 0);
2333
2334         r600_rlc_start(rdev);
2335
2336         return 0;
2337 }
2338
2339 static void r600_enable_interrupts(struct radeon_device *rdev)
2340 {
2341         u32 ih_cntl = RREG32(IH_CNTL);
2342         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2343
2344         ih_cntl |= ENABLE_INTR;
2345         ih_rb_cntl |= IH_RB_ENABLE;
2346         WREG32(IH_CNTL, ih_cntl);
2347         WREG32(IH_RB_CNTL, ih_rb_cntl);
2348         rdev->ih.enabled = true;
2349 }
2350
2351 static void r600_disable_interrupts(struct radeon_device *rdev)
2352 {
2353         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2354         u32 ih_cntl = RREG32(IH_CNTL);
2355
2356         ih_rb_cntl &= ~IH_RB_ENABLE;
2357         ih_cntl &= ~ENABLE_INTR;
2358         WREG32(IH_RB_CNTL, ih_rb_cntl);
2359         WREG32(IH_CNTL, ih_cntl);
2360         /* set rptr, wptr to 0 */
2361         WREG32(IH_RB_RPTR, 0);
2362         WREG32(IH_RB_WPTR, 0);
2363         rdev->ih.enabled = false;
2364         rdev->ih.wptr = 0;
2365         rdev->ih.rptr = 0;
2366 }
2367
2368 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2369 {
2370         u32 tmp;
2371
2372         WREG32(CP_INT_CNTL, 0);
2373         WREG32(GRBM_INT_CNTL, 0);
2374         WREG32(DxMODE_INT_MASK, 0);
2375         if (ASIC_IS_DCE3(rdev)) {
2376                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2377                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2378                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2379                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2380                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2381                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2382                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2383                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2384                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2385                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2386                 if (ASIC_IS_DCE32(rdev)) {
2387                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2388                         WREG32(DC_HPD5_INT_CONTROL, 0);
2389                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2390                         WREG32(DC_HPD6_INT_CONTROL, 0);
2391                 }
2392         } else {
2393                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2394                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2395                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2396                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2397                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2398                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2399                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2400                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2401         }
2402 }
2403
2404 int r600_irq_init(struct radeon_device *rdev)
2405 {
2406         int ret = 0;
2407         int rb_bufsz;
2408         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2409
2410         /* allocate ring */
2411         ret = r600_ih_ring_alloc(rdev);
2412         if (ret)
2413                 return ret;
2414
2415         /* disable irqs */
2416         r600_disable_interrupts(rdev);
2417
2418         /* init rlc */
2419         ret = r600_rlc_init(rdev);
2420         if (ret) {
2421                 r600_ih_ring_fini(rdev);
2422                 return ret;
2423         }
2424
2425         /* setup interrupt control */
2426         /* set dummy read address to ring address */
2427         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2428         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2429         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2430          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2431          */
2432         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2433         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2434         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2435         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2436
2437         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2438         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2439
2440         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2441                       IH_WPTR_OVERFLOW_CLEAR |
2442                       (rb_bufsz << 1));
2443         /* WPTR writeback, not yet */
2444         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2445         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2446         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2447
2448         WREG32(IH_RB_CNTL, ih_rb_cntl);
2449
2450         /* set rptr, wptr to 0 */
2451         WREG32(IH_RB_RPTR, 0);
2452         WREG32(IH_RB_WPTR, 0);
2453
2454         /* Default settings for IH_CNTL (disabled at first) */
2455         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2456         /* RPTR_REARM only works if msi's are enabled */
2457         if (rdev->msi_enabled)
2458                 ih_cntl |= RPTR_REARM;
2459
2460 #ifdef __BIG_ENDIAN
2461         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2462 #endif
2463         WREG32(IH_CNTL, ih_cntl);
2464
2465         /* force the active interrupt state to all disabled */
2466         r600_disable_interrupt_state(rdev);
2467
2468         /* enable irqs */
2469         r600_enable_interrupts(rdev);
2470
2471         return ret;
2472 }
2473
2474 void r600_irq_suspend(struct radeon_device *rdev)
2475 {
2476         r600_disable_interrupts(rdev);
2477         r600_rlc_stop(rdev);
2478 }
2479
2480 void r600_irq_fini(struct radeon_device *rdev)
2481 {
2482         r600_irq_suspend(rdev);
2483         r600_ih_ring_fini(rdev);
2484 }
2485
2486 int r600_irq_set(struct radeon_device *rdev)
2487 {
2488         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2489         u32 mode_int = 0;
2490         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2491
2492         if (!rdev->irq.installed) {
2493                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2494                 return -EINVAL;
2495         }
2496         /* don't enable anything if the ih is disabled */
2497         if (!rdev->ih.enabled) {
2498                 r600_disable_interrupts(rdev);
2499                 /* force the active interrupt state to all disabled */
2500                 r600_disable_interrupt_state(rdev);
2501                 return 0;
2502         }
2503
2504         if (ASIC_IS_DCE3(rdev)) {
2505                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2506                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2507                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2508                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2509                 if (ASIC_IS_DCE32(rdev)) {
2510                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2511                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2512                 }
2513         } else {
2514                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2515                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2516                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2517         }
2518
2519         if (rdev->irq.sw_int) {
2520                 DRM_DEBUG("r600_irq_set: sw int\n");
2521                 cp_int_cntl |= RB_INT_ENABLE;
2522         }
2523         if (rdev->irq.crtc_vblank_int[0]) {
2524                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2525                 mode_int |= D1MODE_VBLANK_INT_MASK;
2526         }
2527         if (rdev->irq.crtc_vblank_int[1]) {
2528                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2529                 mode_int |= D2MODE_VBLANK_INT_MASK;
2530         }
2531         if (rdev->irq.hpd[0]) {
2532                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2533                 hpd1 |= DC_HPDx_INT_EN;
2534         }
2535         if (rdev->irq.hpd[1]) {
2536                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2537                 hpd2 |= DC_HPDx_INT_EN;
2538         }
2539         if (rdev->irq.hpd[2]) {
2540                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2541                 hpd3 |= DC_HPDx_INT_EN;
2542         }
2543         if (rdev->irq.hpd[3]) {
2544                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2545                 hpd4 |= DC_HPDx_INT_EN;
2546         }
2547         if (rdev->irq.hpd[4]) {
2548                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2549                 hpd5 |= DC_HPDx_INT_EN;
2550         }
2551         if (rdev->irq.hpd[5]) {
2552                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2553                 hpd6 |= DC_HPDx_INT_EN;
2554         }
2555
2556         WREG32(CP_INT_CNTL, cp_int_cntl);
2557         WREG32(DxMODE_INT_MASK, mode_int);
2558         if (ASIC_IS_DCE3(rdev)) {
2559                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2560                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2561                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2562                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2563                 if (ASIC_IS_DCE32(rdev)) {
2564                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2565                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2566                 }
2567         } else {
2568                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2569                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2570                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2571         }
2572
2573         return 0;
2574 }
2575
2576 static inline void r600_irq_ack(struct radeon_device *rdev,
2577                                 u32 *disp_int,
2578                                 u32 *disp_int_cont,
2579                                 u32 *disp_int_cont2)
2580 {
2581         u32 tmp;
2582
2583         if (ASIC_IS_DCE3(rdev)) {
2584                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2585                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2586                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2587         } else {
2588                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2589                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2590                 *disp_int_cont2 = 0;
2591         }
2592
2593         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2594                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2595         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2596                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2597         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2598                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2599         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2600                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2601         if (*disp_int & DC_HPD1_INTERRUPT) {
2602                 if (ASIC_IS_DCE3(rdev)) {
2603                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2604                         tmp |= DC_HPDx_INT_ACK;
2605                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2606                 } else {
2607                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2608                         tmp |= DC_HPDx_INT_ACK;
2609                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2610                 }
2611         }
2612         if (*disp_int & DC_HPD2_INTERRUPT) {
2613                 if (ASIC_IS_DCE3(rdev)) {
2614                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2615                         tmp |= DC_HPDx_INT_ACK;
2616                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2617                 } else {
2618                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2619                         tmp |= DC_HPDx_INT_ACK;
2620                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2621                 }
2622         }
2623         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2624                 if (ASIC_IS_DCE3(rdev)) {
2625                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2626                         tmp |= DC_HPDx_INT_ACK;
2627                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2628                 } else {
2629                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2630                         tmp |= DC_HPDx_INT_ACK;
2631                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2632                 }
2633         }
2634         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2635                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2636                 tmp |= DC_HPDx_INT_ACK;
2637                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2638         }
2639         if (ASIC_IS_DCE32(rdev)) {
2640                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2641                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2642                         tmp |= DC_HPDx_INT_ACK;
2643                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2644                 }
2645                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2646                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2647                         tmp |= DC_HPDx_INT_ACK;
2648                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2649                 }
2650         }
2651 }
2652
2653 void r600_irq_disable(struct radeon_device *rdev)
2654 {
2655         u32 disp_int, disp_int_cont, disp_int_cont2;
2656
2657         r600_disable_interrupts(rdev);
2658         /* Wait and acknowledge irq */
2659         mdelay(1);
2660         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2661         r600_disable_interrupt_state(rdev);
2662 }
2663
2664 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2665 {
2666         u32 wptr, tmp;
2667
2668         /* XXX use writeback */
2669         wptr = RREG32(IH_RB_WPTR);
2670
2671         if (wptr & RB_OVERFLOW) {
2672                 /* When a ring buffer overflow happen start parsing interrupt
2673                  * from the last not overwritten vector (wptr + 16). Hopefully
2674                  * this should allow us to catchup.
2675                  */
2676                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2677                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2678                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2679                 tmp = RREG32(IH_RB_CNTL);
2680                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2681                 WREG32(IH_RB_CNTL, tmp);
2682         }
2683         return (wptr & rdev->ih.ptr_mask);
2684 }
2685
2686 /*        r600 IV Ring
2687  * Each IV ring entry is 128 bits:
2688  * [7:0]    - interrupt source id
2689  * [31:8]   - reserved
2690  * [59:32]  - interrupt source data
2691  * [127:60]  - reserved
2692  *
2693  * The basic interrupt vector entries
2694  * are decoded as follows:
2695  * src_id  src_data  description
2696  *      1         0  D1 Vblank
2697  *      1         1  D1 Vline
2698  *      5         0  D2 Vblank
2699  *      5         1  D2 Vline
2700  *     19         0  FP Hot plug detection A
2701  *     19         1  FP Hot plug detection B
2702  *     19         2  DAC A auto-detection
2703  *     19         3  DAC B auto-detection
2704  *    176         -  CP_INT RB
2705  *    177         -  CP_INT IB1
2706  *    178         -  CP_INT IB2
2707  *    181         -  EOP Interrupt
2708  *    233         -  GUI Idle
2709  *
2710  * Note, these are based on r600 and may need to be
2711  * adjusted or added to on newer asics
2712  */
2713
2714 int r600_irq_process(struct radeon_device *rdev)
2715 {
2716         u32 wptr = r600_get_ih_wptr(rdev);
2717         u32 rptr = rdev->ih.rptr;
2718         u32 src_id, src_data;
2719         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2720         unsigned long flags;
2721         bool queue_hotplug = false;
2722
2723         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2724         if (!rdev->ih.enabled)
2725                 return IRQ_NONE;
2726
2727         spin_lock_irqsave(&rdev->ih.lock, flags);
2728
2729         if (rptr == wptr) {
2730                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2731                 return IRQ_NONE;
2732         }
2733         if (rdev->shutdown) {
2734                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2735                 return IRQ_NONE;
2736         }
2737
2738 restart_ih:
2739         /* display interrupts */
2740         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2741
2742         rdev->ih.wptr = wptr;
2743         while (rptr != wptr) {
2744                 /* wptr/rptr are in bytes! */
2745                 ring_index = rptr / 4;
2746                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2747                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2748
2749                 switch (src_id) {
2750                 case 1: /* D1 vblank/vline */
2751                         switch (src_data) {
2752                         case 0: /* D1 vblank */
2753                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2754                                         drm_handle_vblank(rdev->ddev, 0);
2755                                         wake_up(&rdev->irq.vblank_queue);
2756                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2757                                         DRM_DEBUG("IH: D1 vblank\n");
2758                                 }
2759                                 break;
2760                         case 1: /* D1 vline */
2761                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2762                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2763                                         DRM_DEBUG("IH: D1 vline\n");
2764                                 }
2765                                 break;
2766                         default:
2767                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2768                                 break;
2769                         }
2770                         break;
2771                 case 5: /* D2 vblank/vline */
2772                         switch (src_data) {
2773                         case 0: /* D2 vblank */
2774                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2775                                         drm_handle_vblank(rdev->ddev, 1);
2776                                         wake_up(&rdev->irq.vblank_queue);
2777                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2778                                         DRM_DEBUG("IH: D2 vblank\n");
2779                                 }
2780                                 break;
2781                         case 1: /* D1 vline */
2782                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2783                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2784                                         DRM_DEBUG("IH: D2 vline\n");
2785                                 }
2786                                 break;
2787                         default:
2788                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2789                                 break;
2790                         }
2791                         break;
2792                 case 19: /* HPD/DAC hotplug */
2793                         switch (src_data) {
2794                         case 0:
2795                                 if (disp_int & DC_HPD1_INTERRUPT) {
2796                                         disp_int &= ~DC_HPD1_INTERRUPT;
2797                                         queue_hotplug = true;
2798                                         DRM_DEBUG("IH: HPD1\n");
2799                                 }
2800                                 break;
2801                         case 1:
2802                                 if (disp_int & DC_HPD2_INTERRUPT) {
2803                                         disp_int &= ~DC_HPD2_INTERRUPT;
2804                                         queue_hotplug = true;
2805                                         DRM_DEBUG("IH: HPD2\n");
2806                                 }
2807                                 break;
2808                         case 4:
2809                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2810                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2811                                         queue_hotplug = true;
2812                                         DRM_DEBUG("IH: HPD3\n");
2813                                 }
2814                                 break;
2815                         case 5:
2816                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2817                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2818                                         queue_hotplug = true;
2819                                         DRM_DEBUG("IH: HPD4\n");
2820                                 }
2821                                 break;
2822                         case 10:
2823                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2824                                         disp_int_cont &= ~DC_HPD5_INTERRUPT;
2825                                         queue_hotplug = true;
2826                                         DRM_DEBUG("IH: HPD5\n");
2827                                 }
2828                                 break;
2829                         case 12:
2830                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2831                                         disp_int_cont &= ~DC_HPD6_INTERRUPT;
2832                                         queue_hotplug = true;
2833                                         DRM_DEBUG("IH: HPD6\n");
2834                                 }
2835                                 break;
2836                         default:
2837                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2838                                 break;
2839                         }
2840                         break;
2841                 case 176: /* CP_INT in ring buffer */
2842                 case 177: /* CP_INT in IB1 */
2843                 case 178: /* CP_INT in IB2 */
2844                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2845                         radeon_fence_process(rdev);
2846                         break;
2847                 case 181: /* CP EOP event */
2848                         DRM_DEBUG("IH: CP EOP\n");
2849                         break;
2850                 default:
2851                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2852                         break;
2853                 }
2854
2855                 /* wptr/rptr are in bytes! */
2856                 rptr += 16;
2857                 rptr &= rdev->ih.ptr_mask;
2858         }
2859         /* make sure wptr hasn't changed while processing */
2860         wptr = r600_get_ih_wptr(rdev);
2861         if (wptr != rdev->ih.wptr)
2862                 goto restart_ih;
2863         if (queue_hotplug)
2864                 queue_work(rdev->wq, &rdev->hotplug_work);
2865         rdev->ih.rptr = rptr;
2866         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2867         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2868         return IRQ_HANDLED;
2869 }
2870
2871 /*
2872  * Debugfs info
2873  */
2874 #if defined(CONFIG_DEBUG_FS)
2875
2876 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2877 {
2878         struct drm_info_node *node = (struct drm_info_node *) m->private;
2879         struct drm_device *dev = node->minor->dev;
2880         struct radeon_device *rdev = dev->dev_private;
2881         unsigned count, i, j;
2882
2883         radeon_ring_free_size(rdev);
2884         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2885         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2886         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2887         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2888         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2889         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2890         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2891         seq_printf(m, "%u dwords in ring\n", count);
2892         i = rdev->cp.rptr;
2893         for (j = 0; j <= count; j++) {
2894                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2895                 i = (i + 1) & rdev->cp.ptr_mask;
2896         }
2897         return 0;
2898 }
2899
2900 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2901 {
2902         struct drm_info_node *node = (struct drm_info_node *) m->private;
2903         struct drm_device *dev = node->minor->dev;
2904         struct radeon_device *rdev = dev->dev_private;
2905
2906         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2907         DREG32_SYS(m, rdev, VM_L2_STATUS);
2908         return 0;
2909 }
2910
2911 static struct drm_info_list r600_mc_info_list[] = {
2912         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2913         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2914 };
2915 #endif
2916
2917 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2918 {
2919 #if defined(CONFIG_DEBUG_FS)
2920         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2921 #else
2922         return 0;
2923 #endif
2924 }
2925
2926 /**
2927  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2928  * rdev: radeon device structure
2929  * bo: buffer object struct which userspace is waiting for idle
2930  *
2931  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2932  * through ring buffer, this leads to corruption in rendering, see
2933  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2934  * directly perform HDP flush by writing register through MMIO.
2935  */
2936 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2937 {
2938         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2939 }