2 * pdc_adma.c - Pacific Digital Corporation ADMA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Mark Lord
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/gfp.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/blkdev.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <linux/libata.h>
47 #define DRV_NAME "pdc_adma"
48 #define DRV_VERSION "1.0"
50 /* macro to calculate base address for ATA regs */
51 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
53 /* macro to calculate base address for ADMA regs */
54 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
56 /* macro to obtain addresses from ata_port */
57 #define ADMA_PORT_REGS(ap) \
58 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
65 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
66 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
68 ADMA_DMA_BOUNDARY = 0xffffffff,
70 /* global register offsets */
71 ADMA_MODE_LOCK = 0x00c7,
73 /* per-channel register offsets */
74 ADMA_CONTROL = 0x0000, /* ADMA control */
75 ADMA_STATUS = 0x0002, /* ADMA status */
76 ADMA_CPB_COUNT = 0x0004, /* CPB count */
77 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
78 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
79 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
80 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
81 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
83 /* ADMA_CONTROL register bits */
84 aNIEN = (1 << 8), /* irq mask: 1==masked */
85 aGO = (1 << 7), /* packet trigger ("Go!") */
86 aRSTADM = (1 << 5), /* ADMA logic reset */
87 aPIOMD4 = 0x0003, /* PIO mode 4 */
89 /* ADMA_STATUS register bits */
107 /* ATA register flags */
111 /* ATA register addresses */
112 ADMA_REGS_CONTROL = 0x0e,
113 ADMA_REGS_SECTOR_COUNT = 0x12,
114 ADMA_REGS_LBA_LOW = 0x13,
115 ADMA_REGS_LBA_MID = 0x14,
116 ADMA_REGS_LBA_HIGH = 0x15,
117 ADMA_REGS_DEVICE = 0x16,
118 ADMA_REGS_COMMAND = 0x17,
121 board_1841_idx = 0, /* ADMA 2-port controller */
124 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
126 struct adma_port_priv {
132 static int adma_ata_init_one(struct pci_dev *pdev,
133 const struct pci_device_id *ent);
134 static int adma_port_start(struct ata_port *ap);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_freeze(struct ata_port *ap);
140 static void adma_thaw(struct ata_port *ap);
141 static int adma_prereset(struct ata_link *link, unsigned long deadline);
143 static struct scsi_host_template adma_ata_sht = {
144 ATA_BASE_SHT(DRV_NAME),
145 .sg_tablesize = LIBATA_MAX_PRD,
146 .dma_boundary = ADMA_DMA_BOUNDARY,
149 static struct ata_port_operations adma_ata_ops = {
150 .inherits = &ata_sff_port_ops,
152 .lost_interrupt = ATA_OP_NULL,
154 .check_atapi_dma = adma_check_atapi_dma,
155 .qc_prep = adma_qc_prep,
156 .qc_issue = adma_qc_issue,
158 .freeze = adma_freeze,
160 .prereset = adma_prereset,
162 .port_start = adma_port_start,
163 .port_stop = adma_port_stop,
166 static struct ata_port_info adma_port_info[] = {
169 .flags = ATA_FLAG_SLAVE_POSS |
170 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
171 ATA_FLAG_PIO_POLLING,
172 .pio_mask = ATA_PIO4_ONLY,
173 .udma_mask = ATA_UDMA4,
174 .port_ops = &adma_ata_ops,
178 static const struct pci_device_id adma_ata_pci_tbl[] = {
179 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
181 { } /* terminate list */
184 static struct pci_driver adma_ata_pci_driver = {
186 .id_table = adma_ata_pci_tbl,
187 .probe = adma_ata_init_one,
188 .remove = ata_pci_remove_one,
191 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
193 return 1; /* ATAPI DMA not yet supported */
196 static void adma_reset_engine(struct ata_port *ap)
198 void __iomem *chan = ADMA_PORT_REGS(ap);
200 /* reset ADMA to idle state */
201 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
203 writew(aPIOMD4, chan + ADMA_CONTROL);
207 static void adma_reinit_engine(struct ata_port *ap)
209 struct adma_port_priv *pp = ap->private_data;
210 void __iomem *chan = ADMA_PORT_REGS(ap);
212 /* mask/clear ATA interrupts */
213 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
214 ata_sff_check_status(ap);
216 /* reset the ADMA engine */
217 adma_reset_engine(ap);
219 /* set in-FIFO threshold to 0x100 */
220 writew(0x100, chan + ADMA_FIFO_IN);
222 /* set CPB pointer */
223 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
225 /* set out-FIFO threshold to 0x100 */
226 writew(0x100, chan + ADMA_FIFO_OUT);
229 writew(1, chan + ADMA_CPB_COUNT);
231 /* read/discard ADMA status */
232 readb(chan + ADMA_STATUS);
235 static inline void adma_enter_reg_mode(struct ata_port *ap)
237 void __iomem *chan = ADMA_PORT_REGS(ap);
239 writew(aPIOMD4, chan + ADMA_CONTROL);
240 readb(chan + ADMA_STATUS); /* flush */
243 static void adma_freeze(struct ata_port *ap)
245 void __iomem *chan = ADMA_PORT_REGS(ap);
247 /* mask/clear ATA interrupts */
248 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
249 ata_sff_check_status(ap);
251 /* reset ADMA to idle state */
252 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
254 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
258 static void adma_thaw(struct ata_port *ap)
260 adma_reinit_engine(ap);
263 static int adma_prereset(struct ata_link *link, unsigned long deadline)
265 struct ata_port *ap = link->ap;
266 struct adma_port_priv *pp = ap->private_data;
268 if (pp->state != adma_state_idle) /* healthy paranoia */
269 pp->state = adma_state_mmio;
270 adma_reinit_engine(ap);
272 return ata_sff_prereset(link, deadline);
275 static int adma_fill_sg(struct ata_queued_cmd *qc)
277 struct scatterlist *sg;
278 struct ata_port *ap = qc->ap;
279 struct adma_port_priv *pp = ap->private_data;
280 u8 *buf = pp->pkt, *last_buf = NULL;
281 int i = (2 + buf[3]) * 8;
282 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
285 for_each_sg(qc->sg, sg, qc->n_elem, si) {
289 addr = (u32)sg_dma_address(sg);
290 *(__le32 *)(buf + i) = cpu_to_le32(addr);
293 len = sg_dma_len(sg) >> 3;
294 *(__le32 *)(buf + i) = cpu_to_le32(len);
299 buf[i++] = qc->dev->dma_mode & 0xf;
300 buf[i++] = 0; /* pPKLW */
301 buf[i++] = 0; /* reserved */
303 *(__le32 *)(buf + i) =
304 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
307 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
308 (unsigned long)addr, len);
311 if (likely(last_buf))
317 static void adma_qc_prep(struct ata_queued_cmd *qc)
319 struct adma_port_priv *pp = qc->ap->private_data;
321 u32 pkt_dma = (u32)pp->pkt_dma;
326 adma_enter_reg_mode(qc->ap);
327 if (qc->tf.protocol != ATA_PROT_DMA) {
332 buf[i++] = 0; /* Response flags */
333 buf[i++] = 0; /* reserved */
334 buf[i++] = cVLD | cDAT | cIEN;
335 i++; /* cLEN, gets filled in below */
337 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
339 i += 4; /* cPRD, gets filled in below */
341 buf[i++] = 0; /* reserved */
342 buf[i++] = 0; /* reserved */
343 buf[i++] = 0; /* reserved */
344 buf[i++] = 0; /* reserved */
346 /* ATA registers; must be a multiple of 4 */
347 buf[i++] = qc->tf.device;
348 buf[i++] = ADMA_REGS_DEVICE;
349 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
350 buf[i++] = qc->tf.hob_nsect;
351 buf[i++] = ADMA_REGS_SECTOR_COUNT;
352 buf[i++] = qc->tf.hob_lbal;
353 buf[i++] = ADMA_REGS_LBA_LOW;
354 buf[i++] = qc->tf.hob_lbam;
355 buf[i++] = ADMA_REGS_LBA_MID;
356 buf[i++] = qc->tf.hob_lbah;
357 buf[i++] = ADMA_REGS_LBA_HIGH;
359 buf[i++] = qc->tf.nsect;
360 buf[i++] = ADMA_REGS_SECTOR_COUNT;
361 buf[i++] = qc->tf.lbal;
362 buf[i++] = ADMA_REGS_LBA_LOW;
363 buf[i++] = qc->tf.lbam;
364 buf[i++] = ADMA_REGS_LBA_MID;
365 buf[i++] = qc->tf.lbah;
366 buf[i++] = ADMA_REGS_LBA_HIGH;
368 buf[i++] = ADMA_REGS_CONTROL;
371 buf[i++] = qc->tf.command;
372 buf[i++] = ADMA_REGS_COMMAND | rEND;
374 buf[3] = (i >> 3) - 2; /* cLEN */
375 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
377 i = adma_fill_sg(qc);
378 wmb(); /* flush PRDs and pkt to memory */
380 /* dump out CPB + PRDs for debug */
383 static char obuf[2048];
384 for (j = 0; j < i; ++j) {
385 len += sprintf(obuf+len, "%02x ", buf[j]);
387 printk("%s\n", obuf);
392 printk("%s\n", obuf);
397 static inline void adma_packet_start(struct ata_queued_cmd *qc)
399 struct ata_port *ap = qc->ap;
400 void __iomem *chan = ADMA_PORT_REGS(ap);
402 VPRINTK("ENTER, ap %p\n", ap);
404 /* fire up the ADMA engine */
405 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
408 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
410 struct adma_port_priv *pp = qc->ap->private_data;
412 switch (qc->tf.protocol) {
414 pp->state = adma_state_pkt;
415 adma_packet_start(qc);
426 pp->state = adma_state_mmio;
427 return ata_sff_qc_issue(qc);
430 static inline unsigned int adma_intr_pkt(struct ata_host *host)
432 unsigned int handled = 0, port_no;
434 for (port_no = 0; port_no < host->n_ports; ++port_no) {
435 struct ata_port *ap = host->ports[port_no];
436 struct adma_port_priv *pp;
437 struct ata_queued_cmd *qc;
438 void __iomem *chan = ADMA_PORT_REGS(ap);
439 u8 status = readb(chan + ADMA_STATUS);
444 adma_enter_reg_mode(ap);
445 pp = ap->private_data;
446 if (!pp || pp->state != adma_state_pkt)
448 qc = ata_qc_from_tag(ap, ap->link.active_tag);
449 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
451 qc->err_mask |= AC_ERR_HOST_BUS;
452 else if ((status & (aPSD | aUIRQ)))
453 qc->err_mask |= AC_ERR_OTHER;
455 if (pp->pkt[0] & cATERR)
456 qc->err_mask |= AC_ERR_DEV;
457 else if (pp->pkt[0] != cDONE)
458 qc->err_mask |= AC_ERR_OTHER;
463 struct ata_eh_info *ehi = &ap->link.eh_info;
464 ata_ehi_clear_desc(ehi);
465 ata_ehi_push_desc(ehi,
466 "ADMA-status 0x%02X", status);
467 ata_ehi_push_desc(ehi,
468 "pkt[0] 0x%02X", pp->pkt[0]);
470 if (qc->err_mask == AC_ERR_DEV)
480 static inline unsigned int adma_intr_mmio(struct ata_host *host)
482 unsigned int handled = 0, port_no;
484 for (port_no = 0; port_no < host->n_ports; ++port_no) {
485 struct ata_port *ap = host->ports[port_no];
486 struct adma_port_priv *pp = ap->private_data;
487 struct ata_queued_cmd *qc;
489 if (!pp || pp->state != adma_state_mmio)
491 qc = ata_qc_from_tag(ap, ap->link.active_tag);
492 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
494 /* check main status, clearing INTRQ */
495 u8 status = ata_sff_check_status(ap);
496 if ((status & ATA_BUSY))
498 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
499 ap->print_id, qc->tf.protocol, status);
501 /* complete taskfile transaction */
502 pp->state = adma_state_idle;
503 qc->err_mask |= ac_err_mask(status);
507 struct ata_eh_info *ehi = &ap->link.eh_info;
508 ata_ehi_clear_desc(ehi);
509 ata_ehi_push_desc(ehi, "status 0x%02X", status);
511 if (qc->err_mask == AC_ERR_DEV)
522 static irqreturn_t adma_intr(int irq, void *dev_instance)
524 struct ata_host *host = dev_instance;
525 unsigned int handled = 0;
529 spin_lock(&host->lock);
530 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
531 spin_unlock(&host->lock);
535 return IRQ_RETVAL(handled);
538 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
541 port->data_addr = base + 0x000;
543 port->feature_addr = base + 0x004;
544 port->nsect_addr = base + 0x008;
545 port->lbal_addr = base + 0x00c;
546 port->lbam_addr = base + 0x010;
547 port->lbah_addr = base + 0x014;
548 port->device_addr = base + 0x018;
550 port->command_addr = base + 0x01c;
551 port->altstatus_addr =
552 port->ctl_addr = base + 0x038;
555 static int adma_port_start(struct ata_port *ap)
557 struct device *dev = ap->host->dev;
558 struct adma_port_priv *pp;
560 adma_enter_reg_mode(ap);
561 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
564 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
569 if ((pp->pkt_dma & 7) != 0) {
570 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
574 memset(pp->pkt, 0, ADMA_PKT_BYTES);
575 ap->private_data = pp;
576 adma_reinit_engine(ap);
580 static void adma_port_stop(struct ata_port *ap)
582 adma_reset_engine(ap);
585 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
587 unsigned int port_no;
589 /* enable/lock aGO operation */
590 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
592 /* reset the ADMA logic */
593 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
594 adma_reset_engine(host->ports[port_no]);
597 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
601 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
603 dev_printk(KERN_ERR, &pdev->dev,
604 "32-bit DMA enable failed\n");
607 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
609 dev_printk(KERN_ERR, &pdev->dev,
610 "32-bit consistent DMA enable failed\n");
616 static int adma_ata_init_one(struct pci_dev *pdev,
617 const struct pci_device_id *ent)
619 static int printed_version;
620 unsigned int board_idx = (unsigned int) ent->driver_data;
621 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
622 struct ata_host *host;
623 void __iomem *mmio_base;
626 if (!printed_version++)
627 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
630 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
634 /* acquire resources and fill host */
635 rc = pcim_enable_device(pdev);
639 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
642 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
645 host->iomap = pcim_iomap_table(pdev);
646 mmio_base = host->iomap[ADMA_MMIO_BAR];
648 rc = adma_set_dma_masks(pdev, mmio_base);
652 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
653 struct ata_port *ap = host->ports[port_no];
654 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
655 unsigned int offset = port_base - mmio_base;
657 adma_ata_setup_port(&ap->ioaddr, port_base);
659 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
660 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
663 /* initialize adapter */
664 adma_host_init(host, board_idx);
666 pci_set_master(pdev);
667 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
671 static int __init adma_ata_init(void)
673 return pci_register_driver(&adma_ata_pci_driver);
676 static void __exit adma_ata_exit(void)
678 pci_unregister_driver(&adma_ata_pci_driver);
681 MODULE_AUTHOR("Mark Lord");
682 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
683 MODULE_LICENSE("GPL");
684 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
685 MODULE_VERSION(DRV_VERSION);
687 module_init(adma_ata_init);
688 module_exit(adma_ata_exit);