sata_sil24: fix kernel panic on ARM caused by unaligned access in sata_sil24

The sata_sil24 driver has six 16-bit registers that are initialised with
32-bit writes. This cause a kernel panic on ARM due to the unaligned
accesses which result.

This patch changes the accesses to the correct 16-bit ones.

Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index e925051..70b58fe 100644 (file)
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -539,12 +539,12 @@ static void sil24_config_port(struct ata_port *ap)
                writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
 
        /* zero error counters. */
-       writel(0x8000, port + PORT_DECODE_ERR_THRESH);
-       writel(0x8000, port + PORT_CRC_ERR_THRESH);
-       writel(0x8000, port + PORT_HSHK_ERR_THRESH);
-       writel(0x0000, port + PORT_DECODE_ERR_CNT);
-       writel(0x0000, port + PORT_CRC_ERR_CNT);
-       writel(0x0000, port + PORT_HSHK_ERR_CNT);
+       writew(0x8000, port + PORT_DECODE_ERR_THRESH);
+       writew(0x8000, port + PORT_CRC_ERR_THRESH);
+       writew(0x8000, port + PORT_HSHK_ERR_THRESH);
+       writew(0x0000, port + PORT_DECODE_ERR_CNT);
+       writew(0x0000, port + PORT_CRC_ERR_CNT);
+       writew(0x0000, port + PORT_HSHK_ERR_CNT);
 
        /* always use 64bit activation */
        writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);