drm/radeon/kms: fix vram_width calculation on r6xx/r7xx
authorAlex Deucher <alexdeucher@gmail.com>
Mon, 19 Oct 2009 21:23:33 +0000 (17:23 -0400)
committerDave Airlie <airlied@redhat.com>
Mon, 26 Oct 2009 03:28:19 +0000 (13:28 +1000)
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600d.h
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/rv770d.h

index 1b5aa1f..e87475c 100644 (file)
@@ -339,11 +339,10 @@ int r600_mc_init(struct radeon_device *rdev)
 {
        fixed20_12 a;
        u32 tmp;
-       int chansize;
+       int chansize, numchan;
        int r;
 
        /* Get VRAM informations */
-       rdev->mc.vram_width = 128;
        rdev->mc.vram_is_ddr = true;
        tmp = RREG32(RAMCFG);
        if (tmp & CHANSIZE_OVERRIDE) {
@@ -353,17 +352,23 @@ int r600_mc_init(struct radeon_device *rdev)
        } else {
                chansize = 32;
        }
-       if (rdev->family == CHIP_R600) {
-               rdev->mc.vram_width = 8 * chansize;
-       } else if (rdev->family == CHIP_RV670) {
-               rdev->mc.vram_width = 4 * chansize;
-       } else if ((rdev->family == CHIP_RV610) ||
-                       (rdev->family == CHIP_RV620)) {
-               rdev->mc.vram_width = chansize;
-       } else if ((rdev->family == CHIP_RV630) ||
-                       (rdev->family == CHIP_RV635)) {
-               rdev->mc.vram_width = 2 * chansize;
+       tmp = RREG32(CHMAP);
+       switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+       case 0:
+       default:
+               numchan = 1;
+               break;
+       case 1:
+               numchan = 2;
+               break;
+       case 2:
+               numchan = 4;
+               break;
+       case 3:
+               numchan = 8;
+               break;
        }
+       rdev->mc.vram_width = numchan * chansize;
        /* Could aper size report 0 ? */
        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
index 5084595..cf238bf 100644 (file)
 #define        PCIE_PORT_INDEX                                 0x0038
 #define        PCIE_PORT_DATA                                  0x003C
 
+#define CHMAP                                          0x2004
+#define                NOOFCHAN_SHIFT                                  12
+#define                NOOFCHAN_MASK                                   0x00003000
+
 #define RAMCFG                                         0x2408
 #define                NOOFBANK_SHIFT                                  0
 #define                NOOFBANK_MASK                                   0x00000001
index 595ac63..4055391 100644 (file)
@@ -774,14 +774,36 @@ int rv770_mc_init(struct radeon_device *rdev)
 {
        fixed20_12 a;
        u32 tmp;
+       int chansize, numchan;
        int r;
 
        /* Get VRAM informations */
-       /* FIXME: Don't know how to determine vram width, need to check
-        * vram_width usage
-        */
-       rdev->mc.vram_width = 128;
        rdev->mc.vram_is_ddr = true;
+       tmp = RREG32(MC_ARB_RAMCFG);
+       if (tmp & CHANSIZE_OVERRIDE) {
+               chansize = 16;
+       } else if (tmp & CHANSIZE_MASK) {
+               chansize = 64;
+       } else {
+               chansize = 32;
+       }
+       tmp = RREG32(MC_SHARED_CHMAP);
+       switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+       case 0:
+       default:
+               numchan = 1;
+               break;
+       case 1:
+               numchan = 2;
+               break;
+       case 2:
+               numchan = 4;
+               break;
+       case 3:
+               numchan = 8;
+               break;
+       }
+       rdev->mc.vram_width = numchan * chansize;
        /* Could aper size report 0 ? */
        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
index 4b9c3d6..a1367ab 100644 (file)
 #define HDP_REG_COHERENCY_FLUSH_CNTL                   0x54A0
 #define        HDP_TILING_CONFIG                               0x2F3C
 
+#define MC_SHARED_CHMAP                                                0x2004
+#define                NOOFCHAN_SHIFT                                  12
+#define                NOOFCHAN_MASK                                   0x00003000
+
 #define        MC_ARB_RAMCFG                                   0x2760
 #define                NOOFBANK_SHIFT                                  0
 #define                NOOFBANK_MASK                                   0x00000003
 #define                CHANSIZE_MASK                                   0x00000100
 #define                BURSTLENGTH_SHIFT                               9
 #define                BURSTLENGTH_MASK                                0x00000200
+#define                CHANSIZE_OVERRIDE                               (1 << 11)
 #define        MC_VM_AGP_TOP                                   0x2028
 #define        MC_VM_AGP_BOT                                   0x202C
 #define        MC_VM_AGP_BASE                                  0x2030