Blackfin: cpufreq: use a constant latency
authorMichael Hennerich <michael.hennerich@analog.com>
Fri, 25 Sep 2009 09:03:21 +0000 (09:03 +0000)
committerMike Frysinger <vapier@gentoo.org>
Tue, 15 Dec 2009 05:14:00 +0000 (00:14 -0500)
commitd887a1ce285f03c689bb4fbbaf574160bb484c3e
treecb1bfea50d25294c7a4c1c886f1b0b5aab743016
parent21b03cfe4c50fd586bfebd06d852457c07f60c2b
Blackfin: cpufreq: use a constant latency

PLL_LOCKCNT applies only to the PLL programming sequence which does not
apply to core and system clock dividers.  Writes to PLL_DIV to change the
CSEL/SSEL dividers take effect immediately.

There is still overhead in software in writing the new dividers, so just
use a value of 50us as this should be good enough.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
arch/blackfin/mach-common/cpufreq.c