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(parent: e270846) | patch
drm/i915: Write zero to DPLL_MD Reg for non-SDVO output
authorZhao Yakui <yakui.zhao@intel.com>
Thu, 10 Sep 2009 07:45:49 +0000 (15:45 +0800)
committerEric Anholt <eric@anholt.net>
Thu, 10 Sep 2009 18:31:04 +0000 (11:31 -0700)
commitbb66c5122b4300b475b585fffb811311f39f5431
tree0d356b75e3d0e9002bf40df02b400bc137e8b4f3tree | snapshot
parente270846fa7c350712553d767e61cf8b3bbfbd58acommit | diff
drm/i915: Write zero to DPLL_MD Reg for non-SDVO output

When the output device is LVDS, maybe the pixel clock of adjusted_mode will be
less than that in mode. In such case it will set the incorrect multipler factor
in DPLL_MD register.
So the dpll_md_reg will be reset when the output type is non-SDVO

https://bugs.freedesktop.org/show_bug.cgi?id=22761

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewd-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
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