#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/pagemap.h>
-#include <linux/version.h>
#include <asm/io.h>
#include "intelfb.h"
#include "intelfbhw.h"
+struct pll_min_max {
+ int min_m, max_m;
+ int min_m1, max_m1;
+ int min_m2, max_m2;
+ int min_n, max_n;
+ int min_p, max_p;
+ int min_p1, max_p1;
+ int min_vco, max_vco;
+ int p_transition_clk, ref_clk;
+ int p_inc_lo, p_inc_hi;
+};
+
+#define PLLS_I8xx 0
+#define PLLS_I9xx 1
+#define PLLS_MAX 2
+
+static struct pll_min_max plls[PLLS_MAX] = {
+ { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 48000, 4, 22 }, //I8xx
+ { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 96000, 10, 5 } //I9xx
+};
+
int
-intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
- int *mobile)
+intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
{
u32 tmp;
-
- if (!pdev || !name || !chipset || !mobile)
+ if (!pdev || !dinfo)
return 1;
switch (pdev->device) {
case PCI_DEVICE_ID_INTEL_830M:
- *name = "Intel(R) 830M";
- *chipset = INTEL_830M;
- *mobile = 1;
+ dinfo->name = "Intel(R) 830M";
+ dinfo->chipset = INTEL_830M;
+ dinfo->mobile = 1;
+ dinfo->pll_index = PLLS_I8xx;
return 0;
case PCI_DEVICE_ID_INTEL_845G:
- *name = "Intel(R) 845G";
- *chipset = INTEL_845G;
- *mobile = 0;
+ dinfo->name = "Intel(R) 845G";
+ dinfo->chipset = INTEL_845G;
+ dinfo->mobile = 0;
+ dinfo->pll_index = PLLS_I8xx;
return 0;
case PCI_DEVICE_ID_INTEL_85XGM:
tmp = 0;
- *mobile = 1;
+ dinfo->mobile = 1;
+ dinfo->pll_index = PLLS_I8xx;
pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
INTEL_85X_VARIANT_MASK) {
case INTEL_VAR_855GME:
- *name = "Intel(R) 855GME";
- *chipset = INTEL_855GME;
+ dinfo->name = "Intel(R) 855GME";
+ dinfo->chipset = INTEL_855GME;
return 0;
case INTEL_VAR_855GM:
- *name = "Intel(R) 855GM";
- *chipset = INTEL_855GM;
+ dinfo->name = "Intel(R) 855GM";
+ dinfo->chipset = INTEL_855GM;
return 0;
case INTEL_VAR_852GME:
- *name = "Intel(R) 852GME";
- *chipset = INTEL_852GME;
+ dinfo->name = "Intel(R) 852GME";
+ dinfo->chipset = INTEL_852GME;
return 0;
case INTEL_VAR_852GM:
- *name = "Intel(R) 852GM";
- *chipset = INTEL_852GM;
+ dinfo->name = "Intel(R) 852GM";
+ dinfo->chipset = INTEL_852GM;
return 0;
default:
- *name = "Intel(R) 852GM/855GM";
- *chipset = INTEL_85XGM;
+ dinfo->name = "Intel(R) 852GM/855GM";
+ dinfo->chipset = INTEL_85XGM;
return 0;
}
break;
case PCI_DEVICE_ID_INTEL_865G:
- *name = "Intel(R) 865G";
- *chipset = INTEL_865G;
- *mobile = 0;
+ dinfo->name = "Intel(R) 865G";
+ dinfo->chipset = INTEL_865G;
+ dinfo->mobile = 0;
+ dinfo->pll_index = PLLS_I8xx;
return 0;
case PCI_DEVICE_ID_INTEL_915G:
- *name = "Intel(R) 915G";
- *chipset = INTEL_915G;
- *mobile = 0;
+ dinfo->name = "Intel(R) 915G";
+ dinfo->chipset = INTEL_915G;
+ dinfo->mobile = 0;
+ dinfo->pll_index = PLLS_I9xx;
return 0;
case PCI_DEVICE_ID_INTEL_915GM:
- *name = "Intel(R) 915GM";
- *chipset = INTEL_915GM;
- *mobile = 1;
+ dinfo->name = "Intel(R) 915GM";
+ dinfo->chipset = INTEL_915GM;
+ dinfo->mobile = 1;
+ dinfo->pll_index = PLLS_I9xx;
+ return 0;
+ case PCI_DEVICE_ID_INTEL_945G:
+ dinfo->name = "Intel(R) 945G";
+ dinfo->chipset = INTEL_945G;
+ dinfo->mobile = 0;
+ dinfo->pll_index = PLLS_I9xx;
+ return 0;
+ case PCI_DEVICE_ID_INTEL_945GM:
+ dinfo->name = "Intel(R) 945GM";
+ dinfo->chipset = INTEL_945GM;
+ dinfo->mobile = 1;
+ dinfo->pll_index = PLLS_I9xx;
return 0;
default:
return 1;
}
+static int calc_vclock3(int index, int m, int n, int p)
+{
+ if (p == 0 || n == 0)
+ return 0;
+ return plls[index].ref_clk * m / n / p;
+}
+
+static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
+{
+ int p2_val;
+ switch(index)
+ {
+ case PLLS_I9xx:
+ if (p1 == 0)
+ return 0;
+ if (lvds)
+ p2_val = p2 ? 7 : 14;
+ else
+ p2_val = p2 ? 5 : 10;
+ return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
+ ((p1)) * (p2_val)));
+ case PLLS_I8xx:
+ default:
+ return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
+ ((p1+2) * (1 << (p2 + 1)))));
+ }
+}
+
void
intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
{
#if REGDUMP
int i, m1, m2, n, p1, p2;
-
+ int index = dinfo->pll_index;
DBG_MSG("intelfbhw_print_hw_state\n");
if (!hw || !dinfo)
p1 = 0;
else
p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
+
p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
+
printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
+ m1, m2, n, p1, p2);
+ printk(" VGA0: clock is %d\n",
+ calc_vclock(index, m1, m2, n, p1, p2, 0));
n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
+ m1, m2, n, p1, p2);
+ printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+
+ if (IS_I9XX(dinfo)) {
+ int tmpp1;
+
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
+
+ tmpp1 = p1;
+
+ switch (tmpp1)
+ {
+ case 0x1: p1 = 1; break;
+ case 0x2: p1 = 2; break;
+ case 0x4: p1 = 3; break;
+ case 0x8: p1 = 4; break;
+ case 0x10: p1 = 5; break;
+ case 0x20: p1 = 6; break;
+ case 0x40: p1 = 7; break;
+ case 0x80: p1 = 8; break;
+ default: break;
+ }
+
+ p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+
+ } else {
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
+ p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+ }
+
printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
+ m1, m2, n, p1, p2);
+ printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+
+ if (IS_I9XX(dinfo)) {
+ int tmpp1;
+
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
+
+ tmpp1 = p1;
+
+ switch (tmpp1)
+ {
+ case 0x1: p1 = 1; break;
+ case 0x2: p1 = 2; break;
+ case 0x4: p1 = 3; break;
+ case 0x8: p1 = 4; break;
+ case 0x10: p1 = 5; break;
+ case 0x20: p1 = 6; break;
+ case 0x40: p1 = 7; break;
+ case 0x80: p1 = 8; break;
+ default: break;
+ }
+
+ p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+
+ } else {
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
+ p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+ }
printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
- m1, m2, n, p1, p2);
- printk(" PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
+ m1, m2, n, p1, p2);
+ printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
#if 0
printk(" PALETTE_A:\n");
for (i = 0; i < PALETTE_8_ENTRIES)
- printk(" %3d: 0x%08x\n", i, hw->palette_a[i];
+ printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
printk(" PALETTE_B:\n");
for (i = 0; i < PALETTE_8_ENTRIES)
- printk(" %3d: 0x%08x\n", i, hw->palette_b[i];
+ printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
#endif
printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
}
for (i = 0; i < 3; i++) {
printk(" SWF3%d 0x%08x\n", i,
- hw->swf3x[i]);
+ hw->swf3x[i]);
}
for (i = 0; i < 8; i++)
printk(" FENCE%d 0x%08x\n", i,
- hw->fence[i]);
+ hw->fence[i]);
printk(" INSTPM 0x%08x\n", hw->instpm);
printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
#endif
}
+
+
/* Split the M parameter into M1 and M2. */
static int
-splitm(unsigned int m, unsigned int *retm1, unsigned int *retm2)
+splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
{
int m1, m2;
-
- m1 = (m - 2 - (MIN_M2 + MAX_M2) / 2) / 5 - 2;
- if (m1 < MIN_M1)
- m1 = MIN_M1;
- if (m1 > MAX_M1)
- m1 = MAX_M1;
- m2 = m - 5 * (m1 + 2) - 2;
- if (m2 < MIN_M2 || m2 > MAX_M2 || m2 >= m1) {
- return 1;
- } else {
- *retm1 = (unsigned int)m1;
- *retm2 = (unsigned int)m2;
- return 0;
+ int testm;
+ /* no point optimising too much - brute force m */
+ for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
+ for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
+ testm = (5 * (m1 + 2)) + (m2 + 2);
+ if (testm == m) {
+ *retm1 = (unsigned int)m1;
+ *retm2 = (unsigned int)m2;
+ return 0;
+ }
+ }
}
+ return 1;
}
/* Split the P parameter into P1 and P2. */
static int
-splitp(unsigned int p, unsigned int *retp1, unsigned int *retp2)
+splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
{
int p1, p2;
- if (p % 4 == 0)
- p2 = 1;
- else
- p2 = 0;
- p1 = (p / (1 << (p2 + 1))) - 2;
- if (p % 4 == 0 && p1 < MIN_P1) {
- p2 = 0;
- p1 = (p / (1 << (p2 + 1))) - 2;
- }
- if (p1 < MIN_P1 || p1 > MAX_P1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
- return 1;
- } else {
+ if (index == PLLS_I9xx) {
+
+ p2 = 0; // for now
+
+ p1 = p / (p2 ? 5 : 10);
+
*retp1 = (unsigned int)p1;
*retp2 = (unsigned int)p2;
return 0;
}
+
+ if (index == PLLS_I8xx) {
+ if (p % 4 == 0)
+ p2 = 1;
+ else
+ p2 = 0;
+ p1 = (p / (1 << (p2 + 1))) - 2;
+ if (p % 4 == 0 && p1 < plls[index].min_p1) {
+ p2 = 0;
+ p1 = (p / (1 << (p2 + 1))) - 2;
+ }
+ if (p1 < plls[index].min_p1 ||
+ p1 > plls[index].max_p1 ||
+ (p1 + 2) * (1 << (p2 + 1)) != p) {
+ return 1;
+ } else {
+ *retp1 = (unsigned int)p1;
+ *retp2 = (unsigned int)p2;
+ return 0;
+ }
+ }
+ return 1;
}
static int
-calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
+calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
u32 *retp2, u32 *retclock)
{
- u32 m1, m2, n, p1, p2, n1;
- u32 f_vco, p, p_best = 0, m, f_out;
+ u32 m1, m2, n, p1, p2, n1, testm;
+ u32 f_vco, p, p_best = 0, m, f_out = 0;
u32 err_max, err_target, err_best = 10000000;
u32 n_best = 0, m_best = 0, f_best, f_err;
u32 p_min, p_max, p_inc, div_min, div_max;
DBG_MSG("Clock is %d\n", clock);
- div_max = MAX_VCO_FREQ / clock;
- div_min = ROUND_UP_TO(MIN_VCO_FREQ, clock) / clock;
+ div_max = plls[index].max_vco / clock;
+ if (index == PLLS_I9xx)
+ div_min = 5;
+ else
+ div_min = ROUND_UP_TO(plls[index].min_vco, clock) / clock;
- if (clock <= P_TRANSITION_CLOCK)
- p_inc = 4;
+ if (clock <= plls[index].p_transition_clk)
+ p_inc = plls[index].p_inc_lo;
else
- p_inc = 2;
+ p_inc = plls[index].p_inc_hi;
p_min = ROUND_UP_TO(div_min, p_inc);
p_max = ROUND_DOWN_TO(div_max, p_inc);
- if (p_min < MIN_P)
- p_min = 4;
- if (p_max > MAX_P)
- p_max = 128;
+ if (p_min < plls[index].min_p)
+ p_min = plls[index].min_p;
+ if (p_max > plls[index].max_p)
+ p_max = plls[index].max_p;
DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
p = p_min;
do {
- if (splitp(p, &p1, &p2)) {
+ if (splitp(index, p, &p1, &p2)) {
WRN_MSG("cannot split p = %d\n", p);
p += p_inc;
continue;
}
- n = MIN_N;
+ n = plls[index].min_n;
f_vco = clock * p;
do {
- m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
- if (m < MIN_M)
- m = MIN_M;
- if (m > MAX_M)
- m = MAX_M;
- f_out = CALC_VCLOCK3(m, n, p);
- if (splitm(m, &m1, &m2)) {
- WRN_MSG("cannot split m = %d\n", m);
- n++;
- continue;
- }
- if (clock > f_out)
- f_err = clock - f_out;
- else
- f_err = f_out - clock;
-
- if (f_err < err_best) {
- m_best = m;
- n_best = n;
- p_best = p;
- f_best = f_out;
- err_best = f_err;
+ m = ROUND_UP_TO(f_vco * n, plls[index].ref_clk) / plls[index].ref_clk;
+ if (m < plls[index].min_m)
+ m = plls[index].min_m + 1;
+ if (m > plls[index].max_m)
+ m = plls[index].max_m - 1;
+ for (testm = m - 1; testm <= m; testm++) {
+ f_out = calc_vclock3(index, m, n, p);
+ if (splitm(index, m, &m1, &m2)) {
+ WRN_MSG("cannot split m = %d\n", m);
+ n++;
+ continue;
+ }
+ if (clock > f_out)
+ f_err = clock - f_out;
+ else/* slightly bias the error for bigger clocks */
+ f_err = f_out - clock + 1;
+
+ if (f_err < err_best) {
+ m_best = m;
+ n_best = n;
+ p_best = p;
+ f_best = f_out;
+ err_best = f_err;
+ }
}
n++;
- } while ((n <= MAX_N) && (f_out >= clock));
+ } while ((n <= plls[index].max_n) && (f_out >= clock));
p += p_inc;
} while ((p <= p_max));
m = m_best;
n = n_best;
p = p_best;
- splitm(m, &m1, &m2);
- splitp(p, &p1, &p2);
+ splitm(index, m, &m1, &m2);
+ splitp(index, p, &p1, &p2);
n1 = n - 2;
DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
"f: %d (%d), VCO: %d\n",
m, m1, m2, n, n1, p, p1, p2,
- CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2),
- CALC_VCLOCK3(m, n, p) * p);
+ calc_vclock3(index, m, n, p),
+ calc_vclock(index, m1, m2, n1, p1, p2, 0),
+ calc_vclock3(index, m, n, p) * p);
*retm1 = m1;
*retm2 = m2;
*retn = n1;
*retp1 = p1;
*retp2 = p2;
- *retclock = CALC_VCLOCK(m1, m2, n1, p1, p2);
+ *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
return 0;
}
/* Desired clock in kHz */
clock_target = 1000000000 / var->pixclock;
- if (calc_pll_params(clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
+ if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
+ &n, &p1, &p2, &clock)) {
WRN_MSG("calc_pll_params failed\n");
return 1;
}
*dpll &= ~DPLL_P1_FORCE_DIV2;
*dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
(DPLL_P1_MASK << DPLL_P1_SHIFT));
- *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
+
+ if (IS_I9XX(dinfo)) {
+ *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
+ *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
+ } else {
+ *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
+ }
+
*fp0 = (n << FP_N_DIVISOR_SHIFT) |
(m1 << FP_M1_DIVISOR_SHIFT) |
(m2 << FP_M2_DIVISOR_SHIFT);
u32 hsync_reg, htotal_reg, hblank_reg;
u32 vsync_reg, vtotal_reg, vblank_reg;
u32 src_size_reg;
+ u32 count, tmp_val[3];
/* Assume single pipe, display plane A, analog CRT. */
src_size_reg = SRC_SIZE_A;
}
+ /* turn off pipe */
+ tmp = INREG(pipe_conf_reg);
+ tmp &= ~PIPECONF_ENABLE;
+ OUTREG(pipe_conf_reg, tmp);
+
+ count = 0;
+ do {
+ tmp_val[count%3] = INREG(0x70000);
+ if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
+ break;
+ count++;
+ udelay(1);
+ if (count % 200 == 0) {
+ tmp = INREG(pipe_conf_reg);
+ tmp &= ~PIPECONF_ENABLE;
+ OUTREG(pipe_conf_reg, tmp);
+ }
+ } while(count < 2000);
+
+ OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
+
/* Disable planes A and B. */
tmp = INREG(DSPACNTR);
tmp &= ~DISPPLANE_PLANE_ENABLE;
tmp &= ~DISPPLANE_PLANE_ENABLE;
OUTREG(DSPBCNTR, tmp);
- /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
+ /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
mdelay(20);
/* Disable Sync */
tmp |= ADPA_DPMS_D3;
OUTREG(ADPA, tmp);
- /* turn off pipe */
- tmp = INREG(pipe_conf_reg);
- tmp &= ~PIPECONF_ENABLE;
- OUTREG(pipe_conf_reg, tmp);
+ /* do some funky magic - xyzzy */
+ OUTREG(0x61204, 0xabcd0000);
/* turn off PLL */
tmp = INREG(dpll_reg);
OUTREG(fp0_reg, *fp0);
OUTREG(fp1_reg, *fp1);
- /* Set pipe parameters */
- OUTREG(hsync_reg, *hs);
- OUTREG(hblank_reg, *hb);
- OUTREG(htotal_reg, *ht);
- OUTREG(vsync_reg, *vs);
- OUTREG(vblank_reg, *vb);
- OUTREG(vtotal_reg, *vt);
- OUTREG(src_size_reg, *ss);
+ /* Enable PLL */
+ tmp = INREG(dpll_reg);
+ tmp |= DPLL_VCO_ENABLE;
+ OUTREG(dpll_reg, tmp);
/* Set DVOs B/C */
OUTREG(DVOB, hw->dvob);
OUTREG(DVOC, hw->dvoc);
+ /* undo funky magic */
+ OUTREG(0x61204, 0x00000000);
+
/* Set ADPA */
+ OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
- /* Enable PLL */
- tmp = INREG(dpll_reg);
- tmp |= DPLL_VCO_ENABLE;
- OUTREG(dpll_reg, tmp);
+ /* Set pipe parameters */
+ OUTREG(hsync_reg, *hs);
+ OUTREG(hblank_reg, *hb);
+ OUTREG(htotal_reg, *ht);
+ OUTREG(vsync_reg, *vs);
+ OUTREG(vblank_reg, *vb);
+ OUTREG(vtotal_reg, *vt);
+ OUTREG(src_size_reg, *ss);
/* Enable pipe */
OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
OUTREG(DSPACNTR,
hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
mdelay(1);
- }
+ }
}
OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
DBG_MSG("intelfbhw_cursor_init\n");
#endif
- if (dinfo->mobile) {
+ if (dinfo->mobile || IS_I9XX(dinfo)) {
if (!dinfo->cursor.physical)
return;
tmp = INREG(CURSOR_A_CONTROL);
#endif
dinfo->cursor_on = 0;
- if (dinfo->mobile) {
+ if (dinfo->mobile || IS_I9XX(dinfo)) {
if (!dinfo->cursor.physical)
return;
tmp = INREG(CURSOR_A_CONTROL);
if (dinfo->cursor_blanked)
return;
- if (dinfo->mobile) {
+ if (dinfo->mobile || IS_I9XX(dinfo)) {
if (!dinfo->cursor.physical)
return;
tmp = INREG(CURSOR_A_CONTROL);
#endif
/*
- * Sets the position. The coordinates are assumed to already
- * have any offset adjusted. Assume that the cursor is never
+ * Sets the position. The coordinates are assumed to already
+ * have any offset adjusted. Assume that the cursor is never
* completely off-screen, and that x, y are always >= 0.
*/
tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
OUTREG(CURSOR_A_POSITION, tmp);
+
+ if (IS_I9XX(dinfo)) {
+ OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
+ }
}
void
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff