int min_n, max_n;
int min_p, max_p;
int min_p1, max_p1;
- int min_vco_freq, max_vco_freq;
- int p_transition_clock;
+ int min_vco, max_vco;
+ int p_transition_clk, ref_clk;
int p_inc_lo, p_inc_hi;
};
#define PLLS_I9xx 1
#define PLLS_MAX 2
-struct pll_min_max plls[PLLS_MAX] = {
- { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
- { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 } //I9xx
+static struct pll_min_max plls[PLLS_MAX] = {
+ { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 48000, 4, 22 }, //I8xx
+ { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 96000, 10, 5 } //I9xx
};
int
dinfo->mobile = 0;
dinfo->pll_index = PLLS_I9xx;
return 0;
+ case PCI_DEVICE_ID_INTEL_945GM:
+ dinfo->name = "Intel(R) 945GM";
+ dinfo->chipset = INTEL_945GM;
+ dinfo->mobile = 1;
+ dinfo->pll_index = PLLS_I9xx;
+ return 0;
default:
return 1;
}
{
if (p == 0 || n == 0)
return 0;
- return PLL_REFCLK * m / n / p;
+ return plls[index].ref_clk * m / n / p;
}
-
-static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
+
+static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
{
+ int p2_val;
switch(index)
{
case PLLS_I9xx:
if (p1 == 0)
return 0;
- return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
- ((p1)) * (p2 ? 10 : 5)));
+ if (lvds)
+ p2_val = p2 ? 7 : 14;
+ else
+ p2_val = p2 ? 5 : 10;
+ return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
+ ((p1)) * (p2_val)));
case PLLS_I8xx:
default:
- return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
+ return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
((p1+2) * (1 << (p2 + 1)))));
}
}
int i, m1, m2, n, p1, p2;
int index = dinfo->pll_index;
DBG_MSG("intelfbhw_print_hw_state\n");
-
+
if (!hw || !dinfo)
return;
/* Read in as much of the HW state as possible. */
p1 = 0;
else
p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
+
p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
+
printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
- printk(" VGA0: clock is %d\n",
- calc_vclock(index, m1, m2, n, p1, p2));
-
+ printk(" VGA0: clock is %d\n",
+ calc_vclock(index, m1, m2, n, p1, p2, 0));
+
n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
- printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
-
+ printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
+
printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
printk(" FPA0: 0x%08x\n", hw->fpa0);
printk(" FPA1: 0x%08x\n", hw->fpa1);
printk(" FPB0: 0x%08x\n", hw->fpb0);
printk(" FPB1: 0x%08x\n", hw->fpb1);
-
+
n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+
+ if (IS_I9XX(dinfo)) {
+ int tmpp1;
+
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
+
+ tmpp1 = p1;
+
+ switch (tmpp1)
+ {
+ case 0x1: p1 = 1; break;
+ case 0x2: p1 = 2; break;
+ case 0x4: p1 = 3; break;
+ case 0x8: p1 = 4; break;
+ case 0x10: p1 = 5; break;
+ case 0x20: p1 = 6; break;
+ case 0x40: p1 = 7; break;
+ case 0x80: p1 = 8; break;
+ default: break;
+ }
+
+ p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+
+ } else {
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
+ p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+ }
+
printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
- printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
-
+ printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
+
n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+
+ if (IS_I9XX(dinfo)) {
+ int tmpp1;
+
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
+
+ tmpp1 = p1;
+
+ switch (tmpp1)
+ {
+ case 0x1: p1 = 1; break;
+ case 0x2: p1 = 2; break;
+ case 0x4: p1 = 3; break;
+ case 0x8: p1 = 4; break;
+ case 0x10: p1 = 5; break;
+ case 0x20: p1 = 6; break;
+ case 0x40: p1 = 7; break;
+ case 0x80: p1 = 8; break;
+ default: break;
+ }
+
+ p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+
+ } else {
+ if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
+ p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
+ }
printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
- printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
-
+ printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
+
#if 0
printk(" PALETTE_A:\n");
for (i = 0; i < PALETTE_8_ENTRIES)
for (i = 0; i < 8; i++)
printk(" FENCE%d 0x%08x\n", i,
hw->fence[i]);
-
+
printk(" INSTPM 0x%08x\n", hw->instpm);
printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
#endif
}
-
+
/* Split the M parameter into M1 and M2. */
static int
int m1, m2;
int testm;
/* no point optimising too much - brute force m */
- for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++)
- {
- for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++)
- {
- testm = ( 5 * ( m1 + 2 )) + (m2 + 2);
- if (testm == m)
- {
- *retm1 = (unsigned int)m1;
- *retm2 = (unsigned int)m2;
- return 0;
- }
- }
+ for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
+ for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
+ testm = (5 * (m1 + 2)) + (m2 + 2);
+ if (testm == m) {
+ *retm1 = (unsigned int)m1;
+ *retm2 = (unsigned int)m2;
+ return 0;
+ }
+ }
}
return 1;
}
{
int p1, p2;
- if (index == PLLS_I9xx)
- {
- switch (p) {
- case 10:
- p1 = 2;
- p2 = 0;
- break;
- case 20:
- p1 = 1;
- p2 = 0;
- break;
- default:
- p1 = (p / 10) + 1;
- p2 = 0;
- break;
- }
-
+ if (index == PLLS_I9xx) {
+
+ p2 = 0; // for now
+
+ p1 = p / (p2 ? 5 : 10);
+
*retp1 = (unsigned int)p1;
*retp2 = (unsigned int)p2;
return 0;
}
- if (index == PLLS_I8xx)
- {
+ if (index == PLLS_I8xx) {
if (p % 4 == 0)
p2 = 1;
else
p2 = 0;
p1 = (p / (1 << (p2 + 1))) - 2;
}
- if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
+ if (p1 < plls[index].min_p1 ||
+ p1 > plls[index].max_p1 ||
+ (p1 + 2) * (1 << (p2 + 1)) != p) {
return 1;
} else {
*retp1 = (unsigned int)p1;
DBG_MSG("Clock is %d\n", clock);
- div_max = plls[index].max_vco_freq / clock;
+ div_max = plls[index].max_vco / clock;
if (index == PLLS_I9xx)
div_min = 5;
else
- div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
+ div_min = ROUND_UP_TO(plls[index].min_vco, clock) / clock;
- if (clock <= plls[index].p_transition_clock)
+ if (clock <= plls[index].p_transition_clk)
p_inc = plls[index].p_inc_lo;
else
p_inc = plls[index].p_inc_hi;
if (p_max > plls[index].max_p)
p_max = plls[index].max_p;
- if (clock < PLL_REFCLK && index==PLLS_I9xx)
- {
- p_min = 10;
- p_max = 20;
- /* this makes 640x480 work it really shouldn't
- - SOMEONE WITHOUT DOCS WOZ HERE */
- if (clock < 30000)
- clock *= 4;
- }
-
DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
p = p_min;
f_vco = clock * p;
do {
- m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
+ m = ROUND_UP_TO(f_vco * n, plls[index].ref_clk) / plls[index].ref_clk;
if (m < plls[index].min_m)
m = plls[index].min_m + 1;
if (m > plls[index].max_m)
f_err = clock - f_out;
else/* slightly bias the error for bigger clocks */
f_err = f_out - clock + 1;
-
+
if (f_err < err_best) {
m_best = m;
n_best = n;
DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
"f: %d (%d), VCO: %d\n",
m, m1, m2, n, n1, p, p1, p2,
- calc_vclock3(index, m, n, p),
- calc_vclock(index, m1, m2, n1, p1, p2),
+ calc_vclock3(index, m, n, p),
+ calc_vclock(index, m1, m2, n1, p1, p2, 0),
calc_vclock3(index, m, n, p) * p);
*retm1 = m1;
*retm2 = m2;
*retn = n1;
*retp1 = p1;
*retp2 = p2;
- *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
+ *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
return 0;
}
/* Desired clock in kHz */
clock_target = 1000000000 / var->pixclock;
- if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
+ if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
+ &n, &p1, &p2, &clock)) {
WRN_MSG("calc_pll_params failed\n");
return 1;
}
*dpll &= ~DPLL_P1_FORCE_DIV2;
*dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
(DPLL_P1_MASK << DPLL_P1_SHIFT));
- *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
+
+ if (IS_I9XX(dinfo)) {
+ *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
+ *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
+ } else {
+ *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
+ }
+
*fp0 = (n << FP_N_DIVISOR_SHIFT) |
(m1 << FP_M1_DIVISOR_SHIFT) |
(m2 << FP_M2_DIVISOR_SHIFT);
tmp = INREG(pipe_conf_reg);
tmp &= ~PIPECONF_ENABLE;
OUTREG(pipe_conf_reg, tmp);
-
+
count = 0;
- do{
- tmp_val[count%3] = INREG(0x70000);
- if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
- break;
- count++;
- udelay(1);
- if (count % 200 == 0)
- {
- tmp = INREG(pipe_conf_reg);
- tmp &= ~PIPECONF_ENABLE;
- OUTREG(pipe_conf_reg, tmp);
- }
+ do {
+ tmp_val[count%3] = INREG(0x70000);
+ if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
+ break;
+ count++;
+ udelay(1);
+ if (count % 200 == 0) {
+ tmp = INREG(pipe_conf_reg);
+ tmp &= ~PIPECONF_ENABLE;
+ OUTREG(pipe_conf_reg, tmp);
+ }
} while(count < 2000);
OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
tmp &= ~DISPPLANE_PLANE_ENABLE;
OUTREG(DSPBCNTR, tmp);
- /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
+ /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
mdelay(20);
/* Disable Sync */
OUTREG(DSPACNTR,
hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
mdelay(1);
- }
+ }
}
OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
DBG_MSG("intelfbhw_cursor_init\n");
#endif
- if (dinfo->mobile || IS_I9xx(dinfo)) {
+ if (dinfo->mobile || IS_I9XX(dinfo)) {
if (!dinfo->cursor.physical)
return;
tmp = INREG(CURSOR_A_CONTROL);
#endif
dinfo->cursor_on = 0;
- if (dinfo->mobile || IS_I9xx(dinfo)) {
+ if (dinfo->mobile || IS_I9XX(dinfo)) {
if (!dinfo->cursor.physical)
return;
tmp = INREG(CURSOR_A_CONTROL);
if (dinfo->cursor_blanked)
return;
- if (dinfo->mobile || IS_I9xx(dinfo)) {
+ if (dinfo->mobile || IS_I9XX(dinfo)) {
if (!dinfo->cursor.physical)
return;
tmp = INREG(CURSOR_A_CONTROL);
#endif
/*
- * Sets the position. The coordinates are assumed to already
- * have any offset adjusted. Assume that the cursor is never
+ * Sets the position. The coordinates are assumed to already
+ * have any offset adjusted. Assume that the cursor is never
* completely off-screen, and that x, y are always >= 0.
*/
((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
OUTREG(CURSOR_A_POSITION, tmp);
- if (IS_I9xx(dinfo)) {
+ if (IS_I9XX(dinfo)) {
OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
}
}
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff