hw->fw_blc_0 = INREG(FW_BLC_0);
hw->fw_blc_1 = INREG(FW_BLC_1);
+ hw->hwstam = INREG16(HWSTAM);
+ hw->ier = INREG16(IER);
+ hw->iir = INREG16(IIR);
+ hw->imr = INREG16(IMR);
+
return 0;
}
static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
{
- int p2_val;
- switch(index)
- {
- case PLLS_I9xx:
- if (p1 == 0)
- return 0;
- if (lvds)
- p2_val = p2 ? 7 : 14;
+ struct pll_min_max *pll = &plls[index];
+ u32 m, vco, p;
+
+ m = (5 * (m1 + 2)) + (m2 + 2);
+ n += 2;
+ vco = pll->ref_clk * m / n;
+
+ if (index == PLLS_I8xx) {
+ p = ((p1 + 2) * (1 << (p2 + 1)));
+ } else {
+ p = ((p1) * (p2 ? 5 : 10));
+ }
+ return vco / p;
+}
+
+static void
+intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
+{
+ int p1, p2;
+
+ if (IS_I9XX(dinfo)) {
+ if (dpll & DPLL_P1_FORCE_DIV2)
+ p1 = 1;
else
- p2_val = p2 ? 5 : 10;
- return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
- ((p1)) * (p2_val)));
- case PLLS_I8xx:
- default:
- return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
- ((p1+2) * (1 << (p2 + 1)))));
+ p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
+
+ p1 = ffs(p1);
+
+ p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
+ } else {
+ if (dpll & DPLL_P1_FORCE_DIV2)
+ p1 = 0;
+ else
+ p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
+ p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
}
+
+ *o_p1 = p1;
+ *o_p2 = p2;
}
+
void
intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
{
n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
+ intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
+
+ intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (IS_I9XX(dinfo)) {
- int tmpp1;
-
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
-
- tmpp1 = p1;
-
- switch (tmpp1)
- {
- case 0x1: p1 = 1; break;
- case 0x2: p1 = 2; break;
- case 0x4: p1 = 3; break;
- case 0x8: p1 = 4; break;
- case 0x10: p1 = 5; break;
- case 0x20: p1 = 6; break;
- case 0x40: p1 = 7; break;
- case 0x80: p1 = 8; break;
- default: break;
- }
-
- p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
-
- } else {
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
- }
+ intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
- if (IS_I9XX(dinfo)) {
- int tmpp1;
+ intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
-
- tmpp1 = p1;
-
- switch (tmpp1) {
- case 0x1: p1 = 1; break;
- case 0x2: p1 = 2; break;
- case 0x4: p1 = 3; break;
- case 0x8: p1 = 4; break;
- case 0x10: p1 = 5; break;
- case 0x20: p1 = 6; break;
- case 0x40: p1 = 7; break;
- case 0x80: p1 = 8; break;
- default: break;
- }
-
- p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
-
- } else {
- if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
- p1 = 0;
- else
- p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
- p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
- }
printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
m1, m2, n, p1, p2);
printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
+ printk(" HWSTAM 0x%04x\n", hw->hwstam);
+ printk(" IER 0x%04x\n", hw->ier);
+ printk(" IIR 0x%04x\n", hw->iir);
+ printk(" IMR 0x%04x\n", hw->imr);
printk("hw state dump end\n");
#endif
}
{
int m1, m2;
int testm;
+ struct pll_min_max *pll = &plls[index];
+
/* no point optimising too much - brute force m */
- for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
- for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
+ for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
+ for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
testm = (5 * (m1 + 2)) + (m2 + 2);
if (testm == m) {
*retm1 = (unsigned int)m1;
splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
{
int p1, p2;
+ struct pll_min_max *pll = &plls[index];
if (index == PLLS_I9xx) {
p2 = (p % 10) ? 1 : 0;
return 0;
}
- if (index == PLLS_I8xx) {
- if (p % 4 == 0)
- p2 = 1;
- else
- p2 = 0;
+ if (p % 4 == 0)
+ p2 = 1;
+ else
+ p2 = 0;
+ p1 = (p / (1 << (p2 + 1))) - 2;
+ if (p % 4 == 0 && p1 < pll->min_p1) {
+ p2 = 0;
p1 = (p / (1 << (p2 + 1))) - 2;
- if (p % 4 == 0 && p1 < plls[index].min_p1) {
- p2 = 0;
- p1 = (p / (1 << (p2 + 1))) - 2;
- }
- if (p1 < plls[index].min_p1 ||
- p1 > plls[index].max_p1 ||
- (p1 + 2) * (1 << (p2 + 1)) != p) {
- return 1;
- } else {
- *retp1 = (unsigned int)p1;
- *retp2 = (unsigned int)p2;
- return 0;
- }
}
- return 1;
+ if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
+ (p1 + 2) * (1 << (p2 + 1)) != p) {
+ return 1;
+ } else {
+ *retp1 = (unsigned int)p1;
+ *retp2 = (unsigned int)p2;
+ return 0;
+ }
}
static int
m = pll->max_m - 1;
for (testm = m - 1; testm <= m; testm++) {
f_out = calc_vclock3(index, m, n, p);
- if (splitm(index, m, &m1, &m2)) {
+ if (splitm(index, testm, &m1, &m2)) {
WRN_MSG("cannot split m = %d\n", m);
n++;
continue;
f_err = f_out - clock + 1;
if (f_err < err_best) {
- m_best = m;
+ m_best = testm;
n_best = n;
p_best = p;
f_best = f_out;
/* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
mdelay(20);
+ OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
+ OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
+ OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
+
/* Disable Sync */
tmp = INREG(ADPA);
tmp &= ~ADPA_DPMS_CONTROL_MASK;
OUTREG(dpll_reg, tmp);
/* Set PLL parameters */
- OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
OUTREG(fp0_reg, *fp0);
OUTREG(fp1_reg, *fp1);
/* Enable PLL */
- tmp = INREG(dpll_reg);
- tmp |= DPLL_VCO_ENABLE;
- OUTREG(dpll_reg, tmp);
+ OUTREG(dpll_reg, *dpll);
/* Set DVOs B/C */
OUTREG(DVOB, hw->dvob);
end = jiffies + (HZ * 3);
while (dinfo->ring_space < n) {
- dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
- RING_HEAD_MASK);
- if (dinfo->ring_tail + RING_MIN_FREE <
- (u32 __iomem) dinfo->ring_head)
- dinfo->ring_space = (u32 __iomem) dinfo->ring_head
+ dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
+ if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
+ dinfo->ring_space = dinfo->ring_head
- (dinfo->ring_tail + RING_MIN_FREE);
else
dinfo->ring_space = (dinfo->ring.size +
- (u32 __iomem) dinfo->ring_head)
+ dinfo->ring_head)
- (dinfo->ring_tail + RING_MIN_FREE);
- if ((u32 __iomem) dinfo->ring_head != last_head) {
+ if (dinfo->ring_head != last_head) {
end = jiffies + (HZ * 3);
- last_head = (u32 __iomem) dinfo->ring_head;
+ last_head = dinfo->ring_head;
}
i++;
if (time_before(end, jiffies)) {
DBG_MSG("refresh_ring\n");
#endif
- dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
- RING_HEAD_MASK);
+ dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
- if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
- dinfo->ring_space = (u32 __iomem) dinfo->ring_head
+ if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
+ dinfo->ring_space = dinfo->ring_head
- (dinfo->ring_tail + RING_MIN_FREE);
else
- dinfo->ring_space = (dinfo->ring.size +
- (u32 __iomem) dinfo->ring_head)
+ dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
- (dinfo->ring_tail + RING_MIN_FREE);
}
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff