#include <linux/ioport.h>
#include "et1310_phy.h"
-#include "et1310_pm.h"
-#include "et1310_jagcore.h"
-#include "et1310_mac.h"
-
#include "et131x_adapter.h"
+#include "et131x.h"
+
+/*
+ * For interrupts, normal running is:
+ * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
+ * watchdog_interrupt & txdma_xfer_done
+ *
+ * In both cases, when flow control is enabled for either Tx or bi-direction,
+ * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
+ * buffer rings are running low.
+ */
+#define INT_MASK_DISABLE 0xffffffff
+
+/* NOTE: Masking out MAC_STAT Interrupt for now...
+ * #define INT_MASK_ENABLE 0xfff6bf17
+ * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
+ */
+#define INT_MASK_ENABLE 0xfffebf17
+#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
+
/**
* et131x_enable_interrupts - enable interrupt
else
mask = INT_MASK_ENABLE_NO_FLOW;
- if (adapter->DriverNoPhyAccess)
- mask |= ET_INTR_PHY;
-
adapter->CachedMaskValue = mask;
writel(mask, &adapter->regs->global.int_mask);
}
/* This is our interrupt, so process accordingly */
if (status & ET_INTR_WATCHDOG) {
- PMP_TCB pMpTcb = adapter->TxRing.CurrSendHead;
+ struct tcb *tcb = adapter->tx_ring.send_head;
- if (pMpTcb)
- if (++pMpTcb->PacketStaleCount > 1)
+ if (tcb)
+ if (++tcb->stale > 1)
status |= ET_INTR_TXDMA_ISR;
- if (adapter->RxRing.UnfinishedReceives)
+ if (adapter->rx_ring.UnfinishedReceives)
status |= ET_INTR_RXDMA_XFR_DONE;
- else if (pMpTcb == NULL)
+ else if (tcb == NULL)
writel(0, &adapter->regs->global.watchdog_timer);
status &= ~ET_INTR_WATCHDOG;
if (status) {
/* Handle the TXDMA Error interrupt */
if (status & ET_INTR_TXDMA_ERR) {
- TXDMA_ERROR_t TxDmaErr;
+ u32 txdma_err;
/* Following read also clears the register (COR) */
- TxDmaErr.value = readl(&iomem->txdma.TxDmaError.value);
+ txdma_err = readl(&iomem->txdma.TxDmaError);
dev_warn(&etdev->pdev->dev,
"TXDMA_ERR interrupt, error = %d\n",
- TxDmaErr.value);
+ txdma_err);
}
/* Handle Free Buffer Ring 0 and 1 Low interrupt */
u32 pm_csr;
/* Tell the device to send a pause packet via
- * the back pressure register
+ * the back pressure register (bp req and
+ * bp xon/xoff)
*/
pm_csr = readl(&iomem->global.pm_csr);
- if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
- TXMAC_BP_CTRL_t bp_ctrl = { 0 };
-
- bp_ctrl.bits.bp_req = 1;
- bp_ctrl.bits.bp_xonxoff = 1;
- writel(bp_ctrl.value,
- &iomem->txmac.bp_ctrl.value);
- }
+ if ((pm_csr & ET_PM_PHY_SW_COMA) == 0)
+ writel(3, &iomem->txmac.bp_ctrl);
}
}
*/
/* TRAP();*/
- etdev->TxMacTest.value =
- readl(&iomem->txmac.tx_test.value);
dev_warn(&etdev->pdev->dev,
"RxDMA_ERR interrupt, error %x\n",
- etdev->TxMacTest.value);
+ readl(&iomem->txmac.tx_test));
}
/* Handle the Wake on LAN Event */
/* Let's move on to the TxMac */
if (status & ET_INTR_TXMAC) {
- etdev->TxRing.TxMacErr.value =
- readl(&iomem->txmac.err.value);
+ u32 err = readl(&iomem->txmac.err);
/*
* When any of the errors occur and TXMAC generates
*/
dev_warn(&etdev->pdev->dev,
"TXMAC interrupt, error 0x%08x\n",
- etdev->TxRing.TxMacErr.value);
+ err);
/* If we are debugging, we want to see this error,
* otherwise we just want the device to be reset and
dev_warn(&etdev->pdev->dev,
"RXMAC interrupt, error 0x%08x. Requesting reset\n",
- readl(&iomem->rxmac.err_reg.value));
+ readl(&iomem->rxmac.err_reg));
dev_warn(&etdev->pdev->dev,
"Enable 0x%08x, Diag 0x%08x\n",
- readl(&iomem->rxmac.ctrl.value),
- readl(&iomem->rxmac.rxq_diag.value));
+ readl(&iomem->rxmac.ctrl),
+ readl(&iomem->rxmac.rxq_diag));
/*
* If we are debugging, we want to see this error,