* 9-0: pr ndes
*/
-#define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
-#define ET_DMA10_WRAP 0x400
-#define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
-#define ET_DMA4_WRAP 0x010
-
+#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
+#define ET_DMA12_WRAP 0x1000
+#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
+#define ET_DMA10_WRAP 0x0400
+#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
+#define ET_DMA4_WRAP 0x0010
+
+#define INDEX12(x) ((x) & ET_DMA12_MASK)
#define INDEX10(x) ((x) & ET_DMA10_MASK)
#define INDEX4(x) ((x) & ET_DMA4_MASK)
*v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
}
+extern inline void add_12bit(u32 *v, int n)
+{
+ *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
+}
+
/*
* 10bit DMA with wrap
* txdma tx queue write address reg in txdma address map at 0x1010
/*
* structure for control status reg in rxdma address map
* Located at address 0x2000
+ *
+ * CSR
+ * 0: halt
+ * 1-3: tc
+ * 4: fbr_big_endian
+ * 5: psr_big_endian
+ * 6: pkt_big_endian
+ * 7: dma_big_endian
+ * 8-9: fbr0_size
+ * 10: fbr0_enable
+ * 11-12: fbr1_size
+ * 13: fbr1_enable
+ * 14: unused
+ * 15: pkt_drop_disable
+ * 16: pkt_done_flush
+ * 17: halt_status
+ * 18-31: unused
*/
-typedef union _RXDMA_CSR_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused2:14; /* bits 18-31 */
- u32 halt_status:1; /* bit 17 */
- u32 pkt_done_flush:1; /* bit 16 */
- u32 pkt_drop_disable:1; /* bit 15 */
- u32 unused1:1; /* bit 14 */
- u32 fbr1_enable:1; /* bit 13 */
- u32 fbr1_size:2; /* bits 11-12 */
- u32 fbr0_enable:1; /* bit 10 */
- u32 fbr0_size:2; /* bits 8-9 */
- u32 dma_big_endian:1; /* bit 7 */
- u32 pkt_big_endian:1; /* bit 6 */
- u32 psr_big_endian:1; /* bit 5 */
- u32 fbr_big_endian:1; /* bit 4 */
- u32 tc:3; /* bits 1-3 */
- u32 halt:1; /* bit 0 */
-#else
- u32 halt:1; /* bit 0 */
- u32 tc:3; /* bits 1-3 */
- u32 fbr_big_endian:1; /* bit 4 */
- u32 psr_big_endian:1; /* bit 5 */
- u32 pkt_big_endian:1; /* bit 6 */
- u32 dma_big_endian:1; /* bit 7 */
- u32 fbr0_size:2; /* bits 8-9 */
- u32 fbr0_enable:1; /* bit 10 */
- u32 fbr1_size:2; /* bits 11-12 */
- u32 fbr1_enable:1; /* bit 13 */
- u32 unused1:1; /* bit 14 */
- u32 pkt_drop_disable:1; /* bit 15 */
- u32 pkt_done_flush:1; /* bit 16 */
- u32 halt_status:1; /* bit 17 */
- u32 unused2:14; /* bits 18-31 */
-#endif
- } bits;
-} RXDMA_CSR_t, *PRXDMA_CSR_t;
+
/*
* structure for dma writeback lo reg in rxdma address map
/*
* structure for number of packets done reg in rxdma address map
* located at address 0x200C
+ *
+ * 31-8: unused
+ * 7-0: num done
*/
-typedef union _RXDMA_NUM_PKT_DONE_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:24; /* bits 8-31 */
- u32 num_done:8; /* bits 0-7 */
-#else
- u32 num_done:8; /* bits 0-7 */
- u32 unused:24; /* bits 8-31 */
-#endif
- } bits;
-} RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
/*
* structure for max packet time reg in rxdma address map
/*
* structure for packet status ring number of descriptors reg in rxdma address
* map. Located at address 0x2028
+ *
+ * 31-12: unused
+ * 11-0: psr ndes
*/
-typedef union _RXDMA_PSR_NUM_DES_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:20; /* bits 12-31 */
- u32 psr_ndes:12; /* bit 0-11 */
-#else
- u32 psr_ndes:12; /* bit 0-11 */
- u32 unused:20; /* bits 12-31 */
-#endif
- } bits;
-} RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
/*
* structure for packet status ring available offset reg in rxdma address map
* located at address 0x202C
+ *
+ * 31-13: unused
+ * 12: psr avail wrap
+ * 11-0: psr avail
*/
-typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:19; /* bits 13-31 */
- u32 psr_avail_wrap:1; /* bit 12 */
- u32 psr_avail:12; /* bit 0-11 */
-#else
- u32 psr_avail:12; /* bit 0-11 */
- u32 psr_avail_wrap:1; /* bit 12 */
- u32 unused:19; /* bits 13-31 */
-#endif
- } bits;
-} RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
/*
* structure for packet status ring full offset reg in rxdma address map
* located at address 0x2030
+ *
+ * 31-13: unused
+ * 12: psr full wrap
+ * 11-0: psr full
*/
-typedef union _RXDMA_PSR_FULL_OFFSET_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:19; /* bits 13-31 */
- u32 psr_full_wrap:1; /* bit 12 */
- u32 psr_full:12; /* bit 0-11 */
-#else
- u32 psr_full:12; /* bit 0-11 */
- u32 psr_full_wrap:1; /* bit 12 */
- u32 unused:19; /* bits 13-31 */
-#endif
- } bits;
-} RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
/*
* structure for packet status ring access index reg in rxdma address map
* located at address 0x2034
+ *
+ * 31-5: unused
+ * 4-0: psr_ai
*/
-typedef union _RXDMA_PSR_ACCESS_INDEX_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:27; /* bits 5-31 */
- u32 psr_ai:5; /* bits 0-4 */
-#else
- u32 psr_ai:5; /* bits 0-4 */
- u32 unused:27; /* bits 5-31 */
-#endif
- } bits;
-} RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
/*
* structure for packet status ring minimum descriptors reg in rxdma address
* map. Located at address 0x2038
+ *
+ * 31-12: unused
+ * 11-0: psr_min
*/
-typedef union _RXDMA_PSR_MIN_DES_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:20; /* bits 12-31 */
- u32 psr_min:12; /* bits 0-11 */
-#else
- u32 psr_min:12; /* bits 0-11 */
- u32 unused:20; /* bits 12-31 */
-#endif
- } bits;
-} RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
/*
* structure for free buffer ring base lo address reg in rxdma address map
/*
* structure for free buffer ring number of descriptors reg in rxdma address
* map. Located at address 0x2044
+ *
+ * 31-10: unused
+ * 9-0: fbr ndesc
*/
-typedef union _RXDMA_FBR_NUM_DES_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:22; /* bits 10-31 */
- u32 fbr_ndesc:10; /* bits 0-9 */
-#else
- u32 fbr_ndesc:10; /* bits 0-9 */
- u32 unused:22; /* bits 10-31 */
-#endif
- } bits;
-} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
/*
* structure for free buffer ring 0 available offset reg in rxdma address map
/*
* structure for free buffer cache 0 full offset reg in rxdma address map
* located at address 0x2050
+ *
+ * 31-5: unused
+ * 4-0: fbc rdi
*/
-typedef union _RXDMA_FBC_RD_INDEX_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:27; /* bits 5-31 */
- u32 fbc_rdi:5; /* bit 0-4 */
-#else
- u32 fbc_rdi:5; /* bit 0-4 */
- u32 unused:27; /* bits 5-31 */
-#endif
- } bits;
-} RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
/*
* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
* located at address 0x2054
+ *
+ * 31-10: unused
+ * 9-0: fbr min
*/
-typedef union _RXDMA_FBR_MIN_DES_t {
- u32 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u32 unused:22; /* bits 10-31 */
- u32 fbr_min:10; /* bits 0-9 */
-#else
- u32 fbr_min:10; /* bits 0-9 */
- u32 unused:22; /* bits 10-31 */
-#endif
- } bits;
-} RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
/*
* structure for free buffer ring 1 base address lo reg in rxdma address map
* Rx DMA Module of JAGCore Address Mapping
* Located at address 0x2000
*/
-typedef struct _RXDMA_t { /* Location: */
- RXDMA_CSR_t csr; /* 0x2000 */
+struct rxdma_regs { /* Location: */
+ u32 csr; /* 0x2000 */
u32 dma_wb_base_lo; /* 0x2004 */
u32 dma_wb_base_hi; /* 0x2008 */
- RXDMA_NUM_PKT_DONE_t num_pkt_done; /* 0x200C */
+ u32 num_pkt_done; /* 0x200C */
u32 max_pkt_time; /* 0x2010 */
u32 rxq_rd_addr; /* 0x2014 */
- u32 rxq_rd_addr_ext; /* 0x2018 */
+ u32 rxq_rd_addr_ext; /* 0x2018 */
u32 rxq_wr_addr; /* 0x201C */
u32 psr_base_lo; /* 0x2020 */
u32 psr_base_hi; /* 0x2024 */
- RXDMA_PSR_NUM_DES_t psr_num_des; /* 0x2028 */
- RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; /* 0x202C */
- RXDMA_PSR_FULL_OFFSET_t psr_full_offset; /* 0x2030 */
- RXDMA_PSR_ACCESS_INDEX_t psr_access_index; /* 0x2034 */
- RXDMA_PSR_MIN_DES_t psr_min_des; /* 0x2038 */
+ u32 psr_num_des; /* 0x2028 */
+ u32 psr_avail_offset; /* 0x202C */
+ u32 psr_full_offset; /* 0x2030 */
+ u32 psr_access_index; /* 0x2034 */
+ u32 psr_min_des; /* 0x2038 */
u32 fbr0_base_lo; /* 0x203C */
u32 fbr0_base_hi; /* 0x2040 */
- RXDMA_FBR_NUM_DES_t fbr0_num_des; /* 0x2044 */
- u32 fbr0_avail_offset; /* 0x2048 */
- u32 fbr0_full_offset; /* 0x204C */
- RXDMA_FBC_RD_INDEX_t fbr0_rd_index; /* 0x2050 */
- RXDMA_FBR_MIN_DES_t fbr0_min_des; /* 0x2054 */
+ u32 fbr0_num_des; /* 0x2044 */
+ u32 fbr0_avail_offset; /* 0x2048 */
+ u32 fbr0_full_offset; /* 0x204C */
+ u32 fbr0_rd_index; /* 0x2050 */
+ u32 fbr0_min_des; /* 0x2054 */
u32 fbr1_base_lo; /* 0x2058 */
u32 fbr1_base_hi; /* 0x205C */
- RXDMA_FBR_NUM_DES_t fbr1_num_des; /* 0x2060 */
- u32 fbr1_avail_offset; /* 0x2064 */
- u32 fbr1_full_offset; /* 0x2068 */
- RXDMA_FBC_RD_INDEX_t fbr1_rd_index; /* 0x206C */
- RXDMA_FBR_MIN_DES_t fbr1_min_des; /* 0x2070 */
-} RXDMA_t, *PRXDMA_t;
+ u32 fbr1_num_des; /* 0x2060 */
+ u32 fbr1_avail_offset; /* 0x2064 */
+ u32 fbr1_full_offset; /* 0x2068 */
+ u32 fbr1_rd_index; /* 0x206C */
+ u32 fbr1_min_des; /* 0x2070 */
+};
/* END OF RXDMA REGISTER ADDRESS MAP */
TXDMA_t txdma;
/* unused section of txdma address map */
u8 unused_txdma[4096 - sizeof(TXDMA_t)];
- RXDMA_t rxdma;
+ struct rxdma_regs rxdma;
/* unused section of rxdma address map */
- u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
+ u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
TXMAC_t txmac;
/* unused section of txmac address map */
u8 unused_txmac[4096 - sizeof(TXMAC_t)];
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