#ifndef BCM43xx_H_
#define BCM43xx_H_
+#include <linux/hw_random.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#define PFX KBUILD_MODNAME ": "
-#define BCM43xx_SWITCH_CORE_MAX_RETRIES 10
+#define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
#define BCM43xx_IRQWAIT_MAX_RETRIES 50
#define BCM43xx_IO_SIZE 8192
-#define BCM43xx_REG_ACTIVE_CORE 0x80
-/* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
-#define BCM43xx_PCICFG_ICR 0x94
+/* Active Core PCI Configuration Register. */
+#define BCM43xx_PCICFG_ACTIVE_CORE 0x80
/* SPROM control register. */
#define BCM43xx_PCICFG_SPROMCTL 0x88
+/* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
+#define BCM43xx_PCICFG_ICR 0x94
/* MMIO offsets */
-#define BCM43xx_MMIO_DMA1_REASON 0x20
-#define BCM43xx_MMIO_DMA1_IRQ_MASK 0x24
-#define BCM43xx_MMIO_DMA2_REASON 0x28
-#define BCM43xx_MMIO_DMA2_IRQ_MASK 0x2C
-#define BCM43xx_MMIO_DMA3_REASON 0x30
-#define BCM43xx_MMIO_DMA3_IRQ_MASK 0x34
-#define BCM43xx_MMIO_DMA4_REASON 0x38
-#define BCM43xx_MMIO_DMA4_IRQ_MASK 0x3C
+#define BCM43xx_MMIO_DMA0_REASON 0x20
+#define BCM43xx_MMIO_DMA0_IRQ_MASK 0x24
+#define BCM43xx_MMIO_DMA1_REASON 0x28
+#define BCM43xx_MMIO_DMA1_IRQ_MASK 0x2C
+#define BCM43xx_MMIO_DMA2_REASON 0x30
+#define BCM43xx_MMIO_DMA2_IRQ_MASK 0x34
+#define BCM43xx_MMIO_DMA3_REASON 0x38
+#define BCM43xx_MMIO_DMA3_IRQ_MASK 0x3C
+#define BCM43xx_MMIO_DMA4_REASON 0x40
+#define BCM43xx_MMIO_DMA4_IRQ_MASK 0x44
+#define BCM43xx_MMIO_DMA5_REASON 0x48
+#define BCM43xx_MMIO_DMA5_IRQ_MASK 0x4C
#define BCM43xx_MMIO_STATUS_BITFIELD 0x120
#define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
#define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
#define BCM43xx_MMIO_XMITSTAT_1 0x174
#define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
-#define BCM43xx_MMIO_DMA1_BASE 0x200
-#define BCM43xx_MMIO_DMA2_BASE 0x220
-#define BCM43xx_MMIO_DMA3_BASE 0x240
-#define BCM43xx_MMIO_DMA4_BASE 0x260
+
+/* 32-bit DMA */
+#define BCM43xx_MMIO_DMA32_BASE0 0x200
+#define BCM43xx_MMIO_DMA32_BASE1 0x220
+#define BCM43xx_MMIO_DMA32_BASE2 0x240
+#define BCM43xx_MMIO_DMA32_BASE3 0x260
+#define BCM43xx_MMIO_DMA32_BASE4 0x280
+#define BCM43xx_MMIO_DMA32_BASE5 0x2A0
+/* 64-bit DMA */
+#define BCM43xx_MMIO_DMA64_BASE0 0x200
+#define BCM43xx_MMIO_DMA64_BASE1 0x240
+#define BCM43xx_MMIO_DMA64_BASE2 0x280
+#define BCM43xx_MMIO_DMA64_BASE3 0x2C0
+#define BCM43xx_MMIO_DMA64_BASE4 0x300
+#define BCM43xx_MMIO_DMA64_BASE5 0x340
+/* PIO */
#define BCM43xx_MMIO_PIO1_BASE 0x300
#define BCM43xx_MMIO_PIO2_BASE 0x310
#define BCM43xx_MMIO_PIO3_BASE 0x320
#define BCM43xx_MMIO_PIO4_BASE 0x330
+
#define BCM43xx_MMIO_PHY_VER 0x3E0
#define BCM43xx_MMIO_PHY_RADIO 0x3E2
#define BCM43xx_MMIO_ANTENNA 0x3E8
#define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
#define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
#define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
+#define BCM43xx_MMIO_RNG 0x65A
#define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
/* SPROM offsets. */
#define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
#define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
#define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
+#define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
+#define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
+#define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
+#define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
/* GPIO register offset, in both ChipCommon and PCI core. */
#define BCM43xx_GPIO_CONTROL 0x6c
#define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
/* sbtmstatehigh state flags */
-#define BCM43xx_SBTMSTATEHIGH_SERROR 0x1
-#define BCM43xx_SBTMSTATEHIGH_BUSY 0x4
+#define BCM43xx_SBTMSTATEHIGH_SERROR 0x00000001
+#define BCM43xx_SBTMSTATEHIGH_BUSY 0x00000004
+#define BCM43xx_SBTMSTATEHIGH_TIMEOUT 0x00000020
+#define BCM43xx_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
+#define BCM43xx_SBTMSTATEHIGH_DMA64BIT 0x10000000
+#define BCM43xx_SBTMSTATEHIGH_GATEDCLK 0x20000000
+#define BCM43xx_SBTMSTATEHIGH_BISTFAILED 0x40000000
+#define BCM43xx_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
/* sbimstate flags */
#define BCM43xx_SBIMSTATE_IB_ERROR 0x20000
#define BCM43xx_SBF_TIME_UPDATE 0x10000000
#define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
+/* Microcode */
+#define BCM43xx_UCODE_REVISION 0x0000
+#define BCM43xx_UCODE_PATCHLEVEL 0x0002
+#define BCM43xx_UCODE_DATE 0x0004
+#define BCM43xx_UCODE_TIME 0x0006
+#define BCM43xx_UCODE_STATUS 0x0040
+
/* MicrocodeFlagsBitfield (addr + lo-word values?)*/
#define BCM43xx_UCODEFLAGS_OFFSET 0x005E
/* Initial default iw_mode */
#define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA
-/* Values/Masks for the device TX header */
-#define BCM43xx_TXHDRFLAG_EXPECTACK 0x0001
-#define BCM43xx_TXHDRFLAG_FIRSTFRAGMENT 0x0008
-#define BCM43xx_TXHDRFLAG_DESTPSMODE 0x0020
-#define BCM43xx_TXHDRFLAG_FALLBACKOFDM 0x0100
-#define BCM43xx_TXHDRFLAG_FRAMEBURST 0x0800
-
-#define BCM43xx_TXHDRCTL_OFDM 0x0001
-#define BCM43xx_TXHDRCTL_SHORT_PREAMBLE 0x0010
-#define BCM43xx_TXHDRCTL_ANTENNADIV_MASK 0x0030
-#define BCM43xx_TXHDRCTL_ANTENNADIV_SHIFT 8
-
-#define BCM43xx_TXHDR_WSEC_KEYINDEX_MASK 0x00F0
-#define BCM43xx_TXHDR_WSEC_KEYINDEX_SHIFT 4
-#define BCM43xx_TXHDR_WSEC_ALGO_MASK 0x0003
-#define BCM43xx_TXHDR_WSEC_ALGO_SHIFT 0
-
/* Bus type PCI. */
#define BCM43xx_BUSTYPE_PCI 0
/* Bus type Silicone Backplane Bus. */
const s8 *tssi2dbm;
/* idle TSSI value */
s8 idle_tssi;
+
+ /* Values from bcm43xx_calc_loopback_gain() */
+ u16 loopback_gain[2];
+
/* PHY lock for core.rev < 3
* This lock is only used by bcm43xx_phy_{un}lock()
*/
spinlock_t lock;
+
+ /* Firmware. */
+ const struct firmware *ucode;
+ const struct firmware *pcm;
+ const struct firmware *initvals0;
+ const struct firmware *initvals1;
};
u16 version;
u8 revision;
- /* 0: baseband attenuation,
- * 1: radio attenuation,
- * 2: tx_CTL1
- * 3: tx_CTL2
- */
- u16 txpower[4];
/* Desired TX power in dBm Q5.2 */
u16 txpower_desired;
+ /* TX Power control values. */
+ union {
+ /* B/G PHY */
+ struct {
+ u16 baseband_atten;
+ u16 radio_atten;
+ u16 txctl1;
+ u16 txctl2;
+ };
+ /* A PHY */
+ struct {
+ u16 txpwr_offset;
+ };
+ };
+
/* Current Interference Mitigation mode */
int interfmode;
- /* Stack of saved values from the Interference Mitigation code */
- u16 interfstack[20];
+ /* Stack of saved values from the Interference Mitigation code.
+ * Each value in the stack is layed out as follows:
+ * bit 0-11: offset
+ * bit 12-15: register ID
+ * bit 16-32: value
+ * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
+ */
+#define BCM43xx_INTERFSTACK_SIZE 26
+ u32 interfstack[BCM43xx_INTERFSTACK_SIZE];
+
/* Saved values from the NRSSI Slope calculation */
s16 nrssi[2];
s32 nrssislope;
struct bcm43xx_dmaring *tx_ring1;
struct bcm43xx_dmaring *tx_ring2;
struct bcm43xx_dmaring *tx_ring3;
+ struct bcm43xx_dmaring *tx_ring4;
+ struct bcm43xx_dmaring *tx_ring5;
+
struct bcm43xx_dmaring *rx_ring0;
- struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */
+ struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */
};
/* Data structures for PIO transmission, per 80211 core. */
#define BCM43xx_MAX_80211_CORES 2
-#define BCM43xx_COREFLAG_AVAILABLE (1 << 0)
-#define BCM43xx_COREFLAG_ENABLED (1 << 1)
-#define BCM43xx_COREFLAG_INITIALIZED (1 << 2)
-
#ifdef CONFIG_BCM947XX
#define core_offset(bcm) (bcm)->current_core_offset
#else
#define core_offset(bcm) 0
#endif
+/* Generic information about a core. */
struct bcm43xx_coreinfo {
- /** Driver internal flags. See BCM43xx_COREFLAG_* */
- u32 flags;
- /** core_id ID number */
- u16 id;
+ u8 available:1,
+ enabled:1,
+ initialized:1;
/** core_rev revision number */
u8 rev;
/** Index number for _switch_core() */
u8 index;
- /* Pointer to the PHYinfo, which belongs to this core (if 80211 core) */
- struct bcm43xx_phyinfo *phy;
- /* Pointer to the RadioInfo, which belongs to this core (if 80211 core) */
- struct bcm43xx_radioinfo *radio;
- /* Pointer to the DMA rings, which belong to this core (if 80211 core) */
- struct bcm43xx_dma *dma;
- /* Pointer to the PIO queues, which belong to this core (if 80211 core) */
- struct bcm43xx_pio *pio;
+ /** core_id ID number */
+ u16 id;
+ /** Core-specific data. */
+ void *priv;
+};
+
+/* Additional information for each 80211 core. */
+struct bcm43xx_coreinfo_80211 {
+ /* PHY device. */
+ struct bcm43xx_phyinfo phy;
+ /* Radio device. */
+ struct bcm43xx_radioinfo radio;
+ union {
+ /* DMA context. */
+ struct bcm43xx_dma dma;
+ /* PIO context. */
+ struct bcm43xx_pio pio;
+ };
};
/* Context information for a noise calculation (Link Quality). */
};
struct bcm43xx_stats {
- u8 link_quality;
+ u8 noise;
+ struct iw_statistics wstats;
/* Store the last TX/RX times here for updating the leds. */
unsigned long last_tx;
unsigned long last_rx;
u8 algorithm;
};
+/* Driver initialization status. */
+enum {
+ BCM43xx_STAT_UNINIT, /* Uninitialized. */
+ BCM43xx_STAT_INITIALIZING, /* init_board() in progress. */
+ BCM43xx_STAT_INITIALIZED, /* Fully operational. */
+ BCM43xx_STAT_SHUTTINGDOWN, /* free_board() in progress. */
+ BCM43xx_STAT_RESTARTING, /* controller_restart() called. */
+};
+#define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status)
+#define bcm43xx_set_status(bcm, stat) do { \
+ atomic_set(&(bcm)->init_status, (stat)); \
+ smp_wmb(); \
+ } while (0)
+
+/* *** THEORY OF LOCKING ***
+ *
+ * We have two different locks in the bcm43xx driver.
+ * => bcm->mutex: General sleeping mutex. Protects struct bcm43xx_private
+ * and the device registers. This mutex does _not_ protect
+ * against concurrency from the IRQ handler.
+ * => bcm->irq_lock: IRQ spinlock. Protects against IRQ handler concurrency.
+ *
+ * Please note that, if you only take the irq_lock, you are not protected
+ * against concurrency from the periodic work handlers.
+ * Most times you want to take _both_ locks.
+ */
+
struct bcm43xx_private {
struct ieee80211_device *ieee;
struct ieee80211softmac_device *softmac;
unsigned int irq;
void __iomem *mmio_addr;
- unsigned int mmio_len;
- spinlock_t lock;
+ spinlock_t irq_lock;
+ struct mutex mutex;
+
+ /* Driver initialization status BCM43xx_STAT_*** */
+ atomic_t init_status;
- /* Driver status flags. */
- u32 initialized:1, /* init_board() succeed */
- was_initialized:1, /* for PCI suspend/resume. */
- shutting_down:1, /* free_board() in progress */
+ u16 was_initialized:1, /* for PCI suspend/resume. */
__using_pio:1, /* Internal, use bcm43xx_using_pio(). */
bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */
reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */
- powersaving:1, /* TRUE if we are in PowerSaving mode. FALSE otherwise. */
short_preamble:1, /* TRUE, if short preamble is enabled. */
firmware_norelease:1; /* Do not release the firmware. Used on suspend. */
u16 chip_id;
u8 chip_rev;
+ u8 chip_package;
struct bcm43xx_sprominfo sprom;
#define BCM43xx_NR_LEDS 4
struct bcm43xx_led leds[BCM43xx_NR_LEDS];
+ spinlock_t leds_lock;
- /* The currently active core. NULL if not initialized, yet. */
+ /* The currently active core. */
struct bcm43xx_coreinfo *current_core;
#ifdef CONFIG_BCM947XX
/** current core memory offset */
*/
struct bcm43xx_coreinfo core_chipcommon;
struct bcm43xx_coreinfo core_pci;
- struct bcm43xx_coreinfo core_v90;
- struct bcm43xx_coreinfo core_pcmcia;
- struct bcm43xx_coreinfo core_ethernet;
struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
- /* Info about the PHY for each 80211 core. */
- struct bcm43xx_phyinfo phy[ BCM43xx_MAX_80211_CORES ];
- /* Info about the Radio for each 80211 core. */
- struct bcm43xx_radioinfo radio[ BCM43xx_MAX_80211_CORES ];
- /* DMA */
- struct bcm43xx_dma dma[ BCM43xx_MAX_80211_CORES ];
- /* PIO */
- struct bcm43xx_pio pio[ BCM43xx_MAX_80211_CORES ];
+ /* Additional information, specific to the 80211 cores. */
+ struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ];
+ /* Number of available 80211 cores. */
+ int nr_80211_available;
u32 chipcommon_capabilities;
/* Reason code of the last interrupt. */
u32 irq_reason;
- u32 dma_reason[4];
+ u32 dma_reason[6];
/* saved irq enable/disable state bitfield. */
u32 irq_savedstate;
/* Link Quality calculation context. */
struct bcm43xx_noise_calculation noisecalc;
+ /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
+ int mac_suspended;
/* Threshold values. */
//TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
struct tasklet_struct isr_tasklet;
/* Periodic tasks */
- struct timer_list periodic_tasks;
+ struct delayed_work periodic_work;
unsigned int periodic_state;
struct work_struct restart_work;
struct bcm43xx_key key[54];
u8 default_key_idx;
- /* Firmware. */
- const struct firmware *ucode;
- const struct firmware *pcm;
- const struct firmware *initvals0;
- const struct firmware *initvals1;
+ /* Random Number Generator. */
+ struct hwrng rng;
+ char rng_name[20 + 1];
/* Debugging stuff follows. */
#ifdef CONFIG_BCM43XX_DEBUG
struct bcm43xx_dfsentry *dfsentry;
- atomic_t mmio_print_cnt;
- atomic_t pcicfg_print_cnt;
#endif
};
+
static inline
struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
{
return ieee80211softmac_priv(dev);
}
+struct device;
+
+static inline
+struct bcm43xx_private * dev_to_bcm(struct device *dev)
+{
+ struct net_device *net_dev;
+ struct bcm43xx_private *bcm;
+
+ net_dev = dev_get_drvdata(dev);
+ bcm = bcm43xx_priv(net_dev);
+
+ return bcm;
+}
+
/* Helper function, which returns a boolean.
* TRUE, if PIO is used; FALSE, if DMA is used.
# error "Using neither DMA nor PIO? Confused..."
#endif
-
+/* Helper functions to access data structures private to the 80211 cores.
+ * Note that we _must_ have an 80211 core mapped when calling
+ * any of these functions.
+ */
static inline
-int bcm43xx_num_80211_cores(struct bcm43xx_private *bcm)
+struct bcm43xx_coreinfo_80211 *
+bcm43xx_current_80211_priv(struct bcm43xx_private *bcm)
{
- int i, cnt = 0;
-
- for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
- if (bcm->core_80211[i].flags & BCM43xx_COREFLAG_AVAILABLE)
- cnt++;
- }
-
- return cnt;
+ assert(bcm->current_core->id == BCM43xx_COREID_80211);
+ return bcm->current_core->priv;
}
-
-/* Are we running in init_board() context? */
static inline
-int bcm43xx_is_initializing(struct bcm43xx_private *bcm)
+struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm)
{
- if (bcm->initialized)
- return 0;
- if (bcm->shutting_down)
- return 0;
- return 1;
+ assert(bcm43xx_using_pio(bcm));
+ return &(bcm43xx_current_80211_priv(bcm)->pio);
+}
+static inline
+struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm)
+{
+ assert(!bcm43xx_using_pio(bcm));
+ return &(bcm43xx_current_80211_priv(bcm)->dma);
}
+static inline
+struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm)
+{
+ return &(bcm43xx_current_80211_priv(bcm)->phy);
+}
+static inline
+struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm)
+{
+ return &(bcm43xx_current_80211_priv(bcm)->radio);
+}
+
static inline
struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
}
-/* MMIO read/write functions. Debug and non-debug variants. */
-#ifdef CONFIG_BCM43XX_DEBUG
-
static inline
u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
{
- u16 value;
-
- value = ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
- if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) {
- printk(KERN_INFO PFX "ioread16 offset: 0x%04x, value: 0x%04x\n",
- offset, value);
- }
-
- return value;
+ return ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
}
static inline
void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
{
iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset);
- if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) {
- printk(KERN_INFO PFX "iowrite16 offset: 0x%04x, value: 0x%04x\n",
- offset, value);
- }
}
static inline
u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
{
- u32 value;
-
- value = ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
- if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) {
- printk(KERN_INFO PFX "ioread32 offset: 0x%04x, value: 0x%08x\n",
- offset, value);
- }
-
- return value;
+ return ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
}
static inline
void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
{
iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset);
- if (unlikely(atomic_read(&bcm->mmio_print_cnt) > 0)) {
- printk(KERN_INFO PFX "iowrite32 offset: 0x%04x, value: 0x%08x\n",
- offset, value);
- }
}
static inline
int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
{
- int err;
-
- err = pci_read_config_word(bcm->pci_dev, offset, value);
- if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) {
- printk(KERN_INFO PFX "pciread16 offset: 0x%08x, value: 0x%04x, err: %d\n",
- offset, *value, err);
- }
-
- return err;
+ return pci_read_config_word(bcm->pci_dev, offset, value);
}
static inline
int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
{
- int err;
-
- err = pci_read_config_dword(bcm->pci_dev, offset, value);
- if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) {
- printk(KERN_INFO PFX "pciread32 offset: 0x%08x, value: 0x%08x, err: %d\n",
- offset, *value, err);
- }
-
- return err;
+ return pci_read_config_dword(bcm->pci_dev, offset, value);
}
static inline
int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
{
- int err;
-
- err = pci_write_config_word(bcm->pci_dev, offset, value);
- if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) {
- printk(KERN_INFO PFX "pciwrite16 offset: 0x%08x, value: 0x%04x, err: %d\n",
- offset, value, err);
- }
-
- return err;
+ return pci_write_config_word(bcm->pci_dev, offset, value);
}
static inline
int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
{
- int err;
-
- err = pci_write_config_dword(bcm->pci_dev, offset, value);
- if (unlikely(atomic_read(&bcm->pcicfg_print_cnt) > 0)) {
- printk(KERN_INFO PFX "pciwrite32 offset: 0x%08x, value: 0x%08x, err: %d\n",
- offset, value, err);
- }
-
- return err;
+ return pci_write_config_dword(bcm->pci_dev, offset, value);
}
-#define bcm43xx_mmioprint_initial(bcm, value) atomic_set(&(bcm)->mmio_print_cnt, (value))
-#define bcm43xx_mmioprint_enable(bcm) atomic_inc(&(bcm)->mmio_print_cnt)
-#define bcm43xx_mmioprint_disable(bcm) atomic_dec(&(bcm)->mmio_print_cnt)
-#define bcm43xx_pciprint_initial(bcm, value) atomic_set(&(bcm)->pcicfg_print_cnt, (value))
-#define bcm43xx_pciprint_enable(bcm) atomic_inc(&(bcm)->pcicfg_print_cnt)
-#define bcm43xx_pciprint_disable(bcm) atomic_dec(&(bcm)->pcicfg_print_cnt)
-
-#else /* CONFIG_BCM43XX_DEBUG*/
-
-#define bcm43xx_read16(bcm, offset) ioread16((bcm)->mmio_addr + core_offset(bcm) + (offset))
-#define bcm43xx_write16(bcm, offset, value) iowrite16((value), (bcm)->mmio_addr + core_offset(bcm) + (offset))
-#define bcm43xx_read32(bcm, offset) ioread32((bcm)->mmio_addr + core_offset(bcm) + (offset))
-#define bcm43xx_write32(bcm, offset, value) iowrite32((value), (bcm)->mmio_addr + core_offset(bcm) + (offset))
-#define bcm43xx_pci_read_config16(bcm, o, v) pci_read_config_word((bcm)->pci_dev, (o), (v))
-#define bcm43xx_pci_read_config32(bcm, o, v) pci_read_config_dword((bcm)->pci_dev, (o), (v))
-#define bcm43xx_pci_write_config16(bcm, o, v) pci_write_config_word((bcm)->pci_dev, (o), (v))
-#define bcm43xx_pci_write_config32(bcm, o, v) pci_write_config_dword((bcm)->pci_dev, (o), (v))
-
-#define bcm43xx_mmioprint_initial(x, y) do { /* nothing */ } while (0)
-#define bcm43xx_mmioprint_enable(x) do { /* nothing */ } while (0)
-#define bcm43xx_mmioprint_disable(x) do { /* nothing */ } while (0)
-#define bcm43xx_pciprint_initial(bcm, value) do { /* nothing */ } while (0)
-#define bcm43xx_pciprint_enable(bcm) do { /* nothing */ } while (0)
-#define bcm43xx_pciprint_disable(bcm) do { /* nothing */ } while (0)
-
-#endif /* CONFIG_BCM43XX_DEBUG*/
-
-
/** Limit a value between two limits */
#ifdef limit_value
# undef limit_value
__value; \
})
+/** Helpers to print MAC addresses. */
+#define BCM43xx_MACFMT "%02x:%02x:%02x:%02x:%02x:%02x"
+#define BCM43xx_MACARG(x) ((u8*)(x))[0], ((u8*)(x))[1], \
+ ((u8*)(x))[2], ((u8*)(x))[3], \
+ ((u8*)(x))[4], ((u8*)(x))[5]
+
#endif /* BCM43xx_H_ */
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