* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Changed to conform redesigned i.MX scatter gather DMA interface
- *
- * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * Updated for 2.6.14 kernel
- *
- * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
- * Found and corrected problems in the write path
- *
- * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- * The event handling rewritten right way in softirq.
- * Added many ugly hacks and delays to overcome SDHC
- * deficiencies
- *
*/
#include <linux/module.h>
#include <linux/mmc/card.h>
#include <linux/delay.h>
#include <linux/clk.h>
+#include <linux/io.h>
#include <asm/dma.h>
-#include <asm/io.h>
#include <asm/irq.h>
#include <asm/sizes.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/imx-dma.h>
+#include <mach/mmc.h>
+#include <mach/imx-dma.h>
#include "imxmmc.h"
#define DRIVER_NAME "imx-mmc"
#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
- INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
- INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
+ INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
+ INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
struct imxmci_host {
struct mmc_host *mmc;
spinlock_t lock;
struct resource *res;
+ void __iomem *base;
int irq;
imx_dmach_t dma;
- unsigned int clkrt;
- unsigned int cmdat;
volatile unsigned int imask;
unsigned int power_mode;
unsigned int present;
struct tasklet_struct tasklet;
unsigned int status_reg;
unsigned long pending_events;
- /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
+ /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
u16 *data_ptr;
unsigned int data_cnt;
atomic_t stuck_timeout;
static void imxmci_stop_clock(struct imxmci_host *host)
{
int i = 0;
- MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
- while(i < 0x1000) {
- if(!(i & 0x7f))
- MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
+ u16 reg;
+
+ reg = readw(host->base + MMC_REG_STR_STP_CLK);
+ writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
+ while (i < 0x1000) {
+ if (!(i & 0x7f)) {
+ reg = readw(host->base + MMC_REG_STR_STP_CLK);
+ writew(reg | STR_STP_CLK_STOP_CLK,
+ host->base + MMC_REG_STR_STP_CLK);
+ }
- if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
+ reg = readw(host->base + MMC_REG_STATUS);
+ if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
/* Check twice before cut */
- if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
+ reg = readw(host->base + MMC_REG_STATUS);
+ if (!(reg & STATUS_CARD_BUS_CLK_RUN))
return;
}
unsigned int trials = 0;
unsigned int delay_limit = 128;
unsigned long flags;
+ u16 reg;
- MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
+ reg = readw(host->base + MMC_REG_STR_STP_CLK);
+ writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
* then 6 delay loops, but during card detection (low clockrate)
* it takes up to 5000 delay loops and sometimes fails for the first time
*/
- MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
+ reg = readw(host->base + MMC_REG_STR_STP_CLK);
+ writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
do {
unsigned int delay = delay_limit;
- while(delay--){
- if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
+ while (delay--) {
+ reg = readw(host->base + MMC_REG_STATUS);
+ if (reg & STATUS_CARD_BUS_CLK_RUN)
/* Check twice before cut */
- if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
+ reg = readw(host->base + MMC_REG_STATUS);
+ if (reg & STATUS_CARD_BUS_CLK_RUN)
return 0;
- if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
+ if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
return 0;
}
* IRQ or schedule delays this function execution and the clocks has
* been already stopped by other means (response processing, SDHC HW)
*/
- if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
- MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
+ if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
+ reg = readw(host->base + MMC_REG_STR_STP_CLK);
+ writew(reg | STR_STP_CLK_START_CLK,
+ host->base + MMC_REG_STR_STP_CLK);
+ }
local_irq_restore(flags);
- } while(++trials<256);
+ } while (++trials < 256);
dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
return -1;
}
-static void imxmci_softreset(void)
+static void imxmci_softreset(struct imxmci_host *host)
{
+ int i;
+
/* reset sequence */
- MMC_STR_STP_CLK = 0x8;
- MMC_STR_STP_CLK = 0xD;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
- MMC_STR_STP_CLK = 0x5;
-
- MMC_RES_TO = 0xff;
- MMC_BLK_LEN = 512;
- MMC_NOB = 1;
+ writew(0x08, host->base + MMC_REG_STR_STP_CLK);
+ writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
+
+ for (i = 0; i < 8; i++)
+ writew(0x05, host->base + MMC_REG_STR_STP_CLK);
+
+ writew(0xff, host->base + MMC_REG_RES_TO);
+ writew(512, host->base + MMC_REG_BLK_LEN);
+ writew(1, host->base + MMC_REG_NOB);
}
static int imxmci_busy_wait_for_status(struct imxmci_host *host,
- unsigned int *pstat, unsigned int stat_mask,
- int timeout, const char *where)
+ unsigned int *pstat, unsigned int stat_mask,
+ int timeout, const char *where)
{
- int loops=0;
- while(!(*pstat & stat_mask)) {
- loops+=2;
- if(loops >= timeout) {
+ int loops = 0;
+
+ while (!(*pstat & stat_mask)) {
+ loops += 2;
+ if (loops >= timeout) {
dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
where, *pstat, stat_mask);
return -1;
}
udelay(2);
- *pstat |= MMC_STATUS;
+ *pstat |= readw(host->base + MMC_REG_STATUS);
}
- if(!loops)
+ if (!loops)
return 0;
/* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
- if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
+ if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
- loops, where, *pstat, stat_mask);
+ loops, where, *pstat, stat_mask);
return loops;
}
host->data = data;
data->bytes_xfered = 0;
- MMC_NOB = nob;
- MMC_BLK_LEN = blksz;
+ writew(nob, host->base + MMC_REG_NOB);
+ writew(blksz, host->base + MMC_REG_BLK_LEN);
/*
* DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
host->dma_dir = DMA_FROM_DEVICE;
/* Hack to enable read SCR */
- MMC_NOB = 1;
- MMC_BLK_LEN = 512;
+ writew(1, host->base + MMC_REG_NOB);
+ writew(512, host->base + MMC_REG_BLK_LEN);
} else {
host->dma_dir = DMA_TO_DEVICE;
}
/* Convert back to virtual address */
- host->data_ptr = (u16*)sg_virt(data->sg);
+ host->data_ptr = (u16 *)sg_virt(data->sg);
host->data_cnt = 0;
clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
if (data->flags & MMC_DATA_READ) {
host->dma_dir = DMA_FROM_DEVICE;
host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
- data->sg_len, host->dma_dir);
+ data->sg_len, host->dma_dir);
imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
- host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
+ host->res->start + MMC_REG_BUFFER_ACCESS,
+ DMA_MODE_READ);
/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
host->dma_dir = DMA_TO_DEVICE;
host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
- data->sg_len, host->dma_dir);
+ data->sg_len, host->dma_dir);
imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
- host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
+ host->res->start + MMC_REG_BUFFER_ACCESS,
+ DMA_MODE_WRITE);
/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
#if 1 /* This code is there only for consistency checking and can be disabled in future */
host->dma_size = 0;
- for(i=0; i<host->dma_nents; i++)
- host->dma_size+=data->sg[i].length;
+ for (i = 0; i < host->dma_nents; i++)
+ host->dma_size += data->sg[i].length;
if (datasz > host->dma_size) {
dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
- datasz, host->dma_size);
+ datasz, host->dma_size);
}
#endif
wmb();
- if(host->actual_bus_width == MMC_BUS_WIDTH_4)
- BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
- else
- BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
-
- RSSR(host->dma) = DMA_REQ_SDHC;
-
set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
/* start DMA engine for read, write is delayed after initial response */
- if (host->dma_dir == DMA_FROM_DEVICE) {
+ if (host->dma_dir == DMA_FROM_DEVICE)
imx_dma_enable(host->dma);
- }
}
static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
break;
}
- if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
+ if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
- if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
+ if (host->actual_bus_width == MMC_BUS_WIDTH_4)
cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
- MMC_CMD = cmd->opcode;
- MMC_ARGH = cmd->arg >> 16;
- MMC_ARGL = cmd->arg & 0xffff;
- MMC_CMD_DAT_CONT = cmdat;
+ writew(cmd->opcode, host->base + MMC_REG_CMD);
+ writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
+ writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
+ writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
atomic_set(&host->stuck_timeout, 0);
set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
imask = IMXMCI_INT_MASK_DEFAULT;
imask &= ~INT_MASK_END_CMD_RES;
- if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
- /*imask &= ~INT_MASK_BUF_READY;*/
+ if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
+ /* imask &= ~INT_MASK_BUF_READY; */
imask &= ~INT_MASK_DATA_TRAN;
- if ( cmdat & CMD_DAT_CONT_WRITE )
+ if (cmdat & CMD_DAT_CONT_WRITE)
imask &= ~INT_MASK_WRITE_OP_DONE;
- if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
+ if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
imask &= ~INT_MASK_BUF_READY;
}
spin_lock_irqsave(&host->lock, flags);
host->imask = imask;
- MMC_INT_MASK = host->imask;
+ writew(host->imask, host->base + MMC_REG_INT_MASK);
spin_unlock_irqrestore(&host->lock, flags);
dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
spin_lock_irqsave(&host->lock, flags);
host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
- IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
+ IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
host->imask = IMXMCI_INT_MASK_DEFAULT;
- MMC_INT_MASK = host->imask;
+ writew(host->imask, host->base + MMC_REG_INT_MASK);
spin_unlock_irqrestore(&host->lock, flags);
- if(req && req->cmd)
+ if (req && req->cmd)
host->prev_cmd_code = req->cmd->opcode;
host->req = NULL;
struct mmc_data *data = host->data;
int data_error;
- if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
+ if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
imx_dma_disable(host->dma);
dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
host->dma_dir);
}
- if ( stat & STATUS_ERR_MASK ) {
- dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
- if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
+ if (stat & STATUS_ERR_MASK) {
+ dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
+ if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
data->error = -EILSEQ;
- else if(stat & STATUS_TIME_OUT_READ)
+ else if (stat & STATUS_TIME_OUT_READ)
data->error = -ETIMEDOUT;
else
data->error = -EIO;
{
struct mmc_command *cmd = host->cmd;
int i;
- u32 a,b,c;
+ u32 a, b, c;
struct mmc_data *data = host->data;
if (!cmd)
cmd->error = -EILSEQ;
}
- if(cmd->flags & MMC_RSP_PRESENT) {
- if(cmd->flags & MMC_RSP_136) {
+ if (cmd->flags & MMC_RSP_PRESENT) {
+ if (cmd->flags & MMC_RSP_136) {
for (i = 0; i < 4; i++) {
- u32 a = MMC_RES_FIFO & 0xffff;
- u32 b = MMC_RES_FIFO & 0xffff;
- cmd->resp[i] = a<<16 | b;
+ a = readw(host->base + MMC_REG_RES_FIFO);
+ b = readw(host->base + MMC_REG_RES_FIFO);
+ cmd->resp[i] = a << 16 | b;
}
} else {
- a = MMC_RES_FIFO & 0xffff;
- b = MMC_RES_FIFO & 0xffff;
- c = MMC_RES_FIFO & 0xffff;
- cmd->resp[0] = a<<24 | b<<8 | c>>8;
+ a = readw(host->base + MMC_REG_RES_FIFO);
+ b = readw(host->base + MMC_REG_RES_FIFO);
+ c = readw(host->base + MMC_REG_RES_FIFO);
+ cmd->resp[0] = a << 24 | b << 8 | c >> 8;
}
}
/* Wait for FIFO to be empty before starting DMA write */
- stat = MMC_STATUS;
- if(imxmci_busy_wait_for_status(host, &stat,
- STATUS_APPL_BUFF_FE,
- 40, "imxmci_cmd_done DMA WR") < 0) {
+ stat = readw(host->base + MMC_REG_STATUS);
+ if (imxmci_busy_wait_for_status(host, &stat,
+ STATUS_APPL_BUFF_FE,
+ 40, "imxmci_cmd_done DMA WR") < 0) {
cmd->error = -EIO;
imxmci_finish_data(host, stat);
- if(host->req)
+ if (host->req)
imxmci_finish_request(host, host->req);
dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
- stat);
+ stat);
return 0;
}
- if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
+ if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
imx_dma_enable(host->dma);
- }
}
} else {
struct mmc_request *req;
imxmci_stop_clock(host);
req = host->req;
- if(data)
+ if (data)
imxmci_finish_data(host, stat);
- if( req ) {
+ if (req)
imxmci_finish_request(host, req);
- } else {
+ else
dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
- }
}
return 1;
} else {
struct mmc_request *req;
req = host->req;
- if( req ) {
+ if (req)
imxmci_finish_request(host, req);
- } else {
+ else
dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
- }
}
return 1;
int trans_done = 0;
unsigned int stat = *pstat;
- if(host->actual_bus_width != MMC_BUS_WIDTH_4)
+ if (host->actual_bus_width != MMC_BUS_WIDTH_4)
burst_len = 16;
else
burst_len = 64;
udelay(20); /* required for clocks < 8MHz*/
- if(host->dma_dir == DMA_FROM_DEVICE) {
+ if (host->dma_dir == DMA_FROM_DEVICE) {
imxmci_busy_wait_for_status(host, &stat,
- STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
- STATUS_TIME_OUT_READ,
- 50, "imxmci_cpu_driven_data read");
+ STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
+ STATUS_TIME_OUT_READ,
+ 50, "imxmci_cpu_driven_data read");
- while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
- !(stat & STATUS_TIME_OUT_READ) &&
- (host->data_cnt < 512)) {
+ while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
+ !(stat & STATUS_TIME_OUT_READ) &&
+ (host->data_cnt < 512)) {
udelay(20); /* required for clocks < 8MHz*/
- for(i = burst_len; i>=2 ; i-=2) {
+ for (i = burst_len; i >= 2 ; i -= 2) {
u16 data;
- data = MMC_BUFFER_ACCESS;
+ data = readw(host->base + MMC_REG_BUFFER_ACCESS);
udelay(10); /* required for clocks < 8MHz*/
- if(host->data_cnt+2 <= host->dma_size) {
+ if (host->data_cnt+2 <= host->dma_size) {
*(host->data_ptr++) = data;
} else {
- if(host->data_cnt < host->dma_size)
- *(u8*)(host->data_ptr) = data;
+ if (host->data_cnt < host->dma_size)
+ *(u8 *)(host->data_ptr) = data;
}
host->data_cnt += 2;
}
- stat = MMC_STATUS;
+ stat = readw(host->base + MMC_REG_STATUS);
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
host->data_cnt, burst_len, stat);
}
- if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
+ if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
trans_done = 1;
- if(host->dma_size & 0x1ff)
+ if (host->dma_size & 0x1ff)
stat &= ~STATUS_CRC_READ_ERR;
- if(stat & STATUS_TIME_OUT_READ) {
+ if (stat & STATUS_TIME_OUT_READ) {
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
stat);
trans_done = -1;
} else {
imxmci_busy_wait_for_status(host, &stat,
- STATUS_APPL_BUFF_FE,
- 20, "imxmci_cpu_driven_data write");
+ STATUS_APPL_BUFF_FE,
+ 20, "imxmci_cpu_driven_data write");
- while((stat & STATUS_APPL_BUFF_FE) &&
- (host->data_cnt < host->dma_size)) {
- if(burst_len >= host->dma_size - host->data_cnt) {
+ while ((stat & STATUS_APPL_BUFF_FE) &&
+ (host->data_cnt < host->dma_size)) {
+ if (burst_len >= host->dma_size - host->data_cnt) {
burst_len = host->dma_size - host->data_cnt;
host->data_cnt = host->dma_size;
trans_done = 1;
host->data_cnt += burst_len;
}
- for(i = burst_len; i>0 ; i-=2)
- MMC_BUFFER_ACCESS = *(host->data_ptr++);
+ for (i = burst_len; i > 0 ; i -= 2)
+ writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
- stat = MMC_STATUS;
+ stat = readw(host->base + MMC_REG_STATUS);
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
burst_len, stat);
static void imxmci_dma_irq(int dma, void *devid)
{
struct imxmci_host *host = devid;
- uint32_t stat = MMC_STATUS;
+ u32 stat = readw(host->base + MMC_REG_STATUS);
atomic_set(&host->stuck_timeout, 0);
host->status_reg = stat;
static irqreturn_t imxmci_irq(int irq, void *devid)
{
struct imxmci_host *host = devid;
- uint32_t stat = MMC_STATUS;
+ u32 stat = readw(host->base + MMC_REG_STATUS);
int handled = 1;
- MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
+ writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
+ host->base + MMC_REG_INT_MASK);
atomic_set(&host->stuck_timeout, 0);
host->status_reg = stat;
set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
tasklet_schedule(&host->tasklet);
- return IRQ_RETVAL(handled);;
+ return IRQ_RETVAL(handled);
}
static void imxmci_tasklet_fnc(unsigned long data)
unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
int timeout = 0;
- if(atomic_read(&host->stuck_timeout) > 4) {
+ if (atomic_read(&host->stuck_timeout) > 4) {
char *what;
timeout = 1;
- stat = MMC_STATUS;
+ stat = readw(host->base + MMC_REG_STATUS);
host->status_reg = stat;
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
what = "RESP";
else
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
- if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
+ if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
what = "DATA";
else
what = "DMA";
else
what = "???";
- dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
- what, stat, MMC_INT_MASK);
- dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
- MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
+ dev_err(mmc_dev(host->mmc),
+ "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
+ what, stat,
+ readw(host->base + MMC_REG_INT_MASK));
+ dev_err(mmc_dev(host->mmc),
+ "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
+ readw(host->base + MMC_REG_CMD_DAT_CONT),
+ readw(host->base + MMC_REG_BLK_LEN),
+ readw(host->base + MMC_REG_NOB),
+ CCR(host->dma));
dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
- host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
+ host->cmd ? host->cmd->opcode : 0,
+ host->prev_cmd_code,
+ 1 << host->actual_bus_width, host->dma_size);
}
- if(!host->present || timeout)
+ if (!host->present || timeout)
host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
- STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
+ STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
- if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
+ if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
- stat = MMC_STATUS;
+ stat = readw(host->base + MMC_REG_STATUS);
/*
* This is not required in theory, but there is chance to miss some flag
* which clears automatically by mask write, FreeScale original code keeps
*/
stat |= host->status_reg;
- if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
+ if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
stat &= ~STATUS_CRC_READ_ERR;
- if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
+ if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
imxmci_busy_wait_for_status(host, &stat,
- STATUS_END_CMD_RESP | STATUS_ERR_MASK,
- 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
+ STATUS_END_CMD_RESP | STATUS_ERR_MASK,
+ 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
}
- if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
- if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+ if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
+ if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
imxmci_cmd_done(host, stat);
- if(host->data && (stat & STATUS_ERR_MASK))
+ if (host->data && (stat & STATUS_ERR_MASK))
imxmci_data_done(host, stat);
}
- if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
- stat |= MMC_STATUS;
- if(imxmci_cpu_driven_data(host, &stat)){
- if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+ if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
+ stat |= readw(host->base + MMC_REG_STATUS);
+ if (imxmci_cpu_driven_data(host, &stat)) {
+ if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
imxmci_cmd_done(host, stat);
atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
- &host->pending_events);
+ &host->pending_events);
imxmci_data_done(host, stat);
}
}
}
- if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
- !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
+ if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
+ !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
- stat = MMC_STATUS;
+ stat = readw(host->base + MMC_REG_STATUS);
/* Same as above */
stat |= host->status_reg;
- if(host->dma_dir == DMA_TO_DEVICE) {
+ if (host->dma_dir == DMA_TO_DEVICE)
data_dir_mask = STATUS_WRITE_OP_DONE;
- } else {
+ else
data_dir_mask = STATUS_DATA_TRANS_DONE;
- }
- if(stat & data_dir_mask) {
+ if (stat & data_dir_mask) {
clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
imxmci_data_done(host, stat);
}
}
- if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
+ if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
- if(host->cmd)
+ if (host->cmd)
imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
- if(host->data)
+ if (host->data)
imxmci_data_done(host, STATUS_TIME_OUT_READ |
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
- if(host->req)
+ if (host->req)
imxmci_finish_request(host, host->req);
mmc_detect_change(host->mmc, msecs_to_jiffies(100));
if (req->data->flags & MMC_DATA_WRITE)
cmdat |= CMD_DAT_CONT_WRITE;
- if (req->data->flags & MMC_DATA_STREAM) {
+ if (req->data->flags & MMC_DATA_STREAM)
cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
- }
}
imxmci_start_cmd(host, req->cmd, cmdat);
struct imxmci_host *host = mmc_priv(mmc);
int prescaler;
- if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
+ if (ios->bus_width == MMC_BUS_WIDTH_4) {
host->actual_bus_width = MMC_BUS_WIDTH_4;
imx_gpio_mode(PB11_PF_SD_DAT3);
- }else{
+ BLR(host->dma) = 0; /* burst 64 byte read/write */
+ } else {
host->actual_bus_width = MMC_BUS_WIDTH_1;
imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
+ BLR(host->dma) = 16; /* burst 16 byte read/write */
}
- if ( host->power_mode != ios->power_mode ) {
+ if (host->power_mode != ios->power_mode) {
switch (ios->power_mode) {
case MMC_POWER_OFF:
- break;
+ break;
case MMC_POWER_UP:
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
- break;
+ break;
case MMC_POWER_ON:
- break;
+ break;
}
host->power_mode = ios->power_mode;
}
- if ( ios->clock ) {
+ if (ios->clock) {
unsigned int clk;
+ u16 reg;
/* The prescaler is 5 for PERCLK2 equal to 96MHz
* then 96MHz / 5 = 19.2 MHz
*/
clk = clk_get_rate(host->clk);
- prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
- switch(prescaler) {
+ prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
+ switch (prescaler) {
case 0:
case 1: prescaler = 0;
break;
dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
clk, prescaler);
- for(clk=0; clk<8; clk++) {
+ for (clk = 0; clk < 8; clk++) {
int x;
- x = CLK_RATE / (1<<clk);
- if( x <= ios->clock)
+ x = CLK_RATE / (1 << clk);
+ if (x <= ios->clock)
break;
}
- MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
+ /* enable controller */
+ reg = readw(host->base + MMC_REG_STR_STP_CLK);
+ writew(reg | STR_STP_CLK_ENABLE,
+ host->base + MMC_REG_STR_STP_CLK);
imxmci_stop_clock(host);
- MMC_CLK_RATE = (prescaler<<3) | clk;
+ writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
/*
* Under my understanding, clock should not be started there, because it would
* initiate SDHC sequencer and send last or random command into card
*/
- /*imxmci_start_clock(host);*/
+ /* imxmci_start_clock(host); */
- dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
+ dev_dbg(mmc_dev(host->mmc),
+ "MMC_CLK_RATE: 0x%08x\n",
+ readw(host->base + MMC_REG_CLK_RATE));
} else {
imxmci_stop_clock(host);
}
.get_ro = imxmci_get_ro,
};
-static struct resource *platform_device_resource(struct platform_device *dev, unsigned int mask, int nr)
-{
- int i;
-
- for (i = 0; i < dev->num_resources; i++)
- if (dev->resource[i].flags == mask && nr-- == 0)
- return &dev->resource[i];
- return NULL;
-}
-
-static int platform_device_irq(struct platform_device *dev, int nr)
-{
- int i;
-
- for (i = 0; i < dev->num_resources; i++)
- if (dev->resource[i].flags == IORESOURCE_IRQ && nr-- == 0)
- return dev->resource[i].start;
- return NO_IRQ;
-}
-
static void imxmci_check_status(unsigned long data)
{
struct imxmci_host *host = (struct imxmci_host *)data;
- if( host->pdata->card_present(mmc_dev(host->mmc)) != host->present ) {
+ if (host->pdata && host->pdata->card_present &&
+ host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
host->present ^= 1;
dev_info(mmc_dev(host->mmc), "card %s\n",
host->present ? "inserted" : "removed");
tasklet_schedule(&host->tasklet);
}
- if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
- test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
+ if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
+ test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
atomic_inc(&host->stuck_timeout);
- if(atomic_read(&host->stuck_timeout) > 4)
+ if (atomic_read(&host->stuck_timeout) > 4)
tasklet_schedule(&host->tasklet);
} else {
atomic_set(&host->stuck_timeout, 0);
mod_timer(&host->timer, jiffies + (HZ>>1));
}
-static int imxmci_probe(struct platform_device *pdev)
+static int __init imxmci_probe(struct platform_device *pdev)
{
struct mmc_host *mmc;
struct imxmci_host *host = NULL;
struct resource *r;
int ret = 0, irq;
+ u16 rev_no;
printk(KERN_INFO "i.MX mmc driver\n");
- r = platform_device_resource(pdev, IORESOURCE_MEM, 0);
- irq = platform_device_irq(pdev, 0);
- if (!r || irq == NO_IRQ)
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irq = platform_get_irq(pdev, 0);
+ if (!r || irq < 0)
return -ENXIO;
- r = request_mem_region(r->start, 0x100, "IMXMCI");
+ r = request_mem_region(r->start, resource_size(r), pdev->name);
if (!r)
return -EBUSY;
mmc->max_blk_count = 65535;
host = mmc_priv(mmc);
+ host->base = ioremap(r->start, resource_size(r));
+ if (!host->base) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
host->mmc = mmc;
host->dma_allocated = 0;
host->pdata = pdev->dev.platform_data;
+ if (!host->pdata)
+ dev_warn(&pdev->dev, "No platform data provided!\n");
spin_lock_init(&host->lock);
host->res = r;
imx_gpio_mode(PB12_PF_SD_CLK);
imx_gpio_mode(PB13_PF_SD_CMD);
- imxmci_softreset();
+ imxmci_softreset(host);
- if ( MMC_REV_NO != 0x390 ) {
+ rev_no = readw(host->base + MMC_REG_REV_NO);
+ if (rev_no != 0x390) {
dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
- MMC_REV_NO);
+ readw(host->base + MMC_REG_REV_NO));
goto out;
}
- MMC_READ_TO = 0x2db4; /* recommended in data sheet */
+ /* recommended in data sheet */
+ writew(0x2db4, host->base + MMC_REG_READ_TO);
host->imask = IMXMCI_INT_MASK_DEFAULT;
- MMC_INT_MASK = host->imask;
+ writew(host->imask, host->base + MMC_REG_INT_MASK);
host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
if(host->dma < 0) {
ret = -EBUSY;
goto out;
}
- host->dma_allocated=1;
+ host->dma_allocated = 1;
imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
+ RSSR(host->dma) = DMA_REQ_SDHC;
tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
host->status_reg=0;
if (ret)
goto out;
- host->present = host->pdata->card_present(mmc_dev(mmc));
+ if (host->pdata && host->pdata->card_present)
+ host->present = host->pdata->card_present(mmc_dev(mmc));
+ else /* if there is no way to detect assume that card is present */
+ host->present = 1;
+
init_timer(&host->timer);
host->timer.data = (unsigned long)host;
host->timer.function = imxmci_check_status;
add_timer(&host->timer);
- mod_timer(&host->timer, jiffies + (HZ>>1));
+ mod_timer(&host->timer, jiffies + (HZ >> 1));
platform_set_drvdata(pdev, mmc);
out:
if (host) {
- if(host->dma_allocated){
+ if (host->dma_allocated) {
imx_dma_free(host->dma);
- host->dma_allocated=0;
+ host->dma_allocated = 0;
}
if (host->clk) {
clk_disable(host->clk);
clk_put(host->clk);
}
+ if (host->base)
+ iounmap(host->base);
}
if (mmc)
mmc_free_host(mmc);
- release_resource(r);
+ release_mem_region(r->start, resource_size(r));
return ret;
}
-static int imxmci_remove(struct platform_device *pdev)
+static int __exit imxmci_remove(struct platform_device *pdev)
{
struct mmc_host *mmc = platform_get_drvdata(pdev);
mmc_remove_host(mmc);
free_irq(host->irq, host);
- if(host->dma_allocated){
+ iounmap(host->base);
+ if (host->dma_allocated) {
imx_dma_free(host->dma);
- host->dma_allocated=0;
+ host->dma_allocated = 0;
}
tasklet_kill(&host->tasklet);
clk_disable(host->clk);
clk_put(host->clk);
- release_resource(host->res);
+ release_mem_region(host->res->start, resource_size(host->res));
mmc_free_host(mmc);
}
int ret = 0;
if (mmc)
- ret = mmc_suspend_host(mmc, state);
+ ret = mmc_suspend_host(mmc);
return ret;
}
if (mmc) {
host = mmc_priv(mmc);
- if(host)
+ if (host)
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
ret = mmc_resume_host(mmc);
}
#endif /* CONFIG_PM */
static struct platform_driver imxmci_driver = {
- .probe = imxmci_probe,
- .remove = imxmci_remove,
+ .remove = __exit_p(imxmci_remove),
.suspend = imxmci_suspend,
.resume = imxmci_resume,
.driver = {
static int __init imxmci_init(void)
{
- return platform_driver_register(&imxmci_driver);
+ return platform_driver_probe(&imxmci_driver, imxmci_probe);
}
static void __exit imxmci_exit(void)
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff