#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>
+#include <linux/pci.h>
#include <asm/msr.h>
#include <asm/processor.h>
return data;
}
+static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
+{
+ /* The 100C is default for both mobile and non mobile CPUs */
+
+ int tjmax = 100000;
+ int tjmax_ee = 85000;
+ int usemsr_ee = 1;
+ int err;
+ u32 eax, edx;
+ struct pci_dev *host_bridge;
+
+ /* Early chips have no MSR for TjMax */
+
+ if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
+ usemsr_ee = 0;
+ }
+
+ /* Atom CPUs */
+
+ if (c->x86_model == 0x1c) {
+ usemsr_ee = 0;
+
+ host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+
+ if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
+ && (host_bridge->device == 0xa000 /* NM10 based nettop */
+ || host_bridge->device == 0xa010)) /* NM10 based netbook */
+ tjmax = 100000;
+ else
+ tjmax = 90000;
+
+ pci_dev_put(host_bridge);
+ }
+
+ if ((c->x86_model > 0xe) && (usemsr_ee)) {
+ u8 platform_id;
+
+ /* Now we can detect the mobile CPU using Intel provided table
+ http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
+ For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
+ */
+
+ err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
+ if (err) {
+ dev_warn(dev,
+ "Unable to access MSR 0x17, assuming desktop"
+ " CPU\n");
+ usemsr_ee = 0;
+ } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
+ /* Trust bit 28 up to Penryn, I could not find any
+ documentation on that; if you happen to know
+ someone at Intel please ask */
+ usemsr_ee = 0;
+ } else {
+ /* Platform ID bits 52:50 (EDX starts at bit 32) */
+ platform_id = (edx >> 18) & 0x7;
+
+ /* Mobile Penryn CPU seems to be platform ID 7 or 5
+ (guesswork) */
+ if ((c->x86_model == 0x17) &&
+ ((platform_id == 5) || (platform_id == 7))) {
+ /* If MSR EE bit is set, set it to 90 degrees C,
+ otherwise 105 degrees C */
+ tjmax_ee = 90000;
+ tjmax = 105000;
+ }
+ }
+ }
+
+ if (usemsr_ee) {
+
+ err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
+ if (err) {
+ dev_warn(dev,
+ "Unable to access MSR 0xEE, for Tjmax, left"
+ " at default\n");
+ } else if (eax & 0x40000000) {
+ tjmax = tjmax_ee;
+ }
+ /* if we dont use msr EE it means we are desktop CPU (with exeception
+ of Atom) */
+ } else if (tjmax == 100000) {
+ dev_warn(dev, "Using relative temperature scale!\n");
+ }
+
+ return tjmax;
+}
+
static int __devinit coretemp_probe(struct platform_device *pdev)
{
struct coretemp_data *data;
data->id = pdev->id;
data->name = "coretemp";
mutex_init(&data->update_lock);
- /* Tjmax default is 100 degrees C */
- data->tjmax = 100000;
/* test if we can access the THERM_STATUS MSR */
err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
}
}
- /* Some processors have Tjmax 85 following magic should detect it
- Intel won't disclose the information without signed NDA, but
- individuals cannot sign it. Catch(ed) 22.
- */
-
- if (((c->x86_model == 0xf) && (c->x86_mask > 3)) ||
- (c->x86_model == 0xe)) {
- err = rdmsr_safe_on_cpu(data->id, 0xee, &eax, &edx);
- if (err) {
- dev_warn(&pdev->dev,
- "Unable to access MSR 0xEE, Tjmax left at %d "
- "degrees C\n", data->tjmax/1000);
- } else if (eax & 0x40000000) {
- data->tjmax = 85000;
- }
- }
-
- /* Intel says that above should not work for desktop Core2 processors,
- but it seems to work. There is no other way how get the absolute
- readings. Warn the user about this. First check if are desktop,
- bit 50 of MSR_IA32_PLATFORM_ID should be 0.
- */
-
- rdmsr_safe_on_cpu(data->id, MSR_IA32_PLATFORM_ID, &eax, &edx);
-
- if ((c->x86_model == 0xf) && (!(edx & 0x00040000))) {
- dev_warn(&pdev->dev, "Using undocumented features, absolute "
- "temperature might be wrong!\n");
- }
-
+ data->tjmax = adjust_tjmax(c, data->id, &pdev->dev);
platform_set_drvdata(pdev, data);
/* read the still undocumented IA32_TEMPERATURE_TARGET it exists
- on older CPUs but not in this register */
+ on older CPUs but not in this register, Atoms don't have it either */
- if (c->x86_model > 0xe) {
+ if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
err = rdmsr_safe_on_cpu(data->id, 0x1a2, &eax, &edx);
if (err) {
dev_warn(&pdev->dev, "Unable to read"
for_each_online_cpu(i) {
struct cpuinfo_x86 *c = &cpu_data(i);
+ /*
+ * CPUID.06H.EAX[0] indicates whether the CPU has thermal
+ * sensors. We check this bit only, all the early CPUs
+ * without thermal sensors will be filtered out.
+ */
+ if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
+ err = coretemp_device_add(i);
+ if (err)
+ goto exit_devices_unreg;
- /* check if family 6, models e, f, 16 */
- if ((c->cpuid_level < 0) || (c->x86 != 0x6) ||
- !((c->x86_model == 0xe) || (c->x86_model == 0xf) ||
- (c->x86_model == 0x16))) {
-
- /* supported CPU not found, but report the unknown
- family 6 CPU */
- if ((c->x86 == 0x6) && (c->x86_model > 0xf))
- printk(KERN_WARNING DRVNAME ": Unknown CPU "
- "model %x\n", c->x86_model);
- continue;
+ } else {
+ printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
+ " has no thermal sensor.\n", c->x86_model);
}
-
- err = coretemp_device_add(i);
- if (err)
- goto exit_devices_unreg;
}
if (list_empty(&pdev_list)) {
err = -ENODEV;
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff