drm/radeon/kms: expose thermal/fan i2c buses

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / rv515.c

diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 41a34c2..f85499f 100644 (file)
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -29,6 +29,7 @@
 #include "drmP.h"
 #include "rv515d.h"
 #include "radeon.h"
+#include "radeon_asic.h"
 #include "atom.h"
 #include "rv515_reg_safe.h"
 
@@ -277,13 +278,15 @@ static void rv515_vram_get_type(struct radeon_device *rdev)
        }
 }
 
-void rv515_vram_info(struct radeon_device *rdev)
+void rv515_mc_init(struct radeon_device *rdev)
 {
        fixed20_12 a;
 
        rv515_vram_get_type(rdev);
-
        r100_vram_init_sizes(rdev);
+       radeon_vram_location(rdev, &rdev->mc, 0);
+       if (!(rdev->flags & RADEON_IS_AGP))
+               radeon_gtt_location(rdev, &rdev->mc);
        /* FIXME: we should enforce default clock in case GPU is not in
         * default setup
         */
@@ -380,7 +383,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
        save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
 
        /* Stop all video */
-       WREG32(R_000330_D1VGA_CONTROL, 0);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
        WREG32(R_000300_VGA_RENDER_CONTROL, 0);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -389,6 +391,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
        WREG32(R_006880_D2CRTC_CONTROL, 0);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
+       WREG32(R_000330_D1VGA_CONTROL, 0);
+       WREG32(R_000338_D2VGA_CONTROL, 0);
 }
 
 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -402,14 +406,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
        WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
        mdelay(1);
        /* Restore video state */
+       WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
+       WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
        WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
        WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
        WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
        WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
-       WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
-       WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
        WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 }
 
@@ -477,8 +481,8 @@ static int rv515_startup(struct radeon_device *rdev)
                        return r;
        }
        /* Enable IRQ */
-       rdev->irq.sw_int = true;
        rs600_irq_set(rdev);
+       rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
        /* 1M ring buffer */
        r = r100_cp_init(rdev, 1024 * 1024);
        if (r) {
@@ -513,6 +517,8 @@ int rv515_resume(struct radeon_device *rdev)
        atom_asic_init(rdev->mode_info.atom_context);
        /* Resume clock after posting */
        rv515_clock_startup(rdev);
+       /* Initialize surface registers */
+       radeon_surface_init(rdev);
        return rv515_startup(rdev);
 }
 
@@ -534,16 +540,16 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 
 void rv515_fini(struct radeon_device *rdev)
 {
-       rv515_suspend(rdev);
+       radeon_pm_fini(rdev);
        r100_cp_fini(rdev);
        r100_wb_fini(rdev);
        r100_ib_fini(rdev);
        radeon_gem_fini(rdev);
-    rv370_pcie_gart_fini(rdev);
+       rv370_pcie_gart_fini(rdev);
        radeon_agp_fini(rdev);
        radeon_irq_kms_fini(rdev);
        radeon_fence_driver_fini(rdev);
-       radeon_object_fini(rdev);
+       radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
        kfree(rdev->bios);
        rdev->bios = NULL;
@@ -579,18 +585,21 @@ int rv515_init(struct radeon_device *rdev)
                        RREG32(R_0007C0_CP_STAT));
        }
        /* check if cards are posted or not */
-       if (!radeon_card_posted(rdev) && rdev->bios) {
-               DRM_INFO("GPU not posted. posting now...\n");
-               atom_asic_init(rdev->mode_info.atom_context);
-       }
+       if (radeon_boot_test_post_card(rdev) == false)
+               return -EINVAL;
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
-       /* Get vram informations */
-       rv515_vram_info(rdev);
-       /* Initialize memory controller (also test AGP) */
-       r = r420_mc_init(rdev);
-       if (r)
-               return r;
+       /* Initialize power management */
+       radeon_pm_init(rdev);
+       /* initialize AGP */
+       if (rdev->flags & RADEON_IS_AGP) {
+               r = radeon_agp_init(rdev);
+               if (r) {
+                       radeon_agp_disable(rdev);
+               }
+       }
+       /* initialize memory controller */
+       rv515_mc_init(rdev);
        rv515_debugfs(rdev);
        /* Fence driver */
        r = radeon_fence_driver_init(rdev);
@@ -600,7 +609,7 @@ int rv515_init(struct radeon_device *rdev)
        if (r)
                return r;
        /* Memory manager */
-       r = radeon_object_init(rdev);
+       r = radeon_bo_init(rdev);
        if (r)
                return r;
        r = rv370_pcie_gart_init(rdev);
@@ -612,13 +621,12 @@ int rv515_init(struct radeon_device *rdev)
        if (r) {
                /* Somethings want wront with the accel init stop accel */
                dev_err(rdev->dev, "Disabling GPU acceleration\n");
-               rv515_suspend(rdev);
                r100_cp_fini(rdev);
                r100_wb_fini(rdev);
                r100_ib_fini(rdev);
+               radeon_irq_kms_fini(rdev);
                rv370_pcie_gart_fini(rdev);
                radeon_agp_fini(rdev);
-               radeon_irq_kms_fini(rdev);
                rdev->accel_working = false;
        }
        return 0;
@@ -889,8 +897,9 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 
        b.full = rfixed_const(mode->crtc_hdisplay);
        c.full = rfixed_const(256);
-       a.full = rfixed_mul(wm->num_line_pair, b);
-       request_fifo_depth.full = rfixed_div(a, c);
+       a.full = rfixed_div(b, c);
+       request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
+       request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
        if (a.full < rfixed_const(4)) {
                wm->lb_request_fifo_depth = 4;
        } else {
@@ -992,15 +1001,17 @@ void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
        a.full = rfixed_const(16);
        wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
        wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
+       wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
 
        /* Determine estimated width */
        estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
        estimated_width.full = rfixed_div(estimated_width, consumption_time);
        if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
-               wm->priority_mark.full = rfixed_const(10);
+               wm->priority_mark.full = wm->priority_mark_max.full;
        } else {
                a.full = rfixed_const(16);
                wm->priority_mark.full = rfixed_div(estimated_width, a);
+               wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
                wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
        }
 }