drm: move radeon_fixed.h to shared drm_fixed.h header

[safe/jmp/linux-2.6] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c

diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 6432517..7701d42 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -26,7 +26,7 @@
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
-#include "radeon_fixed.h"
+#include <drm/drm_fixed.h>
 #include "radeon.h"
 #include "atom.h"
 
@@ -323,6 +323,7 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
                }
                drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
                radeon_crtc_load_lut(crtc);
+               radeon_crtc->enabled = true;
                break;
        case DRM_MODE_DPMS_STANDBY:
        case DRM_MODE_DPMS_SUSPEND:
@@ -335,8 +336,12 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
                                                                                    RADEON_CRTC_DISP_REQ_EN_B));
                        WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
                }
+               radeon_crtc->enabled = false;
                break;
        }
+
+       /* adjust pm to dpms change */
+       radeon_pm_compute_clocks(rdev);
 }
 
 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
@@ -603,6 +608,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                                      ? RADEON_CRTC2_INTERLACE_EN
                                      : 0));
 
+               /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
+               if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
+                       crtc2_gen_cntl |= RADEON_CRTC2_EN;
+
                disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
                disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 
@@ -630,6 +639,10 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                                    ? RADEON_CRTC_INTERLACE_EN
                                    : 0));
 
+               /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
+               if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
+                       crtc_gen_cntl |= RADEON_CRTC_EN;
+
                crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
                crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
                                  RADEON_CRTC_VSYNC_DIS |
@@ -703,7 +716,10 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
                pll = &rdev->clock.p1pll;
 
        pll->flags = RADEON_PLL_LEGACY;
-       pll->algo = PLL_ALGO_LEGACY;
+       if (radeon_new_pll == 1)
+               pll->algo = PLL_ALGO_NEW;
+       else
+               pll->algo = PLL_ALGO_LEGACY;
 
        if (mode->clock > 200000) /* range limits??? */
                pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
@@ -955,6 +971,12 @@ static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
                                   struct drm_display_mode *mode,
                                   struct drm_display_mode *adjusted_mode)
 {
+       struct drm_device *dev = crtc->dev;
+       struct radeon_device *rdev = dev->dev_private;
+
+       /* adjust pm to upcoming mode change */
+       radeon_pm_compute_clocks(rdev);
+
        if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
                return false;
        return true;