include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...

[safe/jmp/linux-2.6] / drivers / gpio / langwell_gpio.c

diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/langwell_gpio.c
index 5711ce5..00c3a14 100644 (file)
--- a/drivers/gpio/langwell_gpio.c
+++ b/drivers/gpio/langwell_gpio.c
@@ -29,6 +29,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/slab.h>
 
 struct lnw_gpio_register {
        u32     GPLR[2];
@@ -123,7 +124,7 @@ static int lnw_irq_type(unsigned irq, unsigned type)
        void __iomem *grer = (void __iomem *)(&lnw->reg_base->GRER[reg]);
        void __iomem *gfer = (void __iomem *)(&lnw->reg_base->GFER[reg]);
 
-       if (gpio < 0 || gpio > lnw->chip.ngpio)
+       if (gpio >= lnw->chip.ngpio)
                return -EINVAL;
        spin_lock_irqsave(&lnw->lock, flags);
        if (type & IRQ_TYPE_EDGE_RISING)
@@ -144,13 +145,6 @@ static int lnw_irq_type(unsigned irq, unsigned type)
 
 static void lnw_irq_unmask(unsigned irq)
 {
-       struct lnw_gpio *lnw = get_irq_chip_data(irq);
-       u32 gpio = irq - lnw->irq_base;
-       u8 reg = gpio / 32;
-       void __iomem *gedr;
-
-       gedr = (void __iomem *)(&lnw->reg_base->GEDR[reg]);
-       writel(BIT(gpio % 32), gedr);
 };
 
 static void lnw_irq_mask(unsigned irq)
@@ -183,13 +177,11 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
                gedr_v = readl(gedr);
                if (!gedr_v)
                        continue;
-               for (gpio = reg*32; gpio < reg*32+32; gpio++) {
-                       gedr_v = readl(gedr);
+               for (gpio = reg*32; gpio < reg*32+32; gpio++)
                        if (gedr_v & BIT(gpio % 32)) {
                                pr_debug("pin %d triggered\n", gpio);
                                generic_handle_irq(lnw->irq_base + gpio);
                        }
-               }
                /* clear the edge detect status bit */
                writel(gedr_v, gedr);
        }