/**
* @file nmi_int.c
*
- * @remark Copyright 2002 OProfile authors
+ * @remark Copyright 2002-2008 OProfile authors
* @remark Read the file COPYING
*
* @author John Levon <levon@movementarian.org>
+ * @author Robert Richter <robert.richter@amd.com>
*/
#include <linux/init.h>
#include "op_counter.h"
#include "op_x86_model.h"
+DEFINE_PER_CPU(int, switch_index);
+
static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
static void nmi_stop(void);
static void nmi_cpu_start(void *dummy);
static void nmi_cpu_stop(void *dummy);
+static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs);
+static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs);
/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */
+static void nmi_cpu_switch(void *dummy)
+{
+ int cpu = smp_processor_id();
+ int si = per_cpu(switch_index, cpu);
+ struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
+
+ nmi_cpu_stop(NULL);
+ nmi_cpu_save_mpx_registers(msrs);
+
+ /* move to next set */
+ si += model->num_hardware_counters;
+ if ((si > model->num_counters) || (counter_config[si].count == 0))
+ per_cpu(switch_index, smp_processor_id()) = 0;
+ else
+ per_cpu(switch_index, smp_processor_id()) = si;
+
+ nmi_cpu_restore_mpx_registers(msrs);
+ model->setup_ctrs(msrs);
+ nmi_cpu_start(NULL);
+}
+
+/*
+ * Quick check to see if multiplexing is necessary.
+ * The check should be sufficient since counters are used
+ * in ordre.
+ */
+static int nmi_multiplex_on(void)
+{
+ return counter_config[model->num_hardware_counters].count ? 0 : -EINVAL;
+}
+
+static int nmi_switch_event(void)
+{
+ if (nmi_multiplex_on() < 0)
+ return -EINVAL;
+
+ on_each_cpu(nmi_cpu_switch, NULL, 1);
+
+ return 0;
+}
+
static int profile_exceptions_notify(struct notifier_block *self,
unsigned long val, void *data)
{
static int allocate_msrs(void)
{
- int success = 1;
+ int i, success = 1;
size_t controls_size = sizeof(struct op_msr) * model->num_controls;
size_t counters_size = sizeof(struct op_msr) * model->num_counters;
- int i;
for_each_possible_cpu(i) {
per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
GFP_KERNEL);
success = 0;
break;
}
- per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
- GFP_KERNEL);
+ per_cpu(cpu_msrs, i).controls =
+ kmalloc(controls_size, GFP_KERNEL);
if (!per_cpu(cpu_msrs, i).controls) {
success = 0;
break;
return err;
}
- /* We need to serialize save and setup for HT because the subset
+ /*
+ * We need to serialize save and setup for HT because the subset
* of msrs are distinct for save and setup operations
*/
per_cpu(cpu_msrs, 0).controls,
sizeof(struct op_msr) * model->num_controls);
}
-
}
on_each_cpu(nmi_save_registers, NULL, 1);
on_each_cpu(nmi_cpu_setup, NULL, 1);
return 0;
}
-static void nmi_restore_registers(struct op_msrs *msrs)
+static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
+{
+ unsigned int si = __get_cpu_var(switch_index);
+ unsigned int const nr_ctrs = model->num_hardware_counters;
+ struct op_msr *counters = &msrs->counters[si];
+ unsigned int i;
+
+ for (i = 0; i < nr_ctrs; ++i) {
+ int offset = i + si;
+ if (counters[offset].addr) {
+ rdmsr(counters[offset].addr,
+ counters[offset].multiplex.low,
+ counters[offset].multiplex.high);
+ }
+ }
+}
+
+static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
+{
+ unsigned int si = __get_cpu_var(switch_index);
+ unsigned int const nr_ctrs = model->num_hardware_counters;
+ struct op_msr *counters = &msrs->counters[si];
+ unsigned int i;
+
+ for (i = 0; i < nr_ctrs; ++i) {
+ int offset = i + si;
+ if (counters[offset].addr) {
+ wrmsr(counters[offset].addr,
+ counters[offset].multiplex.low,
+ counters[offset].multiplex.high);
+ }
+ }
+}
+
+static void nmi_cpu_restore_registers(struct op_msrs *msrs)
{
unsigned int const nr_ctrs = model->num_counters;
unsigned int const nr_ctrls = model->num_controls;
apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
apic_write(APIC_LVTERR, v);
- nmi_restore_registers(msrs);
+ nmi_cpu_restore_registers(msrs);
+ __get_cpu_var(switch_index) = 0;
}
static void nmi_shutdown(void)
oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
+ counter_config[i].save_count_low = 0;
}
return 0;
__u8 vendor = boot_cpu_data.x86_vendor;
__u8 family = boot_cpu_data.x86;
char *cpu_type;
+ int ret = 0;
if (!cpu_has_apic)
return -ENODEV;
default:
return -ENODEV;
case 6:
- model = &op_athlon_spec;
+ model = &op_amd_spec;
cpu_type = "i386/athlon";
break;
case 0xf:
- model = &op_athlon_spec;
+ model = &op_amd_spec;
/* Actually it could be i386/hammer too, but give
user space an consistent name. */
cpu_type = "x86-64/hammer";
break;
case 0x10:
- model = &op_athlon_spec;
+ model = &op_amd_spec;
cpu_type = "x86-64/family10";
break;
+ case 0x11:
+ model = &op_amd_spec;
+ cpu_type = "x86-64/family11h";
+ break;
}
break;
return -ENODEV;
}
- init_sysfs();
#ifdef CONFIG_SMP
register_cpu_notifier(&oprofile_cpu_nb);
#endif
- using_nmi = 1;
+ /* default values, can be overwritten by model */
+ __raw_get_cpu_var(switch_index) = 0;
ops->create_files = nmi_create_files;
ops->setup = nmi_setup;
ops->shutdown = nmi_shutdown;
ops->start = nmi_start;
ops->stop = nmi_stop;
ops->cpu_type = cpu_type;
+ ops->switch_events = nmi_switch_event;
+
+ if (model->init)
+ ret = model->init(ops);
+ if (ret)
+ return ret;
+
+ init_sysfs();
+ using_nmi = 1;
printk(KERN_INFO "oprofile: using NMI interrupt.\n");
return 0;
}
#ifdef CONFIG_SMP
unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
+ if (model->exit)
+ model->exit();
}
}
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff