MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms

[safe/jmp/linux-2.6] / arch / mips / kernel / irq-msc01.c

diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 71e8e45..6a8cd28 100644 (file)
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -1,21 +1,23 @@
 /*
- * Copyright (c) 2004 MIPS Inc
- * Author: chris@mips.com
- *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
+ *
+ * Copyright (c) 2004 MIPS Inc
+ * Author: chris@mips.com
+ *
+ * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
  */
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <asm/ptrace.h>
 #include <linux/sched.h>
 #include <linux/kernel_stat.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/msc01_ic.h>
+#include <asm/traps.h>
 
 static unsigned long _icctrl_msc;
 #define MSC01_IC_REG_BASE      _icctrl_msc
@@ -44,31 +46,6 @@ static inline void unmask_msc_irq(unsigned int irq)
 }
 
 /*
- * Enables the IRQ on SOC-it
- */
-static void enable_msc_irq(unsigned int irq)
-{
-       unmask_msc_irq(irq);
-}
-
-/*
- * Initialize the IRQ on SOC-it
- */
-static unsigned int startup_msc_irq(unsigned int irq)
-{
-       unmask_msc_irq(irq);
-       return 0;
-}
-
-/*
- * Disables the IRQ on SOC-it
- */
-static void disable_msc_irq(unsigned int irq)
-{
-       mask_msc_irq(irq);
-}
-
-/*
  * Masks and ACKs an IRQ
  */
 static void level_mask_and_ack_msc_irq(unsigned int irq)
@@ -76,11 +53,8 @@ static void level_mask_and_ack_msc_irq(unsigned int irq)
        mask_msc_irq(irq);
        if (!cpu_has_veic)
                MSCIC_WRITE(MSC01_IC_EOI, 0);
-#ifdef CONFIG_MIPS_MT_SMTC
        /* This actually needs to be a call into platform code */
-       if (irq_hwmask[irq] & ST0_IM)
-               set_c0_status(irq_hwmask[irq] & ST0_IM);
-#endif /* CONFIG_MIPS_MT_SMTC */
+       smtc_im_ack_irq(irq);
 }
 
 /*
@@ -97,10 +71,7 @@ static void edge_mask_and_ack_msc_irq(unsigned int irq)
                MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
                MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
        }
-#ifdef CONFIG_MIPS_MT_SMTC
-       if (irq_hwmask[irq] & ST0_IM)
-               set_c0_status(irq_hwmask[irq] & ST0_IM);
-#endif /* CONFIG_MIPS_MT_SMTC */
+       smtc_im_ack_irq(irq);
 }
 
 /*
@@ -128,41 +99,36 @@ void ll_msc_irq(void)
        }
 }
 
-void
-msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
+static void msc_bind_eic_interrupt(int irq, int set)
 {
        MSCIC_WRITE(MSC01_IC_RAMW,
                    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
 }
 
-#define shutdown_msc_irq       disable_msc_irq
-
-struct irq_chip msc_levelirq_type = {
-       .typename = "SOC-it-Level",
-       .startup = startup_msc_irq,
-       .shutdown = shutdown_msc_irq,
-       .enable = enable_msc_irq,
-       .disable = disable_msc_irq,
+static struct irq_chip msc_levelirq_type = {
+       .name = "SOC-it-Level",
        .ack = level_mask_and_ack_msc_irq,
+       .mask = mask_msc_irq,
+       .mask_ack = level_mask_and_ack_msc_irq,
+       .unmask = unmask_msc_irq,
+       .eoi = unmask_msc_irq,
        .end = end_msc_irq,
 };
 
-struct irq_chip msc_edgeirq_type = {
-       .typename = "SOC-it-Edge",
-       .startup =startup_msc_irq,
-       .shutdown = shutdown_msc_irq,
-       .enable = enable_msc_irq,
-       .disable = disable_msc_irq,
+static struct irq_chip msc_edgeirq_type = {
+       .name = "SOC-it-Edge",
        .ack = edge_mask_and_ack_msc_irq,
+       .mask = mask_msc_irq,
+       .mask_ack = edge_mask_and_ack_msc_irq,
+       .unmask = unmask_msc_irq,
+       .eoi = unmask_msc_irq,
        .end = end_msc_irq,
 };
 
 
-void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
+void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
 {
-       extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
-
-       _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);
+       _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
 
        /* Reset interrupt controller - initialises all registers to 0 */
        MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
@@ -174,14 +140,16 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
 
                switch (imp->im_type) {
                case MSC01_IRQ_EDGE:
-                       irq_desc[base+n].chip = &msc_edgeirq_type;
+                       set_irq_chip_and_handler_name(irqbase + n,
+                               &msc_edgeirq_type, handle_edge_irq, "edge");
                        if (cpu_has_veic)
                                MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
                        else
                                MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
                        break;
                case MSC01_IRQ_LEVEL:
-                       irq_desc[base+n].chip = &msc_levelirq_type;
+                       set_irq_chip_and_handler_name(irqbase+n,
+                               &msc_levelirq_type, handle_level_irq, "level");
                        if (cpu_has_veic)
                                MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
                        else
@@ -189,7 +157,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
                }
        }
 
-       irq_base = base;
+       irq_base = irqbase;
 
        MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);     /* Enable interrupt generation */